CN101083284B - 具有槽电荷补偿区的半导体器件及方法 - Google Patents

具有槽电荷补偿区的半导体器件及方法 Download PDF

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CN101083284B
CN101083284B CN2007101064655A CN200710106465A CN101083284B CN 101083284 B CN101083284 B CN 101083284B CN 2007101064655 A CN2007101064655 A CN 2007101064655A CN 200710106465 A CN200710106465 A CN 200710106465A CN 101083284 B CN101083284 B CN 101083284B
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杜尚晖
乔丹·M.·格里弗纳
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Semiconductor Components Industries LLC
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Abstract

具有槽电荷补偿区的半导体器件和方法。在一个实施例中，半导体器件成形为具有电荷补偿槽，该电荷补偿槽邻近该器件的沟道区。电荷补偿槽包括至少两个相反导电类型的半导体层。沟道连接区将沟道区电连接到至少两个相反导电类型的半导体层中的一个。

Description

具有槽电荷补偿区的半导体器件及方法
技术领域
本发明一般涉及半导体器件，更具体地是涉及功率开关器件及其制造方法。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是功率开关器件的常用类型。MOSFET器件包括源区、漏区、在源区和漏区之间延伸的沟道区以及邻近沟道区的栅结构。栅结构包括导电栅电极层，该栅电极层邻近沟道区且与沟道区被薄的电介质层隔开。
当MOSFET处于开态时，电压施加在栅结构上以在源区和漏区之间形成导电沟道区，从而允许电流流过该器件。当处于截止态时，施加在沟道区上的任何电压都充分地小以致不能形成导电沟道，从而不能产生电流。在截止态时，器件必须支持源极和漏极之间的高电压。
当今的高压功率开关市场由两个主要参数驱动：击穿电压(BVdss)和开态电阻(Rdson)。对具体应用，需要最小击穿电压，并且在实际中，设计者通常能满足BVdss规格。然而这通常是以Rdson为代价的。这种性能的平衡对于高压功率开关器件的制造者和使用者是一主要设计挑战。
最近，超结(super junction)器件改善了Rdson和BVdss之间的平衡折衷，大受欢迎。在常规n沟道超结器件中，多个重掺杂扩散n型和p型区域替代了轻掺杂n型外延区。在开态下，电流流过重掺杂n型区域，降低了Rdson。在截止态或闭锁状态，重掺杂n型和p型区域耗尽或相互补偿以提供高的BVdss。尽管超结器件看上去很有前途，但在制造方面仍有很大的挑战性。
当前的高压功率开关器件的另一个问题是它们通常需要一大的输入(比如，栅或控制电极)电荷来从一个状态转换到另一个状态。这种要求，除了别的之外，还在外围控制电路上加上一额外负担。
发明内容
因此，需要能提供低Rdson、高BVdss且能减少输入电荷的高压功率开关器件结构和制造方法。
一种半导体器件，其特征在于具有半导体材料区，半导体材料区半导体材料区具有第一主表面。槽补偿区，其在所述半导体材料区内形成并从所述第一主表面延伸。所述槽补偿区的特征在于包括多个相反导电类型的半导体层。体区在所述半导体材料区内形成。源区在所述体区内形成且与所述槽补偿区横向分隔开。栅结构在所述源区和所述槽补偿区之间形成，并且所述栅结构包括导电栅区，所述导电栅区设置为使得当所述器件在工作的时候在所述体区内建立沟道区。沟道连接区在所述槽补偿区的上部部分形成，并且设置为使得当所述器件在工作的时候将所述沟道区电连接到所述槽补偿区。
一种形成半导体器件的方法，其特征在于提供具有第一主表面的半导体材料区的步骤。所述方法包括在所述半导体材料区内形成从所述第一主表面延伸的槽的步骤。所述方法包括在所述槽内形成多个半导体层的步骤，多个半导体层包括至少两个相反导电类型的半导体层以及至少一个缓冲层，所述缓冲层分隔所述至少两个相反导电类型的半导体层以形成填充槽补偿区。其中在形成的时候，所述缓冲层的特征在于掺杂浓度比所述至少两个相反导电类型的半导体层的掺杂浓度低。所述方法包括形成控制电极，其覆在所述第一主表面上面，且其与所述填充槽补偿区横向分隔开，所述控制电极设置为使得在工作的时候在所述半导体材料区形成沟道。所述方法包括至少部分地在所述填充槽补偿区内形成第一掺杂区，所述第一掺杂区设置为使得在工作的时候将所述沟道区电连接到所述填充槽补偿区。
附图说明
图1为依据本发明的半导体器件的放大的部分截面图；
图2至图9为图1中的半导体器件在不同制造阶段的放大的部分截面图；
图10为依据本发明的另一个实施例的半导体器件的一部分的高倍放大的部分截面图；以及
图11为依据本发明的另一个实施例的半导体器件的一部分的高倍放大的部分截面图。
为了简明清晰的表示，图中元件末必按比例绘制，并且不同图中的相同参考编号表示相同元件。另外，为了简化描述，省略了众所周知的步骤和元件的描述和详细信息。此处使用的载流电极是指器件的元件，其承载流过所述器件的电流，比如MOS晶体管的源极或漏极、双极晶体管的发射极或集电极，或二极管的阴极或阳极，控制电极是指器件的元件，其控制电流流过所述器件，比如，MOS晶体管的栅极或双极晶体管的基极。尽管此处阐述的器件是某些N沟道或P沟道器件，本领域的技术人员应当明白根据本发明互补的器件也是可以的。为了附图的清晰，器件结构的掺杂区表示成具有直线边缘和精确角度的拐角。然而，本领域的技术人员应当明白由于掺杂物的扩散和活性，掺杂区一般不是直线且拐角不是有精确角度的。
另外，本发明的器件可体现为单元式设计(其中主体区是多个单元式区域)或单体设计(其中主体区包括单一区域，其由细长的图案，典型地由蛇形的图案形成)。然而，在整个描述中，为了容易理解起见，本发明的器件将被描述成单元式设计。应当理解，我们要求本发明即包括单元式设计又包括单体设计。
具体实施方式
图1为依据本发明实施例的绝缘栅场效应晶体管(IGFET)、MOSFET、超结器件或开关器件或单元10的部分截面图。作为举例，器件10是作为功率集成电路的一部分与逻辑和/或其它元件一起集成进半导体芯片的多个器件中的之一。或者，器件10是集成在一起以形成分立式晶体管器件的多个器件中之一。
器件10包括半导体材料区11，其包括，比如n型硅基片12，硅型基片12具有范围在大约0.001至大约0.005欧姆-厘米(ohm-cm)之内的电阻率，并且可掺杂有砷。在所示的实施例中，基片12设置有用于器件10的漏区，漏区连接到导电层13。在基片12内或在基片12上形成半导体层14，且依据本发明，半导体层14是n型或p型的并且掺杂的足够轻以致于不影响以下将要描述的槽补偿区的电荷平衡。在一个实施例中，层14是用常规外延生长工艺形成的。在一适用于600伏(volt)器件的实施例中，层14是n型掺杂或p型掺杂，其掺杂浓度是大约1.0×1013原子/厘米3(atoms/cm3)至大约1.0×1014原子/厘米3(atoms/cm3)且厚度是大约40微米至大约60微米。层14厚度的增加或减少依赖于器件10的期望的BVdss  额定值。在一可选实施例中，半导体层14包括渐次变化的掺杂分布，其中半导体层14具有较高的接近于基片12的掺杂浓度并逐渐或突然地过渡到较低的浓度，以平衡半导体层14的厚度。其它材料包括硅-锗、硅-锗-碳、掺碳硅、III-V材料或之类的都可用于半导体材料11的主体或其中的一部分。
依据本发明，器件10进一步包括间隔分开的填充槽、半导体材料填充槽、外延填充区或槽、电荷补偿槽区、深槽电荷补偿区、电荷补偿填充槽或电荷补偿区22。电荷补偿填充槽22包括多个层或多重半导体材料，包括相反导电类型的层，其优选地被一个或多个本征半导体或缓冲半导体层隔开。该本征层，除了其它作用外，起防止或减少相反导电类型层(即，两个电荷层)的内部混杂的作用，而这种内部混杂会对器件10在开态时的导电效率有负面影响。如此处所用到的，电荷补偿通常是指相反导电类型层的总电荷被基本平衡或相等。
在一实施例中，填充槽22包括用单晶(即，非多晶的)外延生长工艺形成的半导体材料的多层或叠层。比如，填充槽22包括p型层23，p型层在槽壁或邻近半导体材料体11的表面上、上方或其毗邻形成。本征半导体或缓冲层24在p型层23上、上方或其毗邻形成，n型层26在本征半导体层24上、上方或其毗邻形成，以及本征半导体或缓冲层27在n型层26上、上方或其毗邻形成。本征层24，除了其它作用外，起防止或减少层23和层26的掺杂物相互混杂的作用，这一点，如前所述的一样，改进了器件10的导电效率。本征层27，除了其它作用外，起填充和部分填充槽的作用。对于n沟道器件，以及依据本发明，在器件10处于开态时，n型层26提供了从沟道到漏极的主要垂直低电阻电流通道。当器件10处于截止态时，依据本发明，p型层23和n型层26相互补偿以提供增加的BVdss特性。应当明白，还可以用附加的n型层和p型层，且它们之间优选地用附加的本征或缓冲层隔开。在一可选实施例中以及如图1所示，电介质层28形成并覆盖最外面(比如，层26和层27)。在一个实施例中，电介质层28填充槽22内的剩余空间。在另一实施例中，电介质层28只部分填充槽22的剩余部分，比如，留下一气隙。作为举例，电介质层28包括氧化物或氮化物或它们的组合。在另一实施例中，电介质层28包括覆盖有薄的多晶硅层的热氧化物，且随之有淀积TEOS层。据观察在一些应用中，覆盖有多晶硅的薄的氧化物减少了来自淀积氧化物的剪应力，因此改进了器件的性能。还应当明白，在热处理的过程中，来自层26和层23的n型和p型掺杂物扩散进缓冲层，这些个别缓冲层可能会也可能不会出现在最终的器件中。然而，当淀积或成形的时候，缓冲层24和/或缓冲层27的掺杂浓度比层23和层26的掺杂浓度低。
作为举例，p型层23和n型层26各自的掺杂浓度为大约9.0×1016至大约3.0×1016原子/厘米3，且每个层的厚度分别在大约0.1微米至大约0.3微米。在一实施例中，本征半导体或缓冲层24和27是不掺杂或轻掺杂的p型的，掺杂浓度小于大约1.0×1014原子/厘米3且每层的厚度为大约0.5微米至大约1.0微米。层27的厚度会被调整以填充槽的剩余部分，比如，当不用电介质层28的时候。
依据本发明，来自p型层23的掺杂物扩散进半导体层14形成p型区或横向掺杂或扩散区域23(描绘成虚线)。从邻近槽22横向扩散的p型区231或者完全合并在一起或者如图1所示的不完全合并，使得半导体14的一部分仍然会出现在成品器件中。也就是说，相邻的横向扩散区231之间的实际扩散距离是可变的。
依据本发明，在一个实施例中，扩散区231包括与半导体14导电性相反的导电类型。该实施例提供一种独特的结构，其中有源器件结构和边缘终端结构(末显示)形成在相同的层中(即，层14)，但是由于横向扩散区域231，有源器件(即，器件10)是在p型层里，而边缘终端结构形成在n型层14里，与槽22横向分隔开。
尽管没有显示，应该理解在器件10形成的时候，来自重掺杂基片12中的n型掺杂物扩散进填充槽22的较低部分，使得基片12内的填充槽22的这些部分变成了更重掺杂的n型。
器件10也包括体或掺杂区31，形成于半导体层14内，在填充槽22之间且接近或邻近或毗邻填充槽22，并从半导体材料体11的主表面18延伸。在一个实施例中，体区31在缓冲层24内横向终止，且不横向延伸进或反掺杂n型区27。在一个实施例中，体区31包括p型导电性，且掺杂浓度适合于形成反型层，该反型层作为器件10的导电沟道45工作。体区31从主表面18延伸至大约1.0到大约5.0微米的深度。n型源区33在体区31内形成，且其从主表面18延伸至大约0.2微米到大约0.5微米的深度。一个或更多个p型体接触区36在体区31内形成，部分地在源区33内和/或在源区33之下。体接触区36设置为能对体区31提供较低的接触电阻，并且降低在源区33之下的体区31的薄层电阻，这就抑制了寄生双极效应。
依据本发明，器件10进一步包括n型覆盖区、沟道连接或漏延伸区32，其形成在填充槽22的上部。在一个实施例中，沟道连接区32在主表面18毗邻形成，且有与源区33一样的掺杂浓度和结深度且如以下将要结合图2至图9描述的，可方便地同时形成。依据本发明，沟道连接区32设置为将沟道区45连接或电连接到填充槽22。在一个实施例中且如图1所示的，器件10也包括n型轻掺杂源区37和轻掺杂漏区39，轻掺杂源区37毗邻、邻近或并置于源区33，轻掺杂漏区39毗邻、邻近或并置于沟道连接区32。作为举例，轻掺杂源区37和轻掺杂漏区的掺杂浓度分别小于源区33和沟道连接区32的掺杂浓度，这一点将结合图2至图9进一步描述。
栅电介质层43在邻近体区31的主平面18之上或其毗邻形成。在一个实施例中，栅电介质层43包括氧化硅，且厚度为大约0.05微米到大约0.1微米。在一可选实施例中，栅电介质层43包括氮化硅、五氧化二钽、二氧化钛、钛酸锶钡或其组合，包括与氧化硅的组合或之类的。
导电栅区57在栅电介质层43之上形成。依据本发明，每个导电栅区57介于在填充槽22和源区33之间。导电栅区57包括，比如，n型多晶硅，且厚度为大约0.3微米到大约0.5微米。导电栅区57和栅电介质层43一起形成器件10的控制电极或栅结构58。栅结构58设置成控制沟道45的成形和器件10内的电流传导。
层间电介质区48在主表面18之上形成并覆在主表面18上，层间电介质区48包括，比如，覆在导电栅区57上形成的第一电介质层51和覆在第一电介质层51及主表面18的其它部分上形成的第二电介质层61。作为举例，电介质层51包括氮化硅，其厚度为大约0.02微米到大约0.05微米。电介质层61包括，比如淀积氧化物，其厚度为大约0.4微米到大约1.0微米。
在层间电介质区48内形成开口，以为源接触层63提供对器件10的接触。如所示的，主表面18的一部分被刻蚀以使源接触层63即与源区33又与体区36接触。在一个实施例中，源接触区63包括钛/氮化钛阻挡层和覆在阻挡层上形成的硅铝合金或之类的。漏接触层13在半导体材料区11的相对面上形成，且包括，比如，可焊接金属结构，诸如钛-镍-银、铬-镍-金或之类的。
器件10的操作按如下进行。假定源端63在零伏的电势Vs下工作，栅区57接收控制电压VG＝5.0伏，该电压大于器件10的导通阀值，且漏端13在漏电势VD＝5.0伏下工作。VG和Vs的数值引起体区31在栅区57下反型以形成沟道45，沟道45将源区33电连接到沟道连接区32。器件电流ID从漏端13流出，经过n型层26、沟道连接区32、沟道45和源区33流至源端63。因此电流ID通过n型层26垂直流动以产生小的导通电阻。在一个实施例中，ID＝1.0安培。为了把器件10转换为截止状态，将小于器件导通阀值的控制电压VG加到栅区57上。(比如，VG＜5.0伏)。这就使沟道45消失，ID不再流过器件10。在截止状态，n型层26和p型层23当来自主阻挡结的耗尽区扩散时相互补偿，从而提高了BVdss。
现在转到图2至图9，其中描述了依据本发明的器件10的形成过程。图2显示了在制造的早期阶段，器件10的放大的部分截面图。结合以上图1提供了半导体材料体11的材料特性的实施例。在一个早期步骤，在主表面18上方形成第一电介质层40，该电介质层40包括，比如，厚度为大约0.05微米至大约0.1微米的氧化硅。然后利用标准光刻法步骤为P型体区31和边缘终端结构(末显示)形成开口。P型体区31通过电介质层40选择性地在半导体14内形成。在一适用于600伏器件的实施例中，硼被掺杂，其剂量为大约1.0×1013原子/厘米2，掺杂能量为大约160KeV，以形成区31。接着，第二电介质层44形成且覆在第一电介质层40上面，第二电介质层44包括，比如，与第一电介质层40不同的材料。作为举例，当第一电介质层40包括氧化硅时，第二电介质层44包括氮化硅。在一个实施例中，第二电介质层44包括大约0.2微米的氮化硅，且是用常规淀积技术形成的。接着，被掺杂的p型掺杂物经过热处理以将该掺杂物扩散至预期深度以形成区31。作为举例，体区31的深度为大约3.0微米到大约5.0微米。
图3显示了器件10在制造的下一阶段的放大的部分截面图。硬掩膜层71形成且覆在主表面18上面并形成图案以通过硬掩模层71、第二电介质层44和第一电介质层40形成开口72，以暴露主表面18的一部分。作为举例，硬掩膜层71包括大约1.0微米的淀积氧化物。作为举例，开口72的宽度74为大约3.0微米到大约5.0微米。接着，通过半导体层14形成槽122。在一个实施例中，槽122延伸进基片12的至少一部分。槽122的深度由半导体层14的厚度决定，这厚度是BVdss的一个函数。在一个实施例中，用一种基于氟或氯化学试剂的深反应离子刻蚀(DRIE)来形成槽122。对DIRE刻蚀可以用几种工艺，包括低温、高密度等离子体或Bosch DRIE工艺。在一个实施例中，槽122具有基本垂直的侧壁。在另一个实施例中，槽122具有渐缩的轮廓，其中在槽的底部表面槽的宽度小于宽度74。尽管槽122被示为多个，应该理解，槽122可以是单个的连续的槽或者是相互连接的槽的阵列。或者槽122也可以是多个具有闭合端部的独立的槽，且被半导体材料体11的部分分开。
图4显示了器件10在下一个制造阶段的放大的部分截面图。在这一阶段上，作为形成填充槽22的第一阶段，半导体材料层在槽122内形成、生长或淀积。在一个实施例中，使用单晶体半导体外延生长工艺填充槽122。也就是说，单晶体半导体层在槽122内生长。
在第一步中，在槽122的侧壁上形成薄的热氧化物(未显示)，以去除由DRIE步骤引起的任何表面损伤。接着，用常规各向同性刻蚀工艺(比如，10：1湿氧化物剥除)去除薄的热氧化物。之后，作为外延生长工艺的第一步，把半导体材料体11放入外延生长反应器并预清洗。当选择硅作为填充层(比如，层23、24、26和27)的半导体材料时，诸如SiHCl3、SiH2Cl2、SiH4或Si2H6的硅气体源是适合于形成这些填充层的。在所示的实施例中，生长的是覆盖层(即，除了生长在槽122上，该层还生长在主表面18上)。在另一实施例中，使用选择性外延生产工艺形成层23、24、26和27以使这些层不是覆在主表面18上形成，而是仅在槽122内形成。
P型层23首先以硼作为合适的掺杂源沿着槽122的表面生长。作为举例，p型层23的掺杂浓度为大约3.0×1016原子/厘米3至大约9.0×1016原子/厘米3，厚度为大约0.1微米至大约0.3微米。在一可选实施例中及如图4所示，本征层233形成且覆在p型层23上，厚度为大约0.1微米至大约0.2微米。覆盖层234接着形成且覆在层233上，且包括，比如，大约0.05微米的热氧化物和大约0.1微米的氮化物。接着，器件10被热处理以主要将来自层23的p型掺杂物横向扩散进半导体层14从而形成横向扩散p型区231。在热处理步骤中，层234设置为覆盖p型层23以防止掺杂物从层23向外扩散。同样，在热处理步骤中，来自基片12的n型掺杂物扩散进层23的部分1200，使部分1200转变成n型。进一步地，层23中的p型掺杂物扩散进本征层233，使本征层233转变成p型层23，如在图5至图9中显示为连续层23。热处理步骤之后，覆盖层234被去除。
现在转到图5，本征层或缓冲层24覆在p型层23上面生长，该本征层24或者是不掺杂的或者是掺杂浓度小于大约2.0×1014原子/厘米3的轻掺杂p型。层24的厚度为大约0.5微米至大约1.5微米。然后，n型层26覆在层24上面生长，该n型层26适于用磷、砷或锑掺杂物源。在一个实施例中，n型层26的掺杂浓度为大约3.0×1016原子/厘米3至大约9.0×1016原子/厘米3，厚度为大约0.1微米至大约0.3微米。接着，在n型层26上生长本征层或缓冲层27，该层或者是不掺杂的(除了在硅源材料中通常存在的微小杂质和/或在以前的生长步骤之后在反应器室中保留的残余掺杂气体)，或者是掺杂浓度小于大约2.0×1014原子/厘米3的轻掺杂n型。层27的厚度为大约0.1微米至大约0.3微米。接着，在层27上生长薄的湿氧化物，继之以形成电介质层28，该电介质层28包括，比如，厚度适合于填充槽122的淀积氧化物。在一个实施例中，使用多个步骤来形成电介质层28，在淀积步骤之间使用深刻蚀(etch-back)或平面化步骤以保证槽122被填充至预期水平。应当理解，层23、24、26、27和28的厚度依据槽122的宽度调整。
图6显示器件10在层28、27、26、2423经过平面化向下至、回到或接近主平面18以形成填充槽22之后又一制造阶段的放大的部分截面图。作为举例，使用深刻蚀或化学机械平面化工艺来平面化这些层。在一个实施例中，多晶硅层和光阻层形成且覆在电介质层28上面，然后用电介质层44作为停止层来深刻蚀或平面化这些多晶硅层和光阻层。接着，通过常规工艺去除层44和40。
接下来，栅电介质层43形成且覆在主平面18上面。在一个实施例中，栅电介质层43包括氧化硅，且厚度为大约0.05微米至大约0.1微米。导电层，比如掺杂的或末掺杂的多晶硅层，覆在栅电介质层43上面淀积并构成图案以形成栅导电区57。比如，栅导电区57包括大约0.2微米的掺杂或末掺杂的多晶硅。如果栅导电区一开始是末掺杂的，这些层随后在区32和33的形成过程中掺杂。注意在一个实施例中，栅导电区57是间隔分开的(即，不重叠)，依据本发明，距填充槽22的距离58使得可以使用分隔工艺(spacer techniques)来形成区32、33、37和39。
接着一钝化层形成且覆在主表面18上，并构成图案以形成第一电介质层51。作为举例，第一电介质层包括大约0.02至大约0.1微米的氧化物。然后一间隔层形成且覆在主表面18上面，并刻蚀以形成间隔物116。作为举例，间隔物116包括大约0.2微米的多晶硅。应当理解，间隔物116的厚度依据区37和39的预期横向宽度来调整。然后沟道连接区32和源区33形成且自对准间隔物116。作为举例，对这一掺杂步骤，用了3.0×1015原子/厘米2的磷掺杂剂量和80KeV的掺杂能量。掺杂的掺杂物或者在这一步退火和扩散，或者在以下将要描述的其它掺杂区形成后退火。
图7为依据形成沟道连接区32的可选方法的器件10的放大的部分截面图。这种可选的方法发生在层28、27、26、24和23被深刻蚀或平面化至接近主表面18后，同时留下第二电介质层44至少部分地覆在部分主表面18上面。接着用第二电介质层44作为掩膜，通过开口72将n型掺杂剂引入。作为举例，在这一掺杂过程中，用了大约1.0×1015原子/厘米2至大约3.0×1015原子/厘米2的磷掺杂剂量和80KeV的掺杂能量。接着，层44和40被去除，并且栅电介质层43形成且覆在主表面18上面。
图8为器件10在另一制造阶段的放大的部分截面图。间隔物116被去除，接着，在源区33和沟道连接区32的邻近分别形成轻掺杂源区37和轻掺杂漏区39。作为举例，在这一掺杂过程中，用了大约1.0×1014原子/厘米2至大约3.0×1014原子/厘米2的磷掺杂剂量和60KeV的掺杂能量。
图9显示器件10在又一个处理过程后的放大的部分截面图。钝化层或电介质层61形成且覆在主表面18上面。作为举例，层61包括淀积氧化物，且厚度为大约0.5微米至大约1.0微米。使用接触光刻蚀步骤形成开口91以暴露源区33之上的主表面18的部分。接下来，一可选的共形间隔层形成且覆在主表面18上面，在开口91内，该共形间隔器被刻蚀以在层61的侧壁上形成间隔物(末显示)。如图9所示的，使用一可选的各向同性刻蚀来加宽层61外表面附近的开口91。接着，主表面18暴露于刻蚀剂，该刻蚀剂用来从半导体层14去除材料以形成凹形区99。在一个实施例中，使用了一系列或一连串掺杂以使体接触区36包括多个如图9所示的区。在一个实施例中，以增加的掺杂能量使用三次硼掺杂来形成如图9所示的渐缩形状。也就是说，较高的离子掺杂能量形成较深且较宽的区域，而较低的离子掺杂能量形成较浅且较窄的区域。作为举例，在形成区36时，第一次硼掺杂的剂量为从大约1.0×1014原子/厘米2至大约1.0×1015原子/厘米2，掺杂能量大约为200KeV，接着第二次硼掺杂的剂量为从大约1.0×1014原子/厘米2至大约1.0×1015原子/厘米2，掺杂能量为大约100KeV，接着第三次硼掺杂的剂量为从大约1.0×1014原子/厘米2至大约1.0×1015原子/厘米2，掺杂能量为25-30KeV。在一可选方法中，体接触区36在形成电介质层61之前用常规掩膜工艺形成。然后形成电介质层61且接着构成图案。
在体接触区36形成后，间隔物从开口91移除，源接触或导电层63形成且覆在主表面18上面。作为举例，形成诸如钛/氮化钛的阻挡结构，继而形成包括铝或铝合金的层。然后，用常规光刻蚀工艺构成导电层的图案以形成如图1所示的源接触层63。在一个实施例中，使用覆在源接触层63上面的最终钝化层，该钝化层包括淀积氧化物、淀积氮化物或它们的组合。接着，如图1所示和结合如图1的进一步描述所述，器件10被减薄，并且形成漏接触层13以接触基片12。
图10为依据本发明另一实施例的具有填充补偿槽区的半导体器件100的一部分的高倍放大的局部截面图。在器件100中，半导体材料体11包括n型基片12、n型阻挡层114，其掺杂浓度比基片12掺杂浓度(比如，大约20-35欧姆-厘米)低，且厚度为大约10微米至大约20微米，除此之外，器件100与器件10类似。另外，在器件100中，填充槽222不是一直延伸穿过阻挡层114。在该实施例中，在槽122刻蚀后，n型掺杂物通过槽122的下表面被引入以在槽122的下表面邻近形成n+区域223，该n+区域起反掺杂p型层的作用从而将填充槽222电连接到缓冲外延层114。该实施例适合于用相同的填充槽工艺制造不同击穿电压的器件。随后用不同缓冲层114的掺杂浓度和厚度可以得到各种击穿电压。
图11显示依据本发明又一实施例的具有填充补偿槽区的半导体器件110的一部分的高倍放大的局部截面图。在器件110中，在p型层23淀积后，p型层23的沿着槽122的底部部分146的那一部分被去除，以在基片12和n型层26之间提供增强的导电通道，除此之外，器件110和器件10类似。
总之，已经描述了一种具有深槽电荷补偿区的新的开关器件结构，包括一种制造方法。深槽电荷补偿区与器件的源区分隔开，并且当器件工作的时候，用沟道连接区将源区电连接到深槽电荷补偿区。器件进一步包括用槽结构形成的横向掺杂区从而形成器件的主阻挡结。
虽然已参照本发明的具体实施例对发明进行了描述和说明，但本发明并不限于这些说明性的实施例。本领域的技术人员可以认识到，在不偏离本发明的精神下，可以作修改和变动。因此，本发明旨在把所有这种变动和修改都包括进所附权利要求的范围。

Claims (10)

1.一种半导体器件，其包括：
半导体材料区，其具有第一主表面；
槽补偿区，其在所述半导体材料区内形成并从所述第一主表面延伸，其中所述槽补偿区包括多个相反导电类型的半导体层；
体区，其在所述半导体材料区内形成；
源区，其在所述体区内形成且与所述槽补偿区横向分隔开；
栅结构，其在所述源区和所述槽补偿区之间形成，其中所述栅结构包括导电栅区，所述导电栅区设置为使得当所述器件在工作的时候在所述体区内建立沟道区；以及
沟道连接区，其在所述槽补偿区的上部部分形成，所述沟道连接区设置为使得当所述器件在工作的时候将所述沟道区电连接到所述槽补偿区。
2.如权利要求1所述的器件，其中所述槽填充有多个单晶体外延层，包括：
具有第一导电类型的第一层，其覆在所述槽的侧壁和下部表面上面形成；以及
具有第二且相反导电类型的第二层，其覆在所述第一层上面形成。
3.如权利要求1所述的器件，其进一步包括掺杂区，所述掺杂区从所述槽补偿区横向延伸进所述半导体材料区中且在所述体区之下，其中所述掺杂区和所述体区包括第一导电类型，且其中所述沟道连接区包括第二且相反导电类型。
4.如权利要求1所述的器件，其进一步包括在所述源区和所述导电栅区之间形成的轻掺杂源区。
5.如权利要求1所述的器件，其中所述半导体材料区包括半导体基片和覆在所述半导体基片上面形成的半导体层，所述半导体层具有比所述半导体基片低的掺杂浓度。
6.如权利要求5所述的器件，其中覆在所述半导体基片上面的半导体层具有渐次变化的掺杂分布。
7.如权利要求5所述的器件，其中所述槽补偿区在所述半导体基片上面的半导体层内终止，且其中所述器件进一步包括与所述槽补偿区的下部表面相邻形成的掺杂区，所述掺杂区设置为使得当所述器件在工作的时候将所述槽补偿区电连接到所述半导体基片。
8.一种形成半导体器件的方法，其包括步骤：
设置具有第一主表面的半导体材料区；
在所述半导体材料区内形成从所述第一主表面延伸的槽；
在所述槽内形成多个半导体层，其包括至少两个相反导电类型的半导体层以及至少一个缓冲层，所述缓冲层分隔所述至少两个相反导电类型的半导体层以形成填充槽补偿区，其中在形成的时候，所述缓冲层的掺杂浓度比所述至少两个相反导电类型的半导体层的掺杂浓度低；
形成控制电极，其覆在所述第一主表面上面，且其与所述填充槽补偿区横向分隔开，所述控制电极设置为使得在工作期间在所述半导体材料区中形成沟道；以及
至少部分地在所述填充槽补偿区内形成第一掺杂区，所述第一掺杂区设置为使得在工作期间将所述沟道区电连接到所述填充槽补偿区。
9.如权利要求8所述的方法，其中所述设置半导体材料区的步骤包括设置具有第一导电类型的半导体基片和形成半导体层，所述半导体层覆在所述半导体基片上面形成，且其中所述方法进一步包括步骤：
在覆在所述半导体基片上面的半导体层内形成具有第二导电类型的体区；以及
在所述体区内形成具有所述第一导电类型的源区，且其与所述填充槽补偿区横向分隔开，且其中所述源区和第一区自对准于所述控制电极。
10.一种半导体超结器件，其包括：
具有第一主表面的半导体材料区；
槽补偿区，其包括具有第一导电类型的第一层和具有第二导电类型的第二层，所述第一层覆在所述槽补偿区的侧壁和下部表面上面，所述第二层覆在所述第一层上面；
具有所述第一导电类型的体区，其与所述槽补偿区相邻在所述半导体材料区内形成；
具有所述第二导电类型的源区，其在所述体区内形成且其与所述槽补偿区分隔开；
栅层，其覆在所述第一主表面上面形成，且其介于所述源区和所述槽补偿区之间，所述栅层设置为使得当所述器件在工作的时候在所述体区形成沟道；以及
具有所述第二导电类型的第一掺杂区，其至少部分地在所述槽补偿区内形成且其设置为使得当器件在工作的时候将所述沟道电连接到所述第二层。
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