CN101095211B - 用于互补金属氧化物半导体的受力无位错沟道及制造方法 - Google Patents

用于互补金属氧化物半导体的受力无位错沟道及制造方法 Download PDF

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CN101095211B
CN101095211B CN2004800299944A CN200480029994A CN101095211B CN 101095211 B CN101095211 B CN 101095211B CN 2004800299944 A CN2004800299944 A CN 2004800299944A CN 200480029994 A CN200480029994 A CN 200480029994A CN 101095211 B CN101095211 B CN 101095211B
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杜里塞蒂·奇达姆贝拉奥
奥默·多库梅西
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Abstract

本发明涉及半导体器件及制造半导体器件的方法。该半导体器件包括用于pFET和nFET的沟道。SiGe层生长在nFET沟道的沟道中，Si:C层生长在pFET沟道中。SiGe和Si:C层匹配下面的Si层的晶格网络，从而在上面生长的外延层中产生应力分量。在一实施方式中，这产生pFET沟道中的压缩分量和nFET沟道中的拉伸分量。在另一实施方式中，SiGe层生长在nFET和pFET沟道两者中。在此实施方式中，pFET沟道中的应力水平应当大于约3GPa。

Description

用于互补金属氧化物半导体的受力无位错沟道及制造方法
技术领域
本发明总地涉及半导体器件及制造方法，更特别地，涉及一种半导体器件及在器件制造期间在该器件中施加拉伸应力和压缩应力的制造方法。
背景技术
半导体器件衬底内的机械应力能调整器件性能。即，已经知道半导体器件内的应力提高半导体器件特性。因此，为了改善半导体器件的特性，在n型器件(例如NFET)和/或p型器件(例如PFET)的沟道内产生拉伸和/或压缩应力。然而，相同的应力分量，拉伸应力或压缩应力，不同地影响n型器件和p型器件的特性。
为了最大化集成电路(IC)芯片内的nFET和pFET两者的性能，对于nFET和pFET应当不同地设计和施加应力分量。这是因为对nFET的性能有利的应力类型通常对pFET的性能不利。更具体地，当器件受拉(例如在平面器件中的电流方向上)时，nFET的性能特性提高，而pFET的性能特性下降。为了选择性地形成nFET中的拉伸应力和pFET中的压缩应力，使用不同工艺和不同的材料组合。
例如，已经提出了槽隔离结构，以分别在nFET和pFET中形成适当的应力。当使用此方法时，用于nFET器件的隔离区包含第一隔离材料，该第一隔离材料在纵向(例如平行于电流方向)和在横向(例如垂直于电流方向)上对nFET器件施加第一类型的机械应力。另外，为pFET提供第一隔离区和第二隔离区，且pFET器件的每个隔离区在横向和纵向上对pFET器件施加唯一的机械应力。
作为选择地，已经提出栅极侧壁上的衬垫(liner)来选择性地在FET器件的沟道中引入合适的应力(例如见Ootsuka等人，IEDM 2000，p.575)。通过提供衬垫，与作为槽隔离填充技术的结果所施加的应力相比，该合适的应力被更近地施加在器件上。
尽管这些方法确实提供了使拉伸应力施加到nFET器件以及使压缩应力沿pFET器件的纵向被施加的结构，但它们会需要额外的材料和/或更复杂的处理，因此导致高成本。另外，这些情况中可施加的应力水平通常是中等的(即大约几百MPa)。因此，期望提供更节省成本和简化的方法以用于分别在nFET和pFET沟道中形成大的拉伸和压缩应力。
发明内容
在本发明的第一方面，提供一种用于制造半导体结构的方法。该方法包括在衬底中形成p型场效应晶体管(pFET)沟道和n型场效应晶体管(nFET)沟道。第一层材料设置在该pFET沟道内，具有与该衬底的晶格常数不同的晶格常数；且第二层材料设置在该nFET沟道内，具有与该衬底的晶格常数不同的晶格常数。外延半导体层形成在该pFET沟道内该第一层材料及该nFET沟道内该第二层材料之上。该外延半导体层基本上具有与该衬底相同的晶格常数，使得应力分量产生在该pFET沟道和该nFET沟道内。
在本发明的另一方面，提供一种制造半导体结构的方法。该方法包括在衬底层例如Si或绝缘体上硅中形成pFET和nFET沟道。第一层材料设置在该pFET沟道内，具有与该衬底层的晶格常数不同的晶格常数；第二层材料设置在该nFET沟道内，具有与该衬底层的晶格常数不同的晶格常数。外延半导体层形成在该pFET沟道内该第一层材料及该nFET沟道内该第二层材料之上。该外延半导体层基本上具有与该衬底层相同的晶格常数，从而引起与该pFET沟道内的该第一层材料及该nFET沟道内的第二层材料的应力分量相反的应力分量。
在本发明的再一方面，一种半导体结构包括形成在衬底例如Si层中的pFET和nFET沟道。浅槽隔离结构形成在该Si层中，且该pFET沟道内的第一层材料具有与该Si层的晶格常数不同的晶格常数。该nFET沟道内的第二层材料具有与该Si层的晶格常数不同的晶格常数。形成在该pFET沟道内该第一层材料及该nFET沟道内该第二层材料之上的外延半导体层基本上具有与该Si层相同的晶格常数，从而在该pFET沟道和该nFET沟道内产生所需要的应力分量。
附图说明
图1a至1f示出形成根据本发明的器件的制造工艺；
图2a至2d示出形成根据本发明的器件的制造工艺；
图3示出根据本发明的nFET器件中应力的位置；及
图4示出根据本发明的pFET器件中应力的位置
具体实施方式
本发明针对半导体器件及制造方法，其提供了CMOS器件的nFET沟道中的拉伸应力和pFET沟道中的压缩应力。在一实施例中，高的拉伸应力也可提供在pFET沟道中从而提高器件性能。在本发明一实施例中，沟道在nFET和pFET的形成区域中在硅层中形成。然后沟道填充以硅基材料，其具有与下面的硅层的晶格常数不相配的天然存在的晶格常数。通过应用这些材料，拉伸和/或压缩力分别产生在nFET和pFET的沟道中的上面的外延层中。在一实施例中，nFET和pFET沟道可同时形成。通过使用本发明的制造工艺，可以实现改进的器件特性以及更高的产率和更低的器件缺陷。另外，利用本发明的制造工艺可以实现更低的生产成本。
图1a至1f示出了形成根据本发明的器件的制造工艺。图1a中，提供衬底10，诸如例如绝缘体上硅(SOI)等。其包括掩埋氧化物层(buried oxidelayer)15和绝缘体上硅层20(例如Si层)。该SOI晶片可以通过本领域公知的SIMOX或粘合技术形成。在一实施例中，Si层20为大约
Figure G04829994420060427D000031
至
Figure G04829994420060427D000032
然而，应当充分理解，根据具体应用本发明考虑Si层20的高度的变动。
仍参照图1a，然后利用垫(pad)氧化、垫氮化物沉积、基于光刻的构图、对包括氮化物、氧化物和硅的堆叠的下至掩埋氧化物的反应离子蚀刻(RIE)、边缘氧化(edge oxidation)、衬垫沉积、填充沉积、以及化学机械抛光的标准技术，Si层20被构图从而形成浅槽隔离部件(STI)25。该STI形成工艺在本领域是公知的。然后剥离垫氮化物。
现在参照图1b，氧化物层32沉积在STI区25和Si层20的抛光表面上。此氧化物层32的高度可以改变，且在一实施例中为大约
Figure G04829994420060427D000033
可以是任何已知光致抗蚀剂材料的光致抗蚀剂层35沉积在氧化物层32上。在使用公知的掩模和光刻构图技术之后，然后在光致抗蚀剂层35和氧化物层32上进行例如反应离子蚀刻。在此步骤中，反应离子蚀刻对氧化物层可以是选择性的。这开始了同时形成pFET沟道40和nFET沟道45的工艺。在氧化物蚀刻后，Si层20利用反应离子蚀刻被选择性地蚀刻，如图1c所示。
在供选步骤中，根据所需的蚀刻深度，利用2e14#/cm2至1e15#/cm2典型剂量、10keV至100keV范围内的能量的Ge注入，Si首先被非晶化。此可选的非晶化步骤可用来改善蚀刻质量。在任一制造中，沟道40和45分别形成在对应pFET和nFET的位置的Si层20中。在一实施例中，沟道40和45在Si层20中被蚀刻至约
Figure G04829994420060427D000041
至
Figure G04829994420060427D000042
的深度。然而，根据使用本发明的具体应用，此深度可改变。
图1d是根据本发明的进一步制造工序的图示。在这些制造工序中，光致抗蚀剂材料35利用任何公知工艺去除。硬掩模50利用任何公知光刻工艺构图在pFET沟道40内。在一实施例中，硬掩模是氮化物材料且构图在氧化物层32之上，接近pFET沟道40。SiGe层45a外延生长在nFET沟道45内至约
Figure G04829994420060427D000043
到
Figure G04829994420060427D000044
的厚度，尽管本发明也可考虑其它厚度。
孤立时，SiGe通常具有比Si层20大的晶格常数。即，SiGe材料的晶格常数与Si层20的晶格常数不相配。然而，在本发明的结构中，由于SiGe层45a在nFET沟道45内的生长，SiGe层45a的晶格结构将倾向于匹配下面的Si层20的晶格结构。
由于SiGe 45a(通常较大)与Si层20的晶格匹配，这导致SiGe层45a和周围区域受压。然而，SiGe层的周围区域将试图获得平衡状态，因此导致形成在SiGe层45a上的外延Si层(如图1f所示)的拉伸应力。在一实施例中，SiGe层45a的Ge含量与Si含量的比例可为5％至50％。
在图1e中，硬掩模50通过任何公知工艺去除。硬掩模55利用任何公知光刻工艺构图在nFET沟道45内。硬掩模55也构图在氧化物层32之上，接近nFET沟道45且在这样生长的SiGe层45a之上。再次，在一实施例中，硬掩模55是氮化物材料。然后，Si:C层40a外延生长在pFET的沟道40中至约
Figure G04829994420060427D000045
到的厚度，尽管本发明也考虑其它厚度。本领域普通技术人员应当理解，图1e的工艺步骤同样可以在图1d所示的工艺步骤之前进行。
孤立时，Si:C通常具有比Si层20小的晶格常数。即，Si:C材料的晶格常数与Si层20的晶格常数不相配。然而，在本发明的结构中，由于Si:C层40a在pFET沟道40内的生长，Si:C层40a的晶格结构将倾向于匹配下面的Si层20的晶格结构。
由于Si:C 40a(通常较小)与Si层20的晶格匹配，这导致Si:C层40a和周围区域处于拉伸应力之下。类似于SiGe层发生的情况，Si:C层40a的周围区域将试图获得平衡状态，因此导致形成在Si:C层40a上的外延Si层的压缩应力。在一实施例中，C含量与Si含量的比例可为0％至4％。
图1f示出了中间结构。为获得此结构，硬掩模55以与参照图1e所描述的方式类似的方式被去除。Si外延层60分别选择性地生长在pFET和nFET的沟道中的Si:C和SiGe层之上。在一实施例中，如上所述，Si外延层60与SiGe 45a或Si:C 40a周围结构及Si绝缘层20平衡，导致nFET沟道45中的拉伸应力及pFET沟道40中的压缩应力。应当理解，通过调整SiGe层中Ge含量的浓度，可以调整nFET沟道45中的拉伸应力。类似地，通过调整Si:C层中C的浓度，于是可以调整pFET沟道40中的压缩应力。这归因于这些材料的晶格常数。
仍然参照图1f，然后牺牲氧化物层65生长在选择性生长的外延Si层60之上。然后利用常规基于光致抗蚀剂的光刻技术遮蔽pFET，从而可以进行nFET沟道注入。在剥离相关抗蚀剂(图1f中未示出)之后，接着nFET被遮蔽(再次使用常规基于光致抗蚀剂的光刻技术)且进行pFET沟道注入，然后是另一光致抗蚀剂剥离。然后，牺牲氧化物层65被剥离，且栅极氧化层70被生长，如图1f所示。然后，栅极多晶硅70形成在pFET和nFET区中。进行本领域普通技术人员公知的栅极多晶硅沉积和化学机械抛光，从而制造图1f所示的结构。
在剥离镶嵌(damascene)氧化物层32之后，常规CMOS加工可继续该工艺。例如，在利用任何公知工艺剥离氧化物层32之后，可进行常规间隔物(spacer)和离子注入工艺，从而形成pFET和nFET的延伸部(extension)及源极和漏极区域。
图2a至2d示出了形成根据本发明的器件的另一制造工艺。图2a中，衬底和STI以与用于图1a的方式相同的方式形成。图2a中，提供衬底10，诸如例如绝缘体上硅(SOI)等。其包括掩埋氧化物层15和绝缘体上硅层20。该SOI晶片可以通过本领域公知的SIMOX或粘合技术形成。在一实施例中，Si层20为大约
Figure G04829994420060427D000051
至
Figure G04829994420060427D000052
然而，应当理解，本发明根据具体应用考虑Si层20的高度的变化。
仍参照图2a，然后利用垫氧化、垫氮化物沉积、基于光刻的构图、包括氮化物、氧化物和硅的堆叠的下至掩埋氧化物的反应离子蚀刻(RIE)、边缘氧化(edge oxidation)、衬沉积、填充沉积和化学机械抛光的常规技术，Si层20被构图，从而形成浅槽隔离部件(STI)25。该STI形成工艺是本领域公知的。然后剥离垫氮化物。
现在参照图2b，氧化物层32沉积在STI区25和Si层20的抛光表面上。此氧化物层32的高度可以改变，且在一实施例中为大约
Figure G04829994420060427D000061
可以是任何公知光致抗蚀剂材料的光致抗蚀剂层35沉积在氧化物层32上。在使用公知的掩模和光刻构图技术之后，然后在光致抗蚀剂层35和氧化物层32上进行例如反应离子蚀刻。在此步骤中，反应离子蚀刻对氧化物层可以是选择性的。这开始了形成nFET沟道45的工艺。在氧化物蚀刻之后，Si层20利用反应离子蚀刻被选择性地蚀刻。可进行可选的非晶Si蚀刻以改善蚀刻质量。在一实施方式中，沟道45在Si绝缘层20中被蚀刻至约至
Figure G04829994420060427D000063
的深度。然而，此深度可根据使用本发明的具体应用而改变。
在供选步骤中，根据所需的蚀刻深度，利用2e14#/cm2至1e15#/cm2的典型剂量、10keV至100keV范围内的能量的Ge注入，Si首先被非晶化。此可选的非晶化步骤可用来改善蚀刻质量。在任一制造中，沟道40和45分别在对应pFET和nFET的位置的Si层20中形成。在一实施方式中，沟道40和45在Si层20中被蚀刻至约
Figure G04829994420060427D000064
至
Figure G04829994420060427D000065
的深度。然而，此深度可根据使用本发明的具体应用而变化。
图2c是根据本发明的进一步制造工序的图示。在这些制造工序中，SiGe层45a生长在nFET的沟道45中至约
Figure G04829994420060427D000066
到
Figure G04829994420060427D000067
的高度，尽管本发明也考虑其它高度。在一实施例中，SiGe的Ge含量与Si含量的比例可为0％至50％，优选约15％。然后，外延Si层60选择性生长在nFET沟道45中的SiGe层45a之上。然后，牺牲栅极氧化物层生长在选择性生长的Si层60之上。然后利用任何公知的制造工艺提供nFET掩模和阱注入。栅极氧化物65a然后形成在nFET区中。然后沉积栅极多晶硅70a，接着是本领域技术人员公知的化学机械抛光，从而制造图2c所示的结构。
然后，此相同工艺可用于形成器件的pFET，其可同等地由图2b和2c表示。取代SiGe，pFET结构结合Si:C。最后的产品示于图2d，其示出了结合选择的Si:C栅极氧化物65b和栅极多晶硅70b的pFET。氧化物32被剥离且可利用常规CMOS加工来继续该工艺。这些包括延伸部(extension)、源极和漏极区、硅化物形成、氮化物蚀刻停止层、接触工艺、互连等。
在本发明另一实施例中，如果由SiGe材料可以在沟道中实现大于约3GPa的应力水平，则SiGe材料可用于pFET沟道和nFET沟道两者中。此方法利于大的Ge含量，因为其要求非松弛系统(unrelaxed system)。因此，针对pFET可以使用所述的SiGe沉积步骤。然而，应当认识到，由于诸如高应力和位错问题的竞争性需求，工艺(Ge％)窗口会较小。由于与嵌入的材料相比沟道应力水平相对减小，所以在实施例中，嵌入的材料应当具有比约25％至30％更大的Ge百分比，以将此结构用于pFET。在此方法中，没有独立的pFET和nFET控制。
图3示出了根据本发明的nFET器件中的应力位置。如图3所示，拉伸应力出现在具有受压非松弛SiGe区域的nFET的沟道中。更具体地，在本发明的结构中，SiGe层45a的晶格结构匹配下面的Si绝缘层20的晶格结构。这导致SiGe层45a和周围区域处于压缩应力下。周围区域将试图获得平衡状态，从而导致形成在SiGe层45a上的外延Si层60的拉伸应力。
图4示出了根据本发明的pFET器件中的应力位置。如图4所示，压缩应力出现在具有受拉非松弛Si:C区域的pFET的沟道中。更具体地，在本发明的结构中，Si:C层40a的晶格结构将匹配下面的Si绝缘层20的晶格结构。这导致Si:C层40a和周围区域处于拉伸应力下。如SiGe层发生的情况那样，Si:C层40a的周围区域将获得平衡状态。然而，这导致形成在Si:C层40a上的外延Si层60的压缩应力。
在一实施方式中，图1f的nFET的Si外延层60中的纵向应力分量(从源极到漏极的电流的方向上的应力)的优选范围为大于100MPa的拉伸值，而在pFET Si沟道中大于100MPa的压缩值是优选的。
因此，在本发明的结构中，现在拉伸应力形成在nFET的沟道中且压缩应力形成在pFET中。在一实施方式中，高拉伸应力也可以形成在pFET中。通过允许这样的应力，可以实现高器件性能。另外，利用本发明的工艺，可以减小制造成本，得到高产率。
尽管已经根据实施例描述了本发明，但是本领域技术人员将理解，在所附权利要求的精神和范围内，本发明可以以改进型式实施。例如，本发明可以容易地应用于块衬底(bulk substrate)。

Claims (26)

1.一种制造半导体结构的方法，包括步骤：
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道，所述p型场效应晶体管沟道和n型场效应晶体管沟道由通过从所述衬底的上表面去除材料来在所述衬底中形成的沟槽形成；
在该p型场效应晶体管沟道内设置具有与该衬底的晶格常数不同的晶格常数的第一层材料；
在该n型场效应晶体管沟道内设置具有与该衬底的晶格常数不同的晶格常数的第二层材料；
在该p型场效应晶体管沟道内该第一层材料及该n型场效应晶体管沟道内该第二层材料之上形成外延半导体层，该外延半导体层基本上具有与该衬底相同的晶格常数，使得应力分量产生在该p型场效应晶体管沟道和该n型场效应晶体管沟道内。
2.如权利要求1所述的方法，其中该p型场效应晶体管沟道和该n型场效应晶体管沟道同时形成。
3.如权利要求1所述的方法，其中该p型场效应晶体管沟道和该n型场效应晶体管沟道分别形成。
4.如权利要求1所述的方法，其中该第一层材料为SiGe，按与Si的比例具有大于25％的Ge含量。
5.如权利要求4所述的方法，其中该第一层材料产生大于3GPa的该外延半导体层内的拉伸应力。
6.如权利要求1所述的方法，其中该第二层材料为SiGe。
7.如权利要求6所述的方法，其中该第二层材料在该n型场效应晶体管沟道内该外延半导体层中产生拉伸应力。
8.如权利要求1所述的方法，其中该第一层材料为Si:C。
9.如权利要求1所述的方法，还包括步骤：
在该外延半导体层之上形成栅极氧化物结构；以及
在该栅极氧化物结构的侧部该衬底中形成延伸部及漏极区和源极区。
10.如权利要求1所述的方法，其中该衬底为硅层或包括绝缘体上硅层的绝缘体上硅，该n型场效应晶体管和该p型场效应晶体管沟道的形成包括蚀刻该硅层至
Figure F200480029994401C00021
到
Figure F200480029994401C00022
的深度。
11.如权利要求1所述的方法，其中：
该第一层材料通过在该n型场效应晶体管沟道之上设置硬掩模且在该p型场效应晶体管沟道内生长该第一层材料而形成；以及
该第二层材料通过在该p型场效应晶体管沟道之上设置硬掩模且在该n型场效应晶体管沟道内生长该第二层材料而形成。
12.如权利要求1所述的方法，还包括在该衬底内形成浅槽结构。
13.如权利要求1所述的方法，其中该第一层材料和该第二层材料生长至
Figure F200480029994401C00023
到
Figure F200480029994401C00024
的高度。
14.如权利要求1所述的方法，其中该衬底层是绝缘体上硅。
15.如权利要求1所述的方法，其中该第一层材料和该第二层材料都是SiGe材料，其具有比25％至30％更大的Ge百分比从而应用于p型场效应晶体管。
16.一种制造半导体结构的方法，包括步骤：
在衬底中形成p型场效应晶体管沟道和n型场效应晶体管沟道，所述p型场效应晶体管沟道和n型场效应晶体管沟道由通过从所述衬底的上表面去除材料来在所述衬底中形成的沟槽形成；
在该p型场效应晶体管沟道内设置具有与该衬底的晶格常数不同的晶格常数的第一层材料；
在该n型场效应晶体管沟道内设置具有与该衬底的晶格常数不同的晶格常数的第二层材料；
在该p型场效应晶体管沟道内该第一层材料及该n型场效应晶体管沟道内该第二层材料之上形成外延半导体层，该外延半导体层基本上具有与该衬底相同的晶格常数，从而产生与该p型场效应晶体管沟道内的该第一层材料及该n型场效应晶体管沟道内的该第二层材料的应力分量相反的应力分量。
17.如权利要求16所述的方法，其中该p型场效应晶体管沟道和该n型场效应晶体管沟道同时形成。
18.如权利要求16所述的方法，其中该p型场效应晶体管沟道和该n型场效应晶体管沟道分别形成。
19.如权利要求16所述的方法，其中该第一层材料是Si:C，且该第二层材料是SiGe。
20.如权利要求19所述的方法，其中：
该第一层材料在该p型场效应晶体管沟道内该外延半导体层中产生压缩应力；且
该第二层材料在该n型场效应晶体管沟道内该外延半导体层中产生拉伸应力。
21.如权利要求16所述的方法，还包括步骤：
在该外延半导体层之上形成栅极氧化物结构；以及
在该栅极氧化物结构的侧部该Si层中形成延伸部及漏极区和源极区。
22.如权利要求16所述的方法，其中：
该第一层材料通过在该n型场效应晶体管沟道之上设置硬掩模且在该p型场效应晶体管沟道内生长该第一层材料而形成；以及
该第二层材料通过在该p型场效应晶体管沟道之上设置硬掩模且在该n型场效应晶体管沟道内生长该第二层材料而形成。
23.一种半导体结构，包括：
p型场效应晶体管沟道，其形成在衬底中，所述p型场效应晶体管沟道由通过从所述衬底的上表面去除材料来在所述衬底中形成的沟槽形成；
n型场效应晶体管沟道，其形成在该衬底中，所述n型场效应晶体管沟道由通过从所述衬底的上表面去除材料来在所述衬底中形成的沟槽形成；
浅槽隔离结构，其形成在该衬底中；
第一层材料，其在该p型场效应晶体管沟道内，具有与该衬底的晶格常数不同的晶格常数；
第二层材料，其在该n型场效应晶体管沟道内，具有与该衬底的晶格常数不同的晶格常数；
外延半导体层，其形成在该p型场效应晶体管沟道内该第一层材料及该n型场效应晶体管沟道内该第二层材料之上，该外延半导体层基本上具有与该衬底相同的晶格常数，从而在该p型场效应晶体管沟道和该n型场效应晶体管沟道内产生所需的应力分量。
24.如权利要求23所述的结构，其中该第一层材料为Si:C，且该第二层材料为SiGe。
25.如权利要求23所述的结构，其中该第一层材料和该第二层材料是SiGe，其在该p型场效应晶体管沟道内产生大于3GPa的应力水平。
26.如权利要求23所述的结构，其中：
该第一层材料在该p型场效应晶体管沟道内该外延半导体层中产生压缩应力；且
该第二层材料在该n型场效应晶体管沟道内该外延半导体层中产生拉伸应力。
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