CN101095218A - 使用沉陷沟槽具有顶部漏极的半导体功率器件 - Google Patents

使用沉陷沟槽具有顶部漏极的半导体功率器件 Download PDF

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CN101095218A
CN101095218A CNA2005800244081A CN200580024408A CN101095218A CN 101095218 A CN101095218 A CN 101095218A CN A2005800244081 A CNA2005800244081 A CN A2005800244081A CN 200580024408 A CN200580024408 A CN 200580024408A CN 101095218 A CN101095218 A CN 101095218A
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trench
sinker trench
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CN100576466C (zh
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托马斯·E·格雷布斯
加里·M·多尔尼
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Fairchild Semiconductor Corp
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Abstract

一种半导体功率器件，包括：第一导电型基板；第一导电型外延层，该外延层位于基板上方并与基板相接触。第一沟槽延伸到并终止于外延层内。沉陷沟槽从外延层的顶表面延伸穿过外延层并终止于基板内。沉陷沟槽与第一沟槽横向隔开，沉陷沟槽比第一沟槽宽且延伸得更深。沉陷沟槽仅沿沉陷沟槽侧壁以绝缘体作衬里，使得填充沉陷沟槽的导电材料沿沟槽的底部与基板进行电接触，并沿沟槽的顶部与互连层进行电接触。

Description

使用沉陷沟槽具有顶部漏极的半导体功率器件
相关申请交叉参考
本申请要求2004年8月3日提交的美国临时申请No.60/598,678的权益，其内容结合于此以作参考。而且，本申请涉及2004年12月29日提交的题为“功率半导体器件及其制造方法”的申请No.11/026,276，其内容结合于此作为参考。
技术领域
本发明通常涉及半导体功率器件，更具体地说，涉及使用沉陷沟槽(sinker trench)的具有顶部漏极接触的功率器件。
背景技术
与具有横向结构(其所有的相互连接均可在上芯片表面上获得)的集成电路(IC)不同，许多功率半导体器件具有垂直结构，其中，芯片的背面为活动的(active)电连接。例如，在垂直功率MOSFET结构中，源极和栅极连接位于芯片的顶表面处，而漏极连接位于芯片的背面。对于一些应用，希望实现在顶部能够获得漏极连接。为此使用沉陷沟槽结构。
在第一技术中，从芯片的顶部向下延伸至基板(其形成器件的漏极接触区)的扩散沉陷槽用来使得在芯片顶部表面处可获得漏极接触。该项技术的缺点在于在扩散沉陷槽形成期间的横向扩散造成大量硅区域的消耗。
在第二技术中，从芯片的顶部延伸通过芯片背面的金属填充通道用来使该背面与芯片的顶部相连。尽管该项技术不会如扩散沉陷槽技术中那样会造成有源区(active area)的损失，但是该项技术需要形成深沟道，这增加了制造工艺的复杂性。此外，在传导期间，在电流到达漏极接触之前，电流需要沿基板传输很长的距离，从而造成导通电阻Ron很高的器件。
因此，需要一种改进的沟槽结构，以便于使得在顶部处可以获得背面接触。
发明内容
根据本发明的实施例，半导体功率器件包括第一导电型基板和第一导电型外延层，该外延层位于该基板上方并与之相接触。第一沟槽延伸到并终止于外延层内。沉陷沟槽从外延层的顶表面延伸穿过外延层，并终止于基板内。沉陷沟槽与第一沟槽横向隔开，并且比第一沟槽更宽且延伸得更深。沉陷沟槽仅沿沉陷沟槽侧壁以绝缘体作衬里，从而填充沉陷沟槽的导电材料沿沟槽的底部与基板进行电接触，并沿沟槽的顶部与互连层进行电接触。
根据本发明的另一实施例，半导体功率器件如下形成。外延层形成在基板上方，并与之接触。外延层和基板是第一导电型的。限定用于形成第一沟槽的第一开口以及用于形成沉陷沟槽的第二开口，使得第二开口宽于第一开口。进行硅蚀刻，通过第一和第二开口同时蚀刻，以形成第一沟槽和沉陷沟槽，使得第一沟槽终止于外延层内，而沉陷沟槽终止于基板内。以绝缘体作为沉陷沟槽侧壁和底部的衬里。用导电材料填充沉陷沟槽，使得导电材料沿沉陷沟槽的底部与基板进行电接触。在外延层上方形成互连层，使得互连层沿沉陷沟槽的顶表面与导电材料进行电接触。
根据本发明的再一实施例，半导体功率器件包括在基板上方的硅区域中延伸的多组带状沟槽。连贯的沉陷沟槽完全包围多组带状沟槽中的每一组，以便使多组带状沟槽彼此绝缘。连贯的沉陷沟槽从硅区域的顶表面延伸穿过硅区域，并终止于基板内。连贯的沉陷沟槽仅沿沉陷沟槽侧壁以绝缘体作衬里，从而填充连贯的沉陷沟槽的导电材料沿连贯沉陷沟槽的底部与基板进行电接触，并沿连贯沉陷沟槽的顶部与互连层进行电接触。
根据本发明的再一实施例，半导体功率器件包括在基板上方的硅区域中延伸的多组带状栅极沟槽。多个带状沉陷沟槽中的每一个均在多组带状栅极沟槽中的两个相邻组之间延伸。多个带状沉陷沟槽从硅区域的顶表面延伸穿过硅区域，并终止于基板内。多个带状沉陷沟槽仅沿沉陷沟槽侧壁以绝缘体作衬里，从而填充每个沉陷沟槽的导电材料沿沉陷沟槽的底部与基板进行电接触，并沿沉陷沟槽的顶部与互连层进行电接触。
根据本发明的另一实施例，半导体封装器件容纳包括功率器件的芯片。该芯片包括基板上方的硅区域。多个第一沟槽中的每一个在硅区域中延伸。连贯沉陷沟槽沿芯片的周边延伸，以便完全包围多个第一沟槽。连贯沉陷沟槽从芯片的顶表面延伸穿过硅区域，并终止于基板内。连贯沉陷沟槽仅沿沉陷沟槽侧壁以绝缘体作衬里，从而填充连贯沉陷沟槽的导电材料沿连贯沉陷沟槽的底部与基板进行电接触，并沿连贯沉陷沟槽的顶部与互连层进行电接触。设置在栅格阵列中的多个互连球包括电连接至连贯沉陷沟槽中导电材料的多个互连球的外部组。
附图说明
图1示出了根据本发明实施例的示例性垂直功率器件的简化横截面视图；
图2-图4示出了根据本发明示例性实施例的具有一个或多个沉陷沟槽的垂直功率器件的各种俯视布局图；以及
图5是示出了根据本发明示例性实施例的球栅阵列封装件中的互连球相对于沉陷沟槽的位置的俯视图，其中沉陷沟槽沿位于球栅阵列封装件中的芯片的周界延伸。
具体实施方式
根据本发明的实施例，终止于硅基板内的沉陷沟槽填充有诸如掺杂质多晶硅或金属材料的高导电材料。沉陷沟槽与其中形成有栅极沟槽的有源区横向隔开预定距离。沉陷沟槽宽于栅极沟槽并延伸成深于栅极沟槽，且仅沿其侧壁以绝缘体作衬里。该项技术消除了由于扩散沉陷槽方法的侧部扩散造成的区域损失，并且与扩散相比较，由于使用了更导电的材料而提高了导通电阻。而且，该项技术需要远比金属填充沟槽从芯片的顶部延伸到其底部的技术中需要的沟槽更浅的沟槽。由于电流无需经过基板整个深度以到达漏极接触，所以导通电阻得以提高。
图1示出了根据本发明示例性实施例的垂直沟槽型栅极功率MOSFET结构100的简化横截面视图。n型外延层104在形成背面漏极的n型基板102上方延伸。沉陷沟槽106从外延层104的顶表面延伸穿过外延层104并终止于基板102内。介电层110为沉陷沟槽侧壁的衬里。介电层110可以由以下任一种制成：氧化物、氮化硅、氮氧化硅、氧化物和氮化物的多层结构、任何公知的低k绝缘材料、以及任何公知的高k绝缘材料。本公开中所使用的“氧化物”是指化学气相沉积的氧化物(SixOy)或热生长(thermally grown)的二氧化硅(SiO2)。沉陷沟槽106填充有导电材料108，诸如掺杂质的多晶硅、选择性外延硅(SEG)、金属、或金属化合物。导电材料108沿沉陷沟槽106的底部与基板102电接触。因此，导电材料108使得沿顶部可获得背面漏极，以便于互相连接。由于漏极接触移动至顶表面，因此不再需要用于与基板102接触的背面金属，但该背面金属可以用于与顶部接触相结合。用于其它目的，诸如防止芯片断裂和提高器件的热传输特性，可以包含背面金属层。
P型导电性的阱区域(well region)114沿外延层104的上部延伸。栅极沟槽112与沉陷沟槽106横向隔开预定距离S1，并从顶表面垂直地延伸穿过P型阱区域114，终止于外延层104内的预定深度处。沉陷沟槽106比栅极沟槽112宽且深。栅极沟槽112以介电层116作衬里。沿栅极沟槽112底部的电介质可以选择性地做得比沿栅极沟槽侧壁的电介质更厚。每个栅极沟槽112均包括栅电极118以及介电层120，介电层120位于栅电极118顶部上，用于减小栅极到漏极的电容。n型导电性的源极区域122沿阱区域114的上部延伸。源极区域122沿垂直方向与栅电极118交叠。可见，阱区域114终止于远离沉陷沟槽106的一距离处。在一个实施例中，该距离由器件闭塞额定电压来控制。在另一实施例中，阱区域114终止于沉陷沟槽106处并与之邻接。在该实施例中，为获得更高的闭塞额定电压，由于沉陷介电层需要承受更高的电压，所以沿沉陷沟槽侧壁的介电层的厚度需要做得较厚。如果为实现电流操纵目的，导电材料108需要具有最小宽度，这就可能需要更宽的沉陷沟槽。
在导通状态，从源极区域122到外延层104的传导通道沿栅极沟槽侧壁形成于阱区域114中。因此，电流从漏极端子124垂直地流过沉陷沟槽106的导电材料108，然后横向流过基板102，并最终垂直流过外延层104、阱区域114中的传导通道、以及源极区域122，流到源极端子126。
尽管通常将栅极沟槽的宽度保持在与制造技术允许的最大封装密度相对应的很小宽度的水平上，然而通常更需要的是较宽的沉陷沟槽。较宽的沉陷沟槽更易于填充、具有较低的电阻，并且如果需要可以更容易延伸得更深。在一个实施例中，沉陷沟槽106和栅极沟槽114同时形成。这有利于沉陷沟槽与有源区自对中。在该实施例中，需要考虑多种因素而认真地选择沉陷沟槽和栅极沟槽的宽度以及沉陷沟槽106与有源区之间的间距S1。首先，需要选择沉陷沟槽106的宽度Ws与栅极沟槽112的宽度Wg之比，以使得一旦沟槽蚀刻步骤完成，沉陷沟槽106和栅极沟槽112终止于所需的深度处。第二，需要谨慎地选择宽度比以及间距S1，以使得当同时蚀刻具有不同特性的沟槽时所发生的微载荷效应(micro-loadingeffect)最小。如果没有正确地处理，微载荷效应可能造成带有宽开口的沟槽具有比顶部宽的底部。这可能造成诸如在沉陷沟槽中的导电材料中形成针孔的问题。微载荷效应还可以通过选择适当的蚀刻材料而最小化。第三，沟槽的宽度以及间距S1影响器件的导通电阻Ron。在A.Andreini等人发表于1986年12月的IEEE(Transactionon Electron Device)Vol.ED-33，No.12，pp2025-2030的题为“一种结合了双极线性、CMOS逻辑和DMOS功率部件的新型集成硅栅极技术”的文章中，在2028页的IV-B部分中提出了一个公式，该公式可以用来确定对应于所需Ron的最优沟槽宽度和间距S1。尽管该文章中所描述的功率器件使用了扩散沉陷，但涉及最优化Ron的相同原理可以应用于本发明中。该文章结合于此作为参考。
沉陷沟槽宽度与栅极沟槽宽度之比还依赖于沉陷沟槽中所使用的导电材料的类型。通常，希望沉陷沟槽宽度与栅极沟槽宽度之比小于10∶1。在使用掺杂质多晶硅作为导电材料的一个实施例中，希望沉陷沟槽宽度与栅极沟槽宽度之比小于5∶1。例如，对于0.5μm的栅极沟槽宽度，将在约0.7μm至2.5μm的范围内选择沉陷沟槽宽度。如果在沉陷沟槽中使用金属或其它高导电材料，则更需要较高的比例(例如，3∶1)。除了沟槽相对宽度之外，沉陷沟槽与有源区之间的间距S1也影响微载荷效应。较小的间距通常导致较小的微载荷效应。
在一个实施例中，外延层中栅极沟槽的深度被选择成靠近基板102与外延层104之间的界面，从而稍宽的沉陷沟槽将透过以接触基板102。在可替换实施例中，栅极沟槽和沉陷沟槽都终止于基板102内。
在另一实施例中，沉陷沟槽和栅极沟槽在不同的时间形成。尽管沉陷沟槽将不与有源区自对中，但是间距S1不是关键尺寸。在不同时间形成两个沟槽的优点包括：微载荷效应的消除以及单独优化每个沟槽的能力。
根据本发明的实施例，以下为形成图1所示功率晶体管的方法，其中，沉陷沟槽和栅极沟槽同时形成。在基板102上方形成外延层104。然后，使用掩模层来对栅极沟槽和沉陷沟槽开口进行图案化。使用传统的等离子蚀刻技术来对硅进行蚀刻，以形成沉陷沟槽和栅极沟槽。然后，沿栅极沟槽和沉陷沟槽的侧壁和底部形成绝缘层(例如，氧化物)。由于来自损耗层的一些电压将由绝缘层承受从而通过沉陷沟槽的使用减少了被消耗的硅区域，所以，增加绝缘厚度或增加绝缘材料的介电常数将有利于损耗区与沉陷沟槽之间的区域以及距离S1的最小化。
在所有沟槽中的氧化物层上方形成氮化物层。然后，使用传统光刻工艺和各向异性蚀刻技术，从沉陷沟槽底部去除氧化物层和氮化物层，从而沿沉陷沟槽内壁留下氧化物-氮化物的双层。可替换地，可以使用各向异性和各向同性蚀刻的组合或仅使用各向同性蚀刻。可以有利地使用各向异性和各向同性蚀刻的组合，以从沟槽沉陷的下侧壁部(例如，在基板或甚至外延层中延伸的那些下侧壁部，这将有利地减小导通电阻)分别去除氮化物和氧化物层。沿沉陷沟槽侧壁所得到的较厚的介电双层有利地能够承受更高的漏极电压。然后，用原位的(in-situ)掺杂质的多晶硅填充沉陷沟槽和栅极沟槽。之后，对掺杂质的多晶硅进行反蚀刻(etch back)，以相对于外延层104的顶表面而平坦化沟槽中的多晶硅的顶部。然后，使用掩模层来覆盖沉陷沟槽，从栅极沟槽中去除多晶硅和氧化物-氮化物的双层。然后以栅极氧化层作栅极沟槽的衬里，并用栅极多晶硅材料填充栅极沟槽。使用传统的光刻工艺和蚀刻工艺去除沉陷沟槽上方的多余栅极多晶硅，以对栅电极进行图案化。用于在栅电极、阱区域、源极区域、源极和漏极金属接触层的上方形成绝缘层的其余工艺步骤，以及完成器件的其它步骤根据传统方法来进行。
在替换方法中，在形成沟槽之后，沿栅极沟槽和沉陷沟槽的侧壁和底部形成厚氧化层(如上所述，以减小沉陷沟槽到阱区域的间距)。然后，使用传统的光刻工艺和各向异性蚀刻技术从沉陷沟槽的底部去除厚氧化层，从而在保护栅极沟槽的同时留下以厚氧化物作衬里的沉陷沟槽的侧壁。可替换地，也可以使用各向异性和各向同性蚀刻的组合，以从沟槽沉陷侧壁的下部去除厚氧化物。氧化层可以用作用于栅极沟槽的牺牲性的(sacrificial)绝缘层，以提高栅极氧化物的完整性。然后，用原位的掺杂质的多晶硅填充沉陷沟槽和栅极沟槽。然后，对掺杂质的多晶硅进行反蚀刻，以使相对于外延层104的顶表面而平坦化沟槽中的多晶硅的顶部。然后，使用掩模层来覆盖沉陷沟槽，从栅极沟槽中去除多晶硅和绝缘层。然后以栅极绝缘层作栅极沟槽的衬里，并用栅极多晶硅材料填充栅极沟槽。使用传统的光刻工艺和蚀刻工艺去除沉陷沟槽上方的多余栅极多晶硅，以对栅电极进行图案化。用于在栅电极、阱区域、源极区域、源极和漏极金属接触层的上方形成绝缘层的其余工艺步骤以及完成器件的其它步骤根据传统方法来进行。
在另一方法中，一旦形成沟槽，就沿栅极沟槽和沉陷沟槽的侧壁和底部形成(生长或沉积)绝缘层(例如栅极氧化物)。然后，使用传统的光刻工艺和各向异性蚀刻技术从沉陷沟槽的底部去除栅极氧化层，从而在保护栅极沟槽的同时留下作为沉陷沟槽侧壁衬里的氧化层。可替换地，可以使用各向异性和各向同性蚀刻的组合或仅使用各向同性蚀刻。可以有利地使用各向异性和各向同性蚀刻的组合，以从沟槽沉陷的下侧壁部(例如，在基板或甚至外延层中延伸的那些下侧壁部，这将有利地减小导通电阻)去除栅极氧化层。然后，用原文掺杂质的多晶硅填充沉陷沟槽和栅极沟槽。然后，使用传统的光刻技术对掺杂质的多晶硅进行图案化，并进行蚀刻，以形成沉陷(漏)电极和栅电极。用于在栅电极、阱区域、源极区域、源极和漏极金属接触层的上方形成绝缘层的其余工艺步骤以及完成器件的其它步骤根据传统方法来进行。
在又一方法中，通过使用独立的掩模步骤来独立地形成沉陷沟槽和栅极沟槽。例如，使用第一组掩模和工艺步骤来对栅极沟槽进行限定和蚀刻，以栅极氧化物作衬里，并用多晶硅填充。使用第二组掩模和工艺步骤来对沉陷沟槽进行限定和蚀刻，沿其侧壁以介电层作衬里，并用导电材料填充。形成沉陷沟槽和栅极沟槽的顺序可以颠倒。
图2示出了根据本发明示例性实施例的具有沉陷沟槽的功率器件的简化俯视布局图。图2的布局图表示带状的单元结构。带状栅极沟槽212a垂直地延伸，并终止于水平延伸的栅极沟槽212b。如所示，三组带状栅极沟槽被连贯沉陷沟槽206环绕。在图3所示的替换实施例中，沉陷沟槽306设置在栅极沟槽组(仅示出了两组)之间，并以由所需Ron控制的频率和间距进行重复。在该实施例的一个变型中，为了获得与背面漏极接触方法相同的Ron，相邻的沉陷沟槽之间的间距需要是晶片厚度的两倍。例如，对于4密耳(mil)厚的晶片，沉陷沟槽可以彼此隔开约8密耳。即使对于较低的Ron，沉陷沟槽也可以更靠近地放置在一起。在图4所示的再一实施例中，带状栅极沟槽412水平地延伸，而垂直延伸的沉陷沟槽406与不同组的栅极沟槽相隔开。沉陷沟槽406通过金属互连件432互相连接。沿视图的右侧示出了放大的金属互连件，其形成了用于接合线(bond-wire)连接的漏极焊盘。此外，在一组栅极沟槽的切除角部中还示出了栅极焊盘430。
图5示出了容纳根据本发明实施例的具有沉陷沟槽的功率器件的芯片的俯视图。小圆圈表示球栅阵列封装件中的球。外围区域506包括沉陷沟槽，并且因此外围区域506中的球提供了漏极连接。中央区域507表示有源区，并且该区域内部的球提供了源极连接。中央区域508左下角处的小方形区域530表示栅极焊盘，并且区域530内部的球提供了栅极连接。
很显然，图1中的沉陷沟槽结构106可以用来将任何功率器件的背面连接引至顶表面，并且不限于与垂直沟槽栅极功率MOSFET一起使用。相同或类似的沉陷沟槽结构可以类似地与诸如平面栅极MOSFET(即，该MOSFET具有栅极且其下层通道区在硅表面上方并与之平行地延伸)的其它垂直导电功率器件以及功率二极管集成，以使沿顶部可获得阳极或阴极接触区，用于相互连接。许多其它变型和替换是可能的，包括在具有各种充电平衡技术的不同组合中使用屏蔽栅极和双重栅极结构，它们中的很多在2004年12月29日提交的题为“功率半导体器件及其制造方法”的、上述参考的、普通转让的专利申请(申请号11/026,276)中得以详细描述，其全部内容结合于此作为参考。而且，尽管图2-5示出了根据开口单元结构的布局实施方式，但本发明并不限于此。图1所示的结构也可以以多个公知公开的单元结构中的任何一个来实施。最后，图1横截面图中的尺寸以及图2-5中的俯视布局图不是成比例的，而主要是说明性的。

Claims (40)

1.一种半导体功率器件，包括：
第一导电型基板；
第一导电型外延层，所述外延层位于所述基板的上方并与所述基板相接触；
第一沟槽，延伸到并终止于所述外延层内；
沉陷沟槽，从所述外延层的顶表面延伸穿过所述外延层并终止于所述基板内，所述沉陷沟槽与所述第一沟槽横向隔开，所述沉陷沟槽比所述第一沟槽宽且延伸得更深，所述沉陷沟槽仅沿所述沉陷沟槽的侧壁以绝缘体作衬里，使得填充所述沉陷沟槽的导电材料沿所述沟槽的底部与所述基板进行电接触，并沿所述沟槽的顶部与互连层进行电接触。
2.根据权利要求1所述的半导体功率器件，进一步包括：
第二导电型阱区域，位于所述外延层中；
第一导电型源极区域，位于所述阱区域中，所述源极区域在所述第一沟槽的侧部；
栅极介电层，至少作为所述第一沟槽的侧壁的衬里；以及
栅电极，至少部分地填充所述第一沟槽，
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域电接触的源极接触层、以及与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
3.根据权利要求1所述的半导体功率器件，其中，所述导电材料包括以下中的一种或多种：掺杂质的多晶硅、选择性外延硅(SEG)、金属、和金属化合物。
4.根据权利要求1所述的半导体功率器件，其中，所述绝缘体包括以下之一：氧化物、氮化硅、氮氧化硅、氧化物和氮化物的多层、低k绝缘材料、和高k绝缘材料。
5.一种半导体功率器件，包括：
第一导电型基板；
第一导电型外延层，所述外延层位于所述基板上方并与所述基板相接触；
第二导电型阱区域，位于所述外延层中；
栅极沟槽，其延伸穿过所述外延层和所述阱区域并终止于所述基板内，所述栅极沟槽包括至少作为所述栅极沟槽的侧壁衬里的栅极介电层，以及至少部分地填充所述栅极沟槽的栅电极；
第一导电型源极区域，其位于所述阱区域中，所述源极区域在所述栅极沟槽的侧部；以及
沉陷沟槽，从所述外延层的顶表面延伸穿过所述外延层并终止于所述基板内，所述沉陷沟槽与所述第一沟槽横向隔开，所述沉陷沟槽比所述第一沟槽宽，所述沉陷沟槽仅沿所述沉陷沟槽侧壁以绝缘体作衬里，使得填充所述沉陷沟槽的导电材料沿所述沟槽的底部与所述基板进行电接触，并沿所述沟槽的顶部与互连层进行电接触。
6.根据权利要求5所述的半导体功率器件，其中，所述导电材料包括以下中的一种或多种：掺杂质的多晶硅、选择性外延硅(SEG)、金属、和金属化合物。
7.根据权利要求5所述的半导体功率器件，其中，所述绝缘体包括以下之一：氧化物、氮化硅、氧化物和氮化物的多层、氮氧化硅、低k绝缘材料、和高k绝缘材料。
8.一种形成半导体功率器件的方法，包括：
在基板上方并与所述基板接触地形成外延层，所述外延层和所述基板是第一导电型的；
限定用于形成第一沟槽的第一开口以及用于形成沉陷沟槽的第二开口，所述第二开口宽于所述第一开口；
进行硅蚀刻，通过所述第一和第二开口同时蚀刻，以形成所述第一沟槽和所述沉陷沟槽，使得所述第一沟槽终止于所述外延层内，而所述沉陷沟槽终止于所述基板内；
以绝缘体作为所述沉陷沟槽的侧壁的衬里；
用导电材料填充所述沉陷沟槽，使得所述导电材料沿所述沉陷沟槽的底部与所述基板进行电接触；以及
在所述外延层上方形成互连层，所述互连层沿所述沉陷沟槽的顶表面与所述导电材料进行电接触。
9.根据权利要求8所述的方法，其中，所述第一沟槽宽度与所述沉陷沟槽宽度的比率根据所述第一沟槽和所述沉陷沟槽的目标深度而预先选择。
10.根据权利要求8所述的方法，其中，预先选择所述第一沟槽宽度与所述沉陷沟槽宽度的比率以及所述第一沟槽与所述沉陷沟槽之间的间距，以使微载荷效应最小。
11.根据权利要求9所述的方法，其中，所述比率小于4∶1。
12.根据权利要求8所述的方法，其中，所述导电材料包括多晶硅，并且所述比率为大约2∶1。
13.根据权利要求8所述的方法，其中，所述衬里步骤中的绝缘体是氮化物-氧化物的双层。
14.根据权利要求8所述的方法，其中，所述绝缘体包括以下之一：氧化物、氮化硅、氧化物和氮化物的多层、氮氧化硅、低k绝缘材料、和高k绝缘材料。
15.根据权利要求8所述的方法，进一步包括：
在所述外延层中形成第二导电型的阱区域；
在所述阱区域中形成第一导电型的源极区域，使得所述源极区域在所述第一沟槽的侧部；
形成至少作为所述第一沟槽的侧壁的衬里的栅极介电层；以及
形成至少部分地填充所述第一沟槽的栅电极，
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域电接触的源极接触层、以及与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
16.根据权利要求8所述的方法，其中，等离子蚀刻用于进行所述硅蚀刻。
17.根据权利要求8所述的方法，其中，在所述衬里步骤中，所述第一沟槽的侧壁也以所述绝缘体作衬里，所述方法进一步包括：
仅从所述沉陷沟槽的底部去除所述绝缘体，使得所述基板沿所述沉陷沟槽的底部被露出。
18.根据权利要求8所述的方法，进一步包括：
在所述填充步骤之前，使用各向异性蚀刻从所述沉陷沟槽的下部去除所述绝缘体。
19.根据权利要求8所述的方法，其中，
所述衬里步骤包括，用所述绝缘体同时为所述沉陷沟槽和所述第一沟槽的侧壁和底部作衬里，并且
所述填充步骤包括，用原位掺杂质的多晶硅同时填充所述沉陷沟槽和所述第一沟槽；
所述方法进一步包括：
在所述填充步骤之前，仅从所述沉陷沟槽的底部去除所述绝缘体；
至少从所述第一沟槽的内部去除所述多晶硅和所述绝缘体；
形成作为所述第一沟槽的侧壁和底部的衬里的栅极电介质；以及
在所述第一沟槽中形成栅电极。
20.根据权利要求8所述的方法，其中：
所述衬里步骤包括，用栅极电介质同时为所述沉陷沟槽和所述第一沟槽的侧壁和底部作衬里；以及
所述填充步骤包括，用原位掺杂质的多晶硅同时填充所述沉陷沟槽和所述第一沟槽，
所述方法进一步包括：
在所述填充步骤之前，仅从所述沉陷沟槽的底部去除所述栅极电介质。
21.一种形成场效应晶体管的方法，所述方法包括：
在基板上方并与所述基板接触地形成外延层，所述外延层和所述基板是第一导电型的；
限定用于形成栅极沟槽的第一开口以及用于形成沉陷沟槽的第二开口，所述第二开口宽于所述第一开口；
进行硅蚀刻，通过所述第一和第二开口同时蚀刻，以形成所述栅极沟槽和所述沉陷沟槽，使得所述栅极沟槽终止于所述外延层内，而所述沉陷沟槽终止于所述基板内；
以绝缘体作为所述沉陷沟槽和所述栅极沟槽的侧壁和底部的衬里；以及
从所述沉陷沟槽的下部去除所述绝缘体；
用掺杂质的多晶硅填充所述沉陷沟槽和所述栅极沟槽，使得所述导电材料沿所述沉陷沟槽的下部与所述基板进行电接触。
22.根据权利要求21所述的方法，进一步包括：
在所述外延层中形成第二导电型的阱区域；
在所述阱区域中形成第一导电型的源极区域，使得所述源极区域在所述栅极沟槽的侧部；
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域和所述阱区域电接触的源极接触层、以及通过所述沉陷沟槽与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
23.根据权利要求21所述的方法，其中，所述栅极沟槽宽度与所述沉陷沟槽宽度的比率根据所述第一沟槽和所述沉陷沟槽的目标深度而预先选择。
24.根据权利要求21所述的方法，其中，预先选择所述栅极沟槽宽度与所述沉陷沟槽宽度的比率以及所述栅极沟槽与所述沉陷沟槽之间的间距，以使微载荷效应最小。
25.根据权利要求21所述的方法，其中，所述比率小于4∶1。
26.根据权利要求21所述的方法，其中，在所述衬里步骤中的所述绝缘体为氧化物-氮化物的双层。
27.根据权利要求21所述的方法，其中，所述沉陷沟槽的下部包括沟槽底部以及沿所述基板延伸的所述沉陷沟槽的下侧壁部。
28.一种半导体功率器件，包括：
多组带状沟槽，其在基板上方的硅区域中延伸；
连贯沉陷沟槽，其完全包围所述多组带状沟槽中的每一组，以便使所述多组带状沟槽彼此绝缘，所述连贯沉陷沟槽从所述硅区域的顶表面延伸穿过所述硅区域并终止于所述基板内，所述连贯沉陷沟槽仅沿所述沉陷沟槽的侧壁以绝缘体作衬里，使得填充所述连贯沉陷沟槽的导电材料沿所述连贯沉陷沟槽的底部与所述基板进行电接触，并沿所述连贯沉陷沟槽的顶部与互连层进行电接触。
29.根据权利要求28所述的半导体功率器件，其中，所述硅区域是外延层，并且所述多个带状沟槽是栅极沟槽，所述半导体器件进一步包括：
第二导电型阱区域，其位于所述外延层中；
第一导电型源极区域，其位于所述阱区域中，所述源极区域在所述栅极沟槽的侧部；
栅极介电层，至少作为每个所述栅极沟槽的侧壁的衬里；
以及
栅电极，至少部分地填充每个所述栅极沟槽，
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域电接触的源极接触层、以及与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
30.根据权利要求28所述的半导体功率器件，其中，所述导电材料包括以下中的一种或多种：掺杂质的多晶硅、选择性外延硅(SEG)、金属、和金属化合物。
31.根据权利要求28所述的半导体功率器件，其中，所述连贯沉陷沟槽比所述多个带状沟槽宽且延伸得更深。
32.一种半导体功率器件，包括：
多组带状栅极沟槽，其在基板上方的硅区域中延伸；
多个带状沉陷沟槽，所述多个带状沉陷沟槽中的每一个均在所述多组带状栅极沟槽中的两个相邻组之间延伸，所述多个带状沉陷沟槽从所述硅区域的顶表面延伸穿过所述硅区域并终止于所述基板内，所述多个带状沉陷沟槽仅沿所述沉陷沟槽的侧壁以绝缘体作衬里，使得填充每个所述沉陷沟槽的导电材料沿所述沉陷沟槽的底部与所述基板进行电接触，并沿所述沉陷沟槽的顶部与互连层进行电接触。
33.根据权利要求32所述的半导体功率器件，其中，所述硅区域是外延层，所述半导体器件进一步包括：
第二导电型阱区域，其位于所述外延层中；
第一导电型源极区域，位于所述阱区域中，所述源极区域在所述多组带状栅极沟槽的侧部；
栅极介电层，其至少作为每个所述栅极沟槽的侧壁的衬里；以及
栅电极，其至少部分地填充每个所述栅极沟槽，
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域电接触的源极接触层、以及与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
34.根据权利要求32所述的半导体功率器件，其中，所述导电材料包括以下中的一种或多种：掺杂质的多晶硅、选择性外延硅(SEG)、金属、和金属化合物。
35.根据权利要求32所述的半导体功率器件，其中，所述多个沉陷沟槽比所述多组带状栅极沟槽宽且延伸得更深。
36.根据权利要求32所述的半导体功率器件，其中，漏极互连层将所述多个带状沉陷沟槽电连接至漏极焊盘，所述漏极焊盘被构造成容纳漏极接合线。
37.一种容纳包括功率器件的芯片的半导体封装器件，所述芯片包括位于基板上方的硅区域，所述半导体封装器件包括：
多个第一沟槽，其在所述硅区域中延伸；
连贯沉陷沟槽，其沿所述芯片的周边延伸，以便完全包围所述多个第一沟槽，所述连贯沉陷沟槽从所述芯片的顶表面延伸穿过所述硅区域并终止于所述基板内，所述连贯沉陷沟槽仅沿所述沉陷沟槽的侧壁以绝缘体作衬里，使得填充所述连贯沉陷沟槽的导电材料沿所述连贯沉陷沟槽的底部与所述基板进行电接触，并沿所述连贯沉陷沟槽的顶部与互连层进行电接触；以及
多个互连球，其设置在栅格阵列中，所述多个互连球的外部组电连接至所述连贯沉陷沟槽中的所述导电材料。
38.根据权利要求37所述的半导体功率器件，其中，所述硅区域是外延层，并且所述多个第一沟槽是栅极沟槽，所述半导体封装器件进一步包括：
第二导电型阱区域，位于所述外延层中；
第一导电型源极区域，位于所述阱区域中，所述源极区域在所述栅极沟槽的侧部；
栅极介电层，其至少作为每个所述栅极沟槽的侧壁的衬里；以及
栅电极，其至少部分地填充每个栅极沟槽，
其中，与所述栅电极电接触的栅电极接触层、与所述源极区域电接触的源极接触层、以及与所述基板电接触的漏极接触层都沿着所述半导体功率器件的一个表面。
39.根据权利要求37所述的半导体功率器件，其中，由所述多个互连球的外部组包围的所述多个互连球的内部组与所述源极接触层电接触。
40.根据权利要求37所述的半导体功率器件，其中，所述连贯沉陷沟槽比所述多个第一沟槽宽且延伸得更深。
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US20120153384A1 (en) 2012-06-21
JP2008509557A (ja) 2008-03-27
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US20060030142A1 (en) 2006-02-09
US7732876B2 (en) 2010-06-08
US8026558B2 (en) 2011-09-27
US20080142883A1 (en) 2008-06-19
CN100576466C (zh) 2009-12-30
US7352036B2 (en) 2008-04-01
HK1112112A1 (en) 2008-08-22
WO2006017376A2 (en) 2006-02-16
DE112005001675T5 (de) 2007-06-14
US8148233B2 (en) 2012-04-03
US20100237415A1 (en) 2010-09-23
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KR100848968B1 (ko) 2008-07-30

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