CN101106113A - 一种集成电路器件封装体及其组装方法 - Google Patents

一种集成电路器件封装体及其组装方法 Download PDF

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Publication number
CN101106113A
CN101106113A CNA2007101040260A CN200710104026A CN101106113A CN 101106113 A CN101106113 A CN 101106113A CN A2007101040260 A CNA2007101040260 A CN A2007101040260A CN 200710104026 A CN200710104026 A CN 200710104026A CN 101106113 A CN101106113 A CN 101106113A
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Prior art keywords
tube core
interpolater
packaging body
plethora
contact pad
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CN100595911C (zh
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雷泽厄·拉曼·卡恩
萨姆·齐昆·赵
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Avago Technologies General IP Singapore Pte Ltd
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Zyray Wireless Inc
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Abstract

本发明介绍一种改进的IC器件封装体及其组装方法。一方面，IC器件封装体包括IC管芯，该管芯上带有一个或多个接触焊盘，每个接触焊盘都设置在IC管芯表面上对应的热点上。该封装体还包括导热内插器，其在接触焊盘处热连接到IC管芯上。另一方面，在IC管芯和内插器之间的空间内填充有底层填料。内插器还可电连接到IC管芯上。此外，内插器和IC管芯之间可通过热互连件或节瘤相互连接。

Description

一种集成电路器件封装体及其组装方法
技术领域
本发明涉及集成电路(IC)器件封装技术，更具体地说，涉及IC半导体管芯热点的冷却、模压塑料IC封装体的散热和IC封装体中的热互联技术。
背景技术
电信号是由流经制作在半导体衬底上的大规模集成电路(IC)中的导线和晶体管的电流来承载的。电流所承载的能量中有一部分在电流流经IC过程中以热量的形式耗散掉。电子半导体IC所产生的热量也称为功耗、功率耗散(power dissipation)或散耗热(heat dissipation)。IC中生成的热量P为动态功率PD和静态功率PS之和，即：
P＝PD+PS＝ACV2f+VIleak
其中A是门电路活跃因子(gate activity factor)，C是所有门电路(gate)的总电容负载，V2是峰至峰电源电压摆幅，f是频率，Ileak是漏电流。静态功率Ps＝VIleak，是漏电流Ileak导致的静态功率耗散。有关静态功率在Kim等人编写的于2003年12月发表于IEEE Computer 36(12)第68-75页上的LeakageCurrent：Moore’s Law Meet Static Power中进行了详细的描述，本文也引用了其中的全部内容。
动态功率PD＝ACV2f，是IC器件电容负载充电和放电过程中的动态功率损耗。因此动态功耗正比于工作频率和工作电压的平方。静态功耗正比于工作电压。半导体IC技术中晶体管门电路尺寸(gate size)的缩小降低了单个晶体管的工作电压和功率耗散。然而，由于产业一直遵循摩尔定律发展，未来技术中芯片功率密度预期将进一步上升。1965年，英特尔共同创始人高登·摩尔预言芯片中晶体管的数量将每两年增加一倍。除了芯片中晶体管数量会增加以外，依照2004年国际半导体技术发展蓝图(ITRS蓝图)(http://www.itrs.net/Common/2004Update/2004_00_Overview.pdf)，工作频率也将每两年提高一倍。电压降低会加大在噪声容限控制方面的难度，因此对于130nm及更短的栅极长度(gate lengths)而言，工作电压再也无法像过去一样降低的那样迅速。因此，芯片的功率耗散将继续上升。详情参见ITRS蓝图表6。随着制造过程中更多的采用65nm技术，以及45nm技术的商业化，功耗问题目前已成为半导体工业中的主要技术问题。
IC芯片的另一特征在于半导体管芯温度的非均匀分布。在片上系统(system-on-chip，SOC)设计中，单块芯片上集成的功能模块越来越多。较高的功率密度区会产生非均匀温度分布现象，在芯片上导致“热点(hotspots)”的出现，热点也称为“热区(hot blocks)”。热点在芯片上产生的温差可达5℃至30℃左右。在Shakouri和Zhang编写的“0n-Chip Solid-State CoolingFor Integrated Circuits Using Thin-Film Microrefrigerators”IEEETransaction on Components and Packaging TechnologiesVol.28，No.1，March，2005，pp.65-69中对热点进行了详细的描述，本文也引用了其中的全部内容。
由于载流子迁移率与温度成反比，因此时钟速度通常必须根据芯片上的最热点来进行设计。因此，热设计是基于这些芯片上的热点温度来进行的。同时，若由于管芯(die)上的片上温度变化而无法在IC管芯上得到统一的载流子迁移率，则将会导致信号速度的变化，并使得电路时钟控制变得复杂。
过去，散热器(包括内嵌(drop-in)散热器、散热片和散热管)被用于提高IC封装体的热性能。2003年4月22日授权的名称为“SemiconductorPackage Having An Exposed Heat Spreader”美国专利No.6552428中对散热器实例进行了详细的描述，本文也引用了其中的全部内容。由Zhao和Avedisian编写的“Enhancing Forced Air Convection Heat Transfer FromAn Array Of Parallel Plate Fins Using A Heat Pipe”Int.J.Heat MassTransfer，Vol.40，No.1，pp.3135-3147(1997)中对散热管实例进行了详细的描述。
例如，图1展示了管芯朝上塑胶球栅阵列封装体(PBGA)封装体100，其上集成了内嵌散热器104。在封装体100中，IC管芯102通过管芯粘合材料106贴装在衬底110上，并与引线(wirebond)114相连。封装体100可通过焊球108连接到印刷线路板(PWB)(未示出)上。内嵌式散热器104设置在衬底110上，用于排出管芯102的热量。塑封材料112将封装体100密封起来，其中包括管芯102、引线114、部分或全部内嵌散热器104和衬底110的部分或全部上表层。内嵌散热器104通常由铜或者热传导性优于塑封材料112的其它材料制成。铜的热传导值在390W/m*℃左右，塑封材料的热传导值为0.8W/m*℃左右。
如图1所示的热性能增强方法的原理是将热量从整个芯片或整个封装体中移除。通过对整个芯片不加区分地进行冷却，将半导体温度维持在工作上限以下。相对于芯片的其它部位，这些方法通常不足以降低热点的温度，或者在降低热点温度方面根本不起作用，因此芯片的工作仍受到热点的限制。
例如，图2A展示了硅管芯102的透视图，并且特别展示了未使用外部散热片的PBGA中硅管芯102上的温度分布情况。管芯102上的温差为13.5℃。图2B展示的是在封装体中增加了内嵌散热器和散热片之后，图2A中管芯102的情况。在露出的内嵌散热器上面贴装大尺寸(45mm×45mm×25mm)外部铝质pin-fin散热片后，温差仍为13.0℃。无论是内嵌散热器还是外部散热片，在降低由热点引起的片上温差方面都是无效的。
在本领域中还有一种冷却方法，这就是使用电能来排出IC芯片热量的主动式片上冷却方法。例如，一些人建议在硅片上刻出微型管道，然后泵入液体冷却剂使其围绕半导体管芯循环流动，以带走残余的热量。由Bush编写的于2005年7月20日发表在Electronic News上的“Fluid Cool ing Plugs Direct onto CMOS”(http://www.reed-electronics.com/electronicnews/article/CA626959？nid＝2019&rid＝550846255)对液体冷却方法进行了详细的介绍，本文也引用了其中的全部内容。还可参见由Singer编写的于2005年7月20日发表在Electronic News上的“Chip Heat Removal with Microfluidic BacksideCooling”，本文也引用了其中的全部内容。
此外，还开发出了使用薄膜热电冷却器(TEC)来提供主动片上冷却的其它主动冷却方法。与使用TEC的片上冷却有关的内容在由Snyder等人编写的“Hot Spot Cooling using Embedded Thermoelectric Coolers”(22ND IEEESEMI-THERM，Symposium，pp.135-143(2006))中进行了详细的描述，本文也引用了其中的全部内容。
这些主动冷却方法要求使用外部的昂贵流体循环或微冷却系统，并且会增加封装体的整体功耗，然而该功耗正是要必须消除的。此外，还需要在IC封装体中集成独立的电源来驱动流体泵或TEC系统。这些部件非常昂贵，而且还会降低部件的可靠性。由于这些解决方案通常都很昂贵，因此在成本敏感应用如消费类电子器件中，其使用受到限制。
上面描述的这些冷却方法不足以和/或难于实现商业化应用，或者成本过高。因此，需要一种低廉可靠的系统和方法，可以选择性的排出半导体管芯上热区或热点的热量。
发明内容
本文描述的是用于改善集成电路封装体的方法、系统和装置。
在本发明的一个方面，集成电路(IC)器件封装体包括IC管芯，该管芯具有至少一个接触焊盘(contact pad)，每个接触焊盘都设置在对应的热点处。封装体中还包括导热内插器(interposer)，其与IC管芯热连接。在本发明的另一方面，在IC管芯和内插器之间填充有底层填料(underfill material)。
在本发明的一个方面，内插器还可电连接到IC管芯。在本发明的另一方面，内插器和IC管芯通过热互连元件(也称为热互连件或节瘤)实现连接。在实施例中，IC封装体可以是依照管芯朝上方法设计的，也可以是依照管芯朝下方法设计的。
在本发明的一个方面，散热器热连接到内插器上。在本发明的另一方面，散热器还可电连接到内插器上。在本发明的又一实施例中，散热器通过焊球或散热块(heat slug)热连接和/或电连接到内插器上。
在本发明的一个方面，散热块设置为连接到印刷电路板(PCB)。在本发明的另一实施例中，内插器设置为连接到PCB上。
在本发明的一个方面，使用一种方法将IC封装体组装起来，该方法中包括通过对应的接触焊盘上的至少一个节瘤(nodule)将内插器热连接到IC管芯上。在本发明的一个方面，在热连接到IC管芯之前，在内插器上设置一些凸起。在本发明的一个方面，在热连接到内插器之前，在IC管芯上设置一些凸起。在本发明的另一方面，IC管芯和内插器之间是电连接的。
在本发明的一个方面，内插器和IC管芯之间的空间填充有底层填料。在本发明的一个方面，内插器热连接到散热块(heat slug)、散热器(heatspreader)、散热片(heat sink)、另一内插器或焊球上。
在本发明的一个方面，将IC封装体组装起来，以将其安装到PCB上。在本发明的另一方面，将IC封装体组装起来，使得该封装体热连接到PCB上。在另一方面，将封装体组装起来，使得该封装体电连接到PCB上。
根据本发明的一个方面，提供了一种集成电路(IC)器件封装体，包括：
带有接触焊盘的IC管芯，所述接触焊盘设置在所述IC管芯的表面上且位于所述IC管芯的热点处；
导热内插器，包含第一和第二表面，所述内插器的第一表面在所述接触焊盘处连接到所述IC管芯。
在本发明所述的封装体中，还包括：
所述内插器第一表面和所述接触焊盘之间的热互连件。
在本发明所述的封装体中，还包括：
底层填料，其充分填充所述IC管芯表面和所述内插器第一表面之间的空间。
在本发明所述的封装体中，所述内插器第一表面设有至少一个柱体。
在本发明所述的封装体中，所述内插器具有导电性。
在本发明所述的封装体中，所述内插器第一表面电连接到所述接触焊盘。
在本发明所述的封装体中，还包括：
至少一个导热节瘤，所述内插器第一表面通过所述至少一个导热节瘤连接到所述IC管芯。
在本发明所述的封装体中，所述至少一个节瘤具有导电性。
在本发明所述的封装体中，所述封装体为管芯朝下IC器件封装体。
在本发明所述的封装体中，所述封装体为管芯朝上IC器件封装体。
在本发明所述的封装体中，还包括：
散热器，其安装在所述内插器的第二表面上。
在本发明所述的封装体中，所述散热器电连接到所述内插器的第二表面上。
在本发明所述的封装体中，还包括：
散热块，其安装在所述内插器的第二表面上。
在本发明所述的封装体中，所述散热块电连接到所述内插器的第二表面。
在本发明所述的封装体中，所述散热块用于连接印刷电路板(PCB)。
在本发明所述的封装体中，所述内插器第二表面用于连接印刷电路板(PCB)。
在本发明所述的封装体中，所述管芯的表面设有第二接触焊盘，用于引线连接。
在本发明所述的封装体中，所述第一接触焊盘位于所述管芯的中心，所述第二接触焊盘位于所述管芯表面的四周区域内。
在本发明所述的封装体中，还包括：
至少一个另外的热互连件；
所述管芯的表面包括至少一个另外的接触焊盘，其位于所述IC管芯的至少一个热点上，每个所述另外的热互连件连接在对应的另外的接触焊盘和所述内插器的第一表面之间。
在本发明所述的封装体中，所述热互连件为焊球。
在本发明所述的封装体中，所述热互连件为块。
在本发明所述的封装体中，所述热互连件为由焊料形成的凸起。
根据本发明的一个方面，提供了一种组装集成电路(IC)封装体的方法，包括：
通过至少一个节瘤将内插器的第一表面与IC管芯表面的接触焊盘相连接。
在本发明所述的方法中，还包括：
将所述节瘤以凸起的形式设置在所述内插器的第一表面上，所述节瘤在所述第一表面上的位置对应所述IC管芯表面所述接触焊盘的位置。
在本发明所述的方法中，还包括：
将所述节瘤以凸起的形式设置在所述IC管芯第一表面的所述接触焊盘上。
在本发明所述的方法中，还包括：通过所述一个节瘤将所述内插器第一表面电连接到所述IC管芯上。
在本发明所述的方法中，还包括：
使用底层填料填充所述IC管芯表面和所述内插器第一表面之间的空间。
在本发明所述的方法中，还包括：
将所述内插器的第二表面连接到散热块、散热器、另一内插器、散热片、焊球或印刷电路板(PWB)上。
在下面将要进行的对本发明的详细描述中，上述和其它部件、优势和特征将变得更加明显。应注意的是，发明内容和摘要部分可能使用一个或多个实施例，但并未列出发明人可能补充的有关本发明的全部示范性实施例。
附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是带有散热器的现有的管芯朝上BGA封装体的截面示意图；
图2A-图2B是使用现有冷却方法后IC管芯在工作过程中的表面温度示意图；
图3A-图3H是根据本发明示范性实施例的IC管芯、节瘤和内插器的结构示意图；
图4A-图4B是根据本发明示范性实施例的内插器的结构示意图；
图5A-图5B是根据本发明示范性实施例的包含柱体(pillars)的内插器的结构示意图；
图6A-图6F是根据本发明示范性实施例的包含内插器的集成电路(IC)封装体的结构示意图；
图7A-图7B是根据本发明示范性实施例的包含内插器的管芯朝上的IC封装体的结构示意图；
图8是根据本发明示范性实施例的带有包含柱体(posts)的内插器的IC封装体的结构示意图；
图9A-图9D是根据本发明示范性实施例的包含内插器和散热器的IC封装体的结构示意图；
图10A-图10F是根据本发明示范性实施例的包含连接到散热块或焊球的内插器的IC封装体的结构示意图；
图11A-图11B是根据本发明示范性实施例的描述制造方法的流程图。
下面将结合附图及实施例对本发明作进一步说明，附图中相似的标号表示相同或功能相似的部件。此外，图中标号最左边的数字表示该标号第一次出现的附图序号。
具体实施方式
本发明涉及对集成电路(IC)封装体做出的改进及对应的方法。具体来说，本文将要描述的IC封装体可将IC管芯热点上的热量排出。根据本发明的一个示范性实施例，导热内插器与IC管芯上的接触焊盘相连，而至少有一个接触焊盘位于热点处。该内插器因此可将整个IC管芯特别是IC管芯热点上的热量排出，从而降低管芯的总温度以及管芯上的温差。
本申请中出现的“一个实施例”、“实施例”、“示例”等术语，指的是本申请描述的实施例可包括有特定的特征、结构或特性，但是并非每个实施例都必须包括有这些特定特征、结构或特性。此外，该术语也并非必须指同一个实施例。当结合一个实施例介绍特定特征、结构或特性时，可以认为本领域的技术人员能够将该特征、结构或特性结合到其它实施例中，不管本申请中是否有明确的描述。
本申请公开了结合有本发明特征的一个或多个实施例。所公开的实施例仅仅是对本发明的举例，本发明的范围不局限于所公开的实施例，而由本申请的权利要求来定义。
此外，需要理解的是，本申请中所使用的与空间方位有关的描述(例如“上面”、“下面”、“左边”、“右边”、“向上”、“向下”、“顶部”、“底部”等)仅仅是出于举例解释的目的，本申请中所介绍的结构的实际实现可以具有各种不同的方位或方式。
实施例举例
本发明涉及选择性地对集成电路(IC)管芯局部区域进行散热。在一个实施例中，IC管芯上的至少一个接触焊盘上连接有导热内插器结构。接触焊盘设置在IC管芯上的热点处。在另一实施例中，该内插器是导电和/或导热的。在一些实施例中，该内插器通过导热互连元件(也称为热互连件或节瘤(nodule))连接到管芯，这些导热互连元件可以是导热球、导热凸起(bump)以及在组装时贴装在内插器和/或IC管芯上的导热块。在另一实施例中，热节瘤是具有导热和/或导电性。在一个实施例中，内插器热连接和/或电连接到IC管芯。
在一个实施例中，该内插器连接在IC管芯上选定的位置上，例如具有高密度功耗的块(例如管芯表面上的区域)上。这些块产生的热量因此将从IC管芯上排出。在一个实施例中，这些选定的位置可根据在具体应用下管芯的功率图(power map)来设计，而应用不同，功率图便不同，同一IC管芯上的内插器连接位置也就不同。这种情况可能发生在管芯上的不同功能模块根据应用的要求而启动和关闭时。
这里的实施例适用于所有类型的IC器件封装体，例如塑胶球栅阵列封装体(PBGA)、精细倾斜球状网阵排列(BGA)、接点栅格阵列(LGA)、引脚网格阵列(PGA)、后模压塑料引线框架封装体如方块平面封装体(QFP)和无引线QFP(QFN)封装体或微引线框架封装体(MLP)。这里的实施例还包括使用引线和/或芯片倒装连接的管芯朝上和管芯朝下配置。列出的封装体和配置示例是非限定性的，本技术可应用在使用模压塑料封装的所有封装体中，用于提供片上热点冷却。
实施例举例：将内插器连接到IC管芯上
图3A是带有至少一个热点306的示范性集成电路(IC)管芯302的结构示意图。为便于描述，图中仅展示了一个热点306，实际上IC管芯302也可以具有多个热点306。可根据管芯302的功率图和/或结合使用功耗和热模拟技术来预测一个或多个热点306的位置。应用不同，同一管芯302的功率图便不同，也就是说在组装和安装完毕后，管芯302上会有不同的模块启动和关闭。因此，即便是在同一管芯302上，这至少一个热点306也可能位于不同的位置。
在一个实施例中，管芯302具有引线接触焊盘(wirebond contactpad)304。在另一实施例中，管芯302用于倒装应用，没有引线接触焊盘304。在又一实施例中，管芯302同时配置有引线和倒装互连。接触焊盘304用于向和/或从安装在或内置于管芯302中的电路输入和/或输出信号。如图3A所示，用于与引线相连的接触焊盘304通常设置在管芯302表面上的四周区域，例如按行/环排列，以便与引线紧密接触。
图3B是带有内插器接触焊盘308的示范性管芯302的结构示意图。接触焊盘308的作用通常与管芯302的电信号无关(例如，用作电连接)，这一点与接触焊盘304不相同。然而，在一实施例中，一个或多个接触焊盘308可以与管芯302的电信号有关。此外，接触焊盘308通常位于管芯302上接触焊盘304所在位置的区域之外。例如，如图3B所示，接触焊盘308设置在管芯302表面的中心位置，也就是说设置在管芯302区域四周设置有引线接触焊盘304(用于引线键合)的位置以外的位置上。但是，在一个实施例中，一个或多个接触焊盘308也可临近设置在接触焊盘304的旁边。
内插器接触焊盘308可设置在任何热点306的内部或外部。在一个实施例中，接触焊盘308中的至少一部分是设置在热点306内部的。如本文所述，接触焊盘308设置在热点306内，用作管道的一端，该管道用于将热点306的热量传到至散热器。在一个实施例中，一个或多个接触焊盘308位于热点306的外部，用于(与热点306内部的接触焊盘308协作)为散热器提供稳定的底座。在一个实施例中，内插器接触焊盘308设置在针对应用而为管芯302专门设计的位置上。接触焊盘308的数量可以任意，这取决于管芯302和/或具体的应用。
图3C是根据本发明一实施例的内插器310的结构示意图，其中在与管芯302上设置内插器接触焊盘308的位置相对的位置上设置有节瘤312。在一个实施例中，节瘤312的形状可以是如图3C-3E中所示的球状、凸起或块状，或者其它不规则或规则形状。在另一实施例中，如图3F所示，节瘤312不管是球状、凸起还是块状，它都是设置在管芯302而非内插器310上的。
管芯302在热点306处产生的热量通过节瘤312提供的很短的导热路径传递给内插器310，其中节瘤312与热点306中的接触焊盘308相连。在图3G所示的实施例中，内插器310通过节瘤312在内插器接触焊盘308处与管芯302相连。在一个未示出的实施例中，内插器在内插器接触焊盘308处直接与管芯302相连，而未使用节瘤312。
图3H是带有一个以上热点306的管芯的结构示意图。内插器310通过节瘤312在内插器接触焊盘308处与管芯302相连。
内插器和节瘤实施例
图4A是内插器310的一个示范性实施例内插器400的结构示意图。图4A中展示的内插器400为平面矩形(例如四角处为圆角)形状。但是，内插器400的实施例还可为其它形状。内插器310可根据对应的IC管芯设计进行配置和/或根据具体应用进行配置。如此，内插器400的形状可以是非平面形和或非矩形。例如，内插器310可以是圆形、方形、矩形、帽形、凹或凸“汤碗”形，或其它规则或不规则、平面或非平面形。
在一个实施例中，内插器400具有导热性。在一个实施例中，内插器400还具有导电性。在一些实施例中，内插器400由金属如铜、铜合金(如同引线框架封装体的引线框架材料如C151、C194、EFTEC-64T、C7025等)、铝、其它金属合金和金属材料制成，或者由陶瓷、有机材料(双马来酰亚胺三嗪(bismaleimide triazine(BT))、阻燃类型4(FR4)等)制成，或者由传导性较差的材料如绝缘材料组成。内插器400还可由柔性胶带衬底组成，例如带有或没有一个或多个金属箔层的聚酰亚胺胶带衬底。现有的以及高密度加强衬底，包含BT和FR4的衬底也都可用于制造内插器400。
在图4A展示的实施例中，内插器400在选定位置处涂敷有表面覆层402。这个表面覆层402用于例如加强与节瘤312之间的连接，或者与IC管芯之间的直接连接。表面覆层402材料可以是多种材料中的一种或者多种，包括碳、金属、氧化物等。
图4B是内插器310另一示范性实施例450的结构示意图，其包括一个或多个开口404，塑封材料或底层填料可通过开口404注入，以填充内插器450和IC管芯之间的间隙。尽管在图4B中为狭槽和十字形状，但开口404可以是任何形状，包括圆形、狭槽型、矩形、正方形，以及其它规则和不规则形状。在一个实施例中，可以内插器450中或边缘上剪切一个切口以方便引线键合。在另一实施例中，还可在内插器450上设置模压锁片或凹槽。
在一个实施例中，内插器310通过节瘤312连接到IC管芯。节瘤312可以设置在IC管芯上，也可以设置在内插器310上。在图4B中展示的实施例中，节瘤312是以凸起的形式设置在内插器450上的。无论是设置在内插器310上，还是设置在IC管芯上，节瘤312都具有一定程度的导热性。在一个实施例中，节瘤312既可导热又可导电。
节瘤312的其它实施例可以是球状、截去的球状、凸起、块状、锥状、圆柱状、柱状或其它形状。节瘤312可以是焊料、金、铜、铝、合金、覆有焊料的圆柱、聚合材料、环氧材料、粘合材料或其它材料。节瘤312可包括基本材料(例如铝、铜、合金等)和沉积在基本材料部分或全部表面的辅助材料(例如焊料、环氧材料、金、合金等)。在一个实施例中，辅助材料可提高内插器310和IC管芯之间的机械连接性、热连接性和/或电连接性。
图5A和图5B是内插器310另一实施例内插器500的结构示意图，其包括以节瘤312为顶部的柱体502。图5A展示的是带有柱体502的内插器310的截面示意图，其中节瘤312位于柱体502的顶部。图5B展示的是一实施例的俯视图，除了以节瘤312为顶部的柱体502以外，该实施例上还设有开口404。图5A中的柱体502是中空的，其开口设置在内插器310的下表面上，其形状为平截头形状。柱体502可制成任何形状，如圆柱状、金字塔状、锥状和/或截去顶部的锥状或金字塔状。在另一实施例中，柱体502的顶部未设有节瘤312。在又一实施例中，柱体502部分或者全部覆盖有材料(例如焊料、环氧材料、粘合材料或其它材料)。覆盖的材料可以提高内插器310和IC管芯之间的机械连接性、热连接性和/或电连接性。
IC封装体实施例
下面的这一部分和相关的附图旨在描述本发明的多种实施例，但并非对本发明的范围进行限制。下面的这一部分将描述集成电路(IC)封装体的多个实施例，但本发明同样适用于其它现有或将来的IC器件封装体。
例如，图6A展示了一个示范性实施例，塑胶球栅阵列(PBGA)IC封装体600，该封装体包含IC管芯302，它通过节瘤312与内插器310相连。管芯302通过引线614和管芯粘合材料606连接到衬底608。塑封材料612将封装体600密封起来，其中包括管芯302、内插器310、引线614和整个或部分衬底608(例如上表面)。衬底608通过焊球610连接到印刷电路板(PWB)(未示出)。图6B展示了一个实施例，PGBAIC封装体650，其与图6A中的封装体600类似，区别仅在于在管芯302和内插器310之间添加了底层填料620。底层填料620可以是任何类型的底层填料，用于为内插器310与管芯310上的接触焊盘之间的连接提供保护。
图6C展示了引线框架式塑胶方形扁平封装体(PGFP)的一个示范性实施例封装体660，其IC管芯302通过节瘤312与内插器310相连。管芯302通过管芯粘合材料606粘合在管芯托盘622上。引线614将引线616与管芯302相连。塑封材料612将封装体660密封起来，其中包括管芯302和引线614。图6D展示了一个实施例，引线框架式封装体670，其类似于图6C中描述的封装体660，区别仅在于在管芯302和内插器310之间填充有底层填料620。
图6E展示了无引线方形扁平封装体(QFN)(也称为微型引线框架封装体(MLP)或微型引线框架(MLF)IC封装体)的一个示范性实施例的封装体680。在本实施例中，封装体680包含通过节瘤312连接到内插器310的IC管芯302。管芯302通过管芯粘合材料606粘合在管芯托盘622上。引线614将管芯302连接到封装体680的引线618上。图6F展示了类似的QFN/MLP/MLF IC封装体690，区别仅在于在管芯302和内插器310之间填充有底层填料620。
本发明的实施例还包括管芯朝下IC封装体。例如，图7A展示了示范性管芯朝下球栅阵列封装体(BGA)700，其包括通过节瘤312与内插器310相连的IC管芯302。管芯302与内插器310之间的区域可使用底层填料(未示出)填充。管芯302连接到散热器704上，引线614将管芯302与衬底706相连。焊球610将封装体700连接到印刷电路板(PWB)(未示出)上。塑封材料612将管芯302和引线614密封起来。
图7B展示了示范性管芯朝下引线框架式IC封装体750，其包括通过节瘤312连接到内插器310的管芯302。管芯粘合材料606将管芯302粘合在管芯托盘622上。引线将管芯302与引线616相连。底层填料(未示出)用于填充管芯302和内插器310之间的空间。
如本文所述，内插器310可包括柱体502。图8展示了带有柱体502的内插器310的BGA IC封装体。内插器310通过位于柱体502尖端的节瘤312连接到IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯302通过管芯粘合材料606粘合到衬底608上。引线614将管芯302与衬底608相连。封装体800密封在塑封材料612中，后者覆盖管芯302、引线614和整个或部分衬底608。焊球610用于将封装体800连接到印刷电路板(未示出)。尽管图8中展示的示例是BGA封装体800，但使用带有柱体502的内插器310的本发明实施例可包括IC封装体的所有类型，包括在本文其它附图中描述的那些类型。
本发明的实施例可使用多种类型的散热器。在包含散热器的实施例中，散热器可由金属如铜、铜合金(例如用于引线框架封装体中引线框架的材料如C151、C194、EFTEC-64T、C7025等)、铝和其它金属材料制成。散热器还可以是柔性胶带衬底类型，例如在聚酰亚胺胶片上层压一层或两层金属箔层而制成的聚酰亚胺胶带衬底。散热器还可由导热但不导电的材料如导热陶瓷材料制成。在一个实施例中，塑封材料将散热器完全密封。在其它实施例中，散热器中的一部分或者全部均未被密封。
例如，图9A中展示了一个示范性实施例，管芯朝上BGA IC封装体900，其包括通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到衬底608上，引线614将管芯302与衬底608相连。封装体900中还包括内嵌的散热器902，它可由塑封材料612完全密封，也可不完全密封。散热器902为帽形散热器，包括内腔906，和围绕散热器902外周设置的帽沿908。塑封材料612将封装体900密封起来，其中包括管芯302、引线614和整个或部分衬底608。焊球610用于将封装体900连接到印刷电路板(PWB)(未示出)上。图9B展示了BGA封装体950，其基本类似于封装体900，区别仅在于封装体950中使用的散热器904。散热器904为平板形。其它实施例还可使用其它类型的散热器设计，这一点对于本领域的技术人员来说应当是很明显的。
类似的，图9C中展示了封装体960，其为引线框架式QFP类型的IC封装体，并进一步包含通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到管芯托盘622上，引线614将管芯302与引线616相连。封装体960中还包括内嵌的散热器902。塑封材料612将封装体960密封起来，其中包括管芯302和引线614。内嵌散热器902可由塑封材料612完全密封，也可不完全密封。其它实施例还可使用其它类型的散热器设计，这一点对于本领域的技术人员来说应当是很明显的。
图9D展示了示范性的管芯朝下BGA封装体970，其中包含散热块906。散热块906可连接到PWB(未示出)。其它实施例还可包含多种其它类型的散热块906设计，这一点对于本领域的技术人员来说应当是很明显的。封装体970包括通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到散热器704上，引线614将管芯302与衬底706相连。塑封材料612将引线614和管芯302密封起来。焊球618用于连接到PWB(未示出)。
在一个实施例中，内插器通过非塑封材料连接到散热器。例如，图10A中展示了一个示范性实施例，管芯朝上的BGA封装体1000，其包含通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到衬底608上，引线614将管芯302与衬底608相连。封装体900还包括内嵌散热器902，它通过散热块1002连接到内插器310。其它实施例还可使用其它类型的散热器设计，这一点对于本领域的技术人员来说应当是很明显的。塑封材料将封装体1000密封起来，其中包括管芯302、引线614和整个或部分衬底608。散热器902和散热块1002可由塑封材料612完全密封，也可不完全密封。焊球618用于将封装体900连接到PWB(未示出)。
类似的，图10B中展示了引线框架式QFP IC封装体1010，其包含通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到管芯托盘622上。管芯302通过引线614与引线616相连。封装体1010中包含内嵌散热器902。其它实施例还可使用其它类型的散热器设计，这一点对于本领域的技术人员来说应当是很明显的。塑封材料612将封装体1010密封起来，其中包括管芯302、引线614。内嵌散热器902可由塑封材料612完全密封，也可不完全密封。
图10C和图10D展示了示范性实施例，IC封装体1040和1050，它们基本类似于图10A和图10B中展示的封装体1000和1010，区别仅在于使用焊球1004将散热器902连接到内插器310。
在另一示范性实施例中，图10E中展示了管芯朝下BGA封装体1060，其包括散热块1006和焊球1004。散热块1006安装在管芯302的表面上。当封装体1060安装在电路板上时，焊球1004用于将散热块1006连接到电路板如印刷线路板(PWB)(图10E中未示出)上。其它实施例还可使用其它配置的散热块1006，这一点对于本领域的技术人员来说应当是很明显的。封装体1060包括通过节瘤312与内插器310相连的IC管芯302。底层填料(未示出)用于填充管芯302和内插器310之间的空间。管芯粘合材料606将管芯302粘合到散热器704上，引线614将管芯302与衬底706相连。塑封材料612将引线614和管芯302密封起来。焊球618用于连接到PWB(未示出)。其它实施例还可使用其它的散热块1006实现，这一点对于本领域的技术人员来说应当是很明显的。例如，在图10F中展示的示例IC封装体1070中，散热块1006直接连接到电路板，因此无需使用焊球1004。
示范性实施例：组装方法
将管芯和内插器组装起来的示范性实施例在图11A-图11B中进行了介绍。图11A展示了流程图1100，图11B展示了流程图1150。正如在本文其它部分描述的那样，内插器和管芯通常为大规模IC封装体的组件。通过下面的讨论和本文中其它部分的教授方法，如何将管芯和内插器组装到本文其它部分描述的IC封装体实施例中，对于本领域的技术人员而言应当是很明显的。图11A-图11B中描述的步骤不必非要按照描述的顺序进行，这一点对于本领域的技术人员而言应当是很明显的。通过下面的讨论，其它结构和操作实施例对于本领域的技术人员而言应当是很明显的。
先来看图11A，流程图1100描述了安装过程，其中管芯上设有凸起的节瘤。在步骤1102，在管芯上设置至少一个凸起的节瘤。节瘤的示例见图3C-图3E中展示的节瘤312。在实施例中，如图3C-图3E所示，节瘤312可以是球状(例如焊球)、凸块状或块状，也可以是其它的形状。正如本文其它部分(例如图3F中)描述的那样，节瘤可以设置在位于管芯热点内部或外部的接触焊盘上。
在步骤1104，将内插器安放在管芯上，这样一来，管芯上的节瘤便可接触到内插器上的对应位置。例如，如结合图4A所描述的那样，在内插器表面上用于连接节瘤的位置可设有覆层。
在步骤1106，将内插器连接到管芯上。若节瘤是环氧材料、粘合材料或类似的材料，则将其固化即可。若节瘤是焊料、主层由焊料制成、由焊料覆盖或类似的成份，则会要对节瘤进行回流焊。其它节瘤成份也会要求对应的回流或固化方法来完成连接过程。
在可选的步骤1108，在管芯和内插器之间填充底层填料。例如，底层填料可以是图6B中的底层填料620。在一个实施例中，用于沉积底层填料的填充过程与现有芯片倒装技术中的对应过程相同。
现在来看图11B，流程图1150对组装过程进行了描述，其中内插器上设有凸起的节瘤。在步骤1152，在内插器上设置至少一个凸起的节瘤。节瘤的示例见图3C-图3E中展示的节瘤312。在实施例中，节瘤312可以是球状(例如焊球)、凸块状或块状，也可以是其它的形状。正如本文其它部分(例如图3F中)描述的那样，节瘤可以设置在位于管芯热点内部或外部的接触焊盘上。
在步骤1154，将内插器安放在管芯上，这样一来，内插器上的节瘤便可接触到管芯上对应的内插器接触焊盘。
在步骤1156，将内插器连接到管芯上。若节瘤是环氧材料、粘合材料或类似的材料，则将其固化即可。若节瘤是焊料、主层由焊料制成、由焊料覆盖或类似的成份，则会要对节瘤进行回流焊。其它节瘤成份也会要求对应的回流或固化方法来完成连接过程。
在步骤1158，在管芯和内插器之间填充底层填料。例如，底层填料可以是图6B中的底层填料620。在一个实施例中，用于沉积底层填料的填充过程与现有芯片倒装技术中的对应过程相同。
结论
尽管以上介绍了本发明的各种实施例，但是可以理解的是，以上仅仅是示例，并非对本发明的限制。本领域的技术人员显然知道，可以对本发明进行各种形式和细节上的改变而不脱离本发明的精神实质和范围。因此，本发明的保护范围不限于任何上述的实施例，而是由权利要求及其等效替换来定义。

Claims (10)

1.一种集成电路(IC)器件封装体，其特征在于，包括：
带有接触焊盘的IC管芯，所述接触焊盘设置在所述IC管芯的表面上且位于所述IC管芯的热点处；
导热内插器，包含第一和第二表面，所述内插器的第一表面在所述接触焊盘处与所述IC管芯相连。
2.根据权利要求1所述的封装体，其特征在于，还包括：
所述内插器第一表面和所述接触焊盘之间的热互连件。
3.根据权利要求1所述的封装体，其特征在于，还包括：
底层填料，其充分填充所述IC管芯表面和所述内插器第一表面之间的空间。
4.根据权利要求1所述的封装体，其特征在于，所述内插器第一表面设有至少一个柱体。
5.根据权利要求1所述的封装体，其特征在于，所述内插器具有导电性。
6.根据权利要求1所述的封装体，其特征在于，所述内插器第一表面与所述接触焊盘电连接。
7.根据权利要求1所述的封装体，其特征在于，还包括：
至少一个导热节瘤，所述内插器第一表面通过所述至少一个导热节瘤连接到所述IC管芯。
8.一种组装集成电路(IC)封装体的方法，其特征在于，包括：
通过至少一个节瘤将内插器的第一表面与IC管芯表面的接触焊盘相连接。
9.根据权利要求8所述的方法，其特征在于，还包括：
将所述节瘤以凸起的形式设置在所述内插器的第一表面上，所述节瘤在所述第一表面上的位置对应所述IC管芯表面所述接触焊盘的位置。
10.根据权利要求8所述的方法，其特征在于，还包括：
将所述节瘤以凸起的形式设置在所述IC管芯第一表面的所述接触焊盘上。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290393A (zh) * 2010-06-18 2011-12-21 星科金朋有限公司 具有导线架的集成电路封装系统及其制造方法
CN102822965A (zh) * 2010-03-01 2012-12-12 高通股份有限公司 具有内嵌式裸片的集成电路封装中的热通孔
CN109116140A (zh) * 2018-07-16 2019-01-01 中国航空综合技术研究所 一种用于pbga封装器件的测试方法
US10607913B2 (en) 2015-04-30 2020-03-31 Huawei Technologies Co., Ltd. Integrated circuit die and manufacture method thereof

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271479B2 (en) * 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
US7566591B2 (en) * 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7557438B2 (en) * 2006-04-27 2009-07-07 Intel Corporation Cooling mechanism for stacked die package, and method of manufacturing stacked die package containing same
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US20070273023A1 (en) * 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US9013035B2 (en) * 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages
US8169067B2 (en) * 2006-10-20 2012-05-01 Broadcom Corporation Low profile ball grid array (BGA) package with exposed die and method of making same
US8183687B2 (en) * 2007-02-16 2012-05-22 Broadcom Corporation Interposer for die stacking in semiconductor packages and the method of making the same
US7926173B2 (en) * 2007-07-05 2011-04-19 Occam Portfolio Llc Method of making a circuit assembly
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
TW200900961A (en) * 2007-06-26 2009-01-01 Inventec Corp Method for simulating thermal resistance value of thermal test die
US8318541B2 (en) * 2010-08-10 2012-11-27 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect in FO-WLCSP using leadframe disposed between semiconductor die
FR2977975A1 (fr) * 2011-07-13 2013-01-18 St Microelectronics Grenoble 2 Boitier electronique a via thermique et procede de fabrication
FR2982080B1 (fr) 2011-10-26 2013-11-22 St Microelectronics Rousset Procede de communication sans fil entre deux dispositifs, notamment au sein d'un meme circuit integre, et systeme correspondant
DE102011088256A1 (de) * 2011-12-12 2013-06-13 Zf Friedrichshafen Ag Multilayer-Leiterplatte sowie Anordnung mit einer solchen
US8867231B2 (en) * 2012-01-13 2014-10-21 Tyco Electronics Corporation Electronic module packages and assemblies for electrical systems
KR20130097481A (ko) * 2012-02-24 2013-09-03 삼성전자주식회사 인쇄회로기판(ｐｃｂ) 및 그 ｐｃｂ를 포함한 메모리 모듈
US9252068B2 (en) * 2012-05-24 2016-02-02 Mediatek Inc. Semiconductor package
US9041212B2 (en) 2013-03-06 2015-05-26 Qualcomm Incorporated Thermal design and electrical routing for multiple stacked packages using through via insert (TVI)
CN104737635B (zh) 2013-06-26 2017-04-26 莫列斯公司 适于电子模块的热插件
DE102014211524B4 (de) * 2014-06-17 2022-10-20 Robert Bosch Gmbh Elektronikmodul mit einer Vorrichtung zur Wärmeabführung von durch eine in einem Kunststoffgehäuse angeordnete Halbleitereinrichtung erzeugter Wärme und Verfahren zur Herstellung eines Elektronikmoduls
JP2016029681A (ja) * 2014-07-25 2016-03-03 イビデン株式会社 多層配線板及びその製造方法
JP6473595B2 (ja) 2014-10-10 2019-02-20 イビデン株式会社 多層配線板及びその製造方法
JP6324539B2 (ja) * 2014-12-26 2018-05-16 三菱電機株式会社 半導体モジュール
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
JP6361821B2 (ja) * 2015-04-27 2018-07-25 富士電機株式会社 半導体装置
US20190206839A1 (en) * 2017-12-29 2019-07-04 Intel Corporation Electronic device package
DE102019202718B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
DE102019202716B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit coplanarer topologie für hochfrequenzsignale und verfahren zum herstellen eines derartigen flex-folien-packages
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
DE102019202717A1 (de) * 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit erweiterter topologie
DE102021214757A1 (de) * 2021-12-21 2023-06-22 Magna powertrain gmbh & co kg Optimiertes Verfahren zur Anbindung von Leistungsmodulen, sowie Bauteil
WO2024000475A1 (en) * 2022-06-30 2024-01-04 Innoscience (suzhou) Semiconductor Co., Ltd. Semiconductor packaged device and method for manufacturing thereof

Family Cites Families (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468681A (en) * 1989-08-28 1995-11-21 Lsi Logic Corporation Process for interconnecting conductive substrates using an interposer having conductive plastic filled vias
US5247426A (en) 1992-06-12 1993-09-21 Digital Equipment Corporation Semiconductor heat removal apparatus with non-uniform conductance
US6466446B1 (en) * 1994-07-01 2002-10-15 Saint Gobain/Norton Industrial Ceramics Corporation Integrated circuit package with diamond heat sink
US5856911A (en) 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US5786635A (en) 1996-12-16 1998-07-28 International Business Machines Corporation Electronic package with compressible heatsink structure
US6395582B1 (en) 1997-07-14 2002-05-28 Signetics Methods for forming ground vias in semiconductor packages
US6337445B1 (en) 1998-03-16 2002-01-08 Texas Instruments Incorporated Composite connection structure and method of manufacturing
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
TW418511B (en) 1998-10-12 2001-01-11 Siliconware Precision Industries Co Ltd Packaged device of exposed heat sink
JP2000138262A (ja) 1998-10-31 2000-05-16 Anam Semiconductor Inc チップスケ―ル半導体パッケ―ジ及びその製造方法
US6313521B1 (en) 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
US6218730B1 (en) 1999-01-06 2001-04-17 International Business Machines Corporation Apparatus for controlling thermal interface gap distance
US6265771B1 (en) 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
US6180426B1 (en) 1999-03-01 2001-01-30 Mou-Shiung Lin High performance sub-system design and assembly
TW579555B (en) * 2000-03-13 2004-03-11 Ibm Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus
TW456013B (en) 2000-07-04 2001-09-21 Advanced Semiconductor Eng Heat spreader substrate structure and the process thereof
AU2001276898A1 (en) * 2000-07-11 2002-01-21 Binie V. Lipps Synthetic peptide for neurological disorders
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6541849B1 (en) * 2000-08-25 2003-04-01 Micron Technology, Inc. Memory device power distribution
JP4529262B2 (ja) 2000-09-14 2010-08-25 ソニー株式会社 高周波モジュール装置及びその製造方法
US6882042B2 (en) 2000-12-01 2005-04-19 Broadcom Corporation Thermally and electrically enhanced ball grid array packaging
US7132744B2 (en) 2000-12-22 2006-11-07 Broadcom Corporation Enhanced die-up ball grid array packages and method for making the same
US7161239B2 (en) 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US6906414B2 (en) 2000-12-22 2005-06-14 Broadcom Corporation Ball grid array package with patterned stiffener layer
US20020079572A1 (en) 2000-12-22 2002-06-27 Khan Reza-Ur Rahman Enhanced die-up ball grid array and method for making the same
US6853070B2 (en) 2001-02-15 2005-02-08 Broadcom Corporation Die-down ball grid array package with die-attached heat spreader and method for making the same
US7259448B2 (en) 2001-05-07 2007-08-21 Broadcom Corporation Die-up ball grid array package with a heat spreader and method for making the same
US6528892B2 (en) 2001-06-05 2003-03-04 International Business Machines Corporation Land grid array stiffener use with flexible chip carriers
US6573592B2 (en) * 2001-08-21 2003-06-03 Micron Technology, Inc. Semiconductor die packages with standard ball grid array footprint and method for assembling the same
US6888235B2 (en) * 2001-09-26 2005-05-03 Molex Incorporated Power delivery system for integrated circuits utilizing discrete capacitors
TW523887B (en) 2001-11-15 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor packaged device and its manufacturing method
US6879039B2 (en) 2001-12-18 2005-04-12 Broadcom Corporation Ball grid array package substrates and method of making the same
TW529112B (en) 2002-01-07 2003-04-21 Advanced Semiconductor Eng Flip-chip packaging having heat sink member and the manufacturing process thereof
US6712621B2 (en) * 2002-01-23 2004-03-30 High Connection Density, Inc. Thermally enhanced interposer and method
JP3908157B2 (ja) 2002-01-24 2007-04-25 Ｎｅｃエレクトロニクス株式会社 フリップチップ型半導体装置の製造方法
WO2003065451A1 (en) * 2002-01-31 2003-08-07 Thomson Licensing S.A. Flip chip die bond pads, die bond pad placement and routing optimization
US7245500B2 (en) 2002-02-01 2007-07-17 Broadcom Corporation Ball grid array package with stepped stiffener layer
US6825108B2 (en) 2002-02-01 2004-11-30 Broadcom Corporation Ball grid array package fabrication with IC die support structures
US6861750B2 (en) 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
US7550845B2 (en) 2002-02-01 2009-06-23 Broadcom Corporation Ball grid array package with separated stiffener layer
US6606251B1 (en) * 2002-02-07 2003-08-12 Cooligy Inc. Power conditioning module
US6876553B2 (en) 2002-03-21 2005-04-05 Broadcom Corporation Enhanced die-up ball grid array package with two substrates
US7196415B2 (en) 2002-03-22 2007-03-27 Broadcom Corporation Low voltage drop and high thermal performance ball grid array package
FR2837982B1 (fr) 2002-03-26 2005-02-18 Thales Sa Module de circuits integres et procede de fabrication correspondant
US20030202332A1 (en) 2002-04-29 2003-10-30 Tommi Reinikainen Second level packaging interconnection method with improved thermal and reliability performance
TW582100B (en) 2002-05-30 2004-04-01 Fujitsu Ltd Semiconductor device having a heat spreader exposed from a seal resin
US6848912B2 (en) 2002-12-12 2005-02-01 Broadcom Corporation Via providing multiple electrically conductive paths through a circuit board
DE10260185B4 (de) * 2002-12-20 2007-04-12 Infineon Technologies Ag Halbleiterspeicher mit vertikalen Charge-trapping-Speicherzellen und Verfahren zu seiner Herstellung
US20050093135A1 (en) * 2003-10-31 2005-05-05 Wei-Chi Liu Thermal dissipating element of a chip
TWI222729B (en) * 2003-11-18 2004-10-21 Advanced Semiconductor Eng Semiconductor device package with a heat spreader
US7245022B2 (en) * 2003-11-25 2007-07-17 International Business Machines Corporation Semiconductor module with improved interposer structure and method for forming the same
US20050127500A1 (en) 2003-12-10 2005-06-16 International Business Machines Corporation Local reduction of compliant thermally conductive material layer thickness on chips
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US20050191786A1 (en) * 2003-12-31 2005-09-01 Microfabrica Inc. Integrated circuit packaging using electrochemically fabricated structures
JP4467318B2 (ja) * 2004-01-28 2010-05-26 Ｎｅｃエレクトロニクス株式会社 半導体装置、マルチチップ半導体装置用チップのアライメント方法およびマルチチップ半導体装置用チップの製造方法
KR100632459B1 (ko) 2004-01-28 2006-10-09 삼성전자주식회사 열방출형 반도체 패키지 및 그 제조방법
JP4587676B2 (ja) * 2004-01-29 2010-11-24 ルネサスエレクトロニクス株式会社 チップ積層構成の３次元半導体装置
US7119432B2 (en) 2004-04-07 2006-10-10 Lsi Logic Corporation Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
US20070278666A1 (en) 2004-04-13 2007-12-06 Jean-Charles Garcia Method for Production of Electronic and Optoelectronic Circuits
KR100604848B1 (ko) 2004-04-30 2006-07-31 삼성전자주식회사 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법
US7199466B2 (en) * 2004-05-03 2007-04-03 Intel Corporation Package design using thermal linkage from die to printed circuit board
US20050257821A1 (en) * 2004-05-19 2005-11-24 Shriram Ramanathan Thermoelectric nano-wire devices
US7482686B2 (en) 2004-06-21 2009-01-27 Braodcom Corporation Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same
US7411281B2 (en) * 2004-06-21 2008-08-12 Broadcom Corporation Integrated circuit device package having both wire bond and flip-chip interconnections and method of making the same
US7432586B2 (en) 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
US20060060952A1 (en) * 2004-09-22 2006-03-23 Tsorng-Dih Yuan Heat spreader for non-uniform power dissipation
US7786591B2 (en) 2004-09-29 2010-08-31 Broadcom Corporation Die down ball grid array package
US7290596B2 (en) * 2004-10-20 2007-11-06 University Of Maryland Thermal management of systems having localized regions of elevated heat flux
US20060091542A1 (en) 2004-11-03 2006-05-04 Broadcom Corporation Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same
US7271479B2 (en) 2004-11-03 2007-09-18 Broadcom Corporation Flip chip package including a non-planar heat spreader and method of making the same
US7355289B2 (en) 2005-07-29 2008-04-08 Freescale Semiconductor, Inc. Packaged integrated circuit with enhanced thermal dissipation
US7566591B2 (en) 2005-08-22 2009-07-28 Broadcom Corporation Method and system for secure heat sink attachment on semiconductor devices with macroscopic uneven surface features
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7245495B2 (en) * 2005-12-21 2007-07-17 Sun Microsystems, Inc. Feedback controlled magneto-hydrodynamic heat sink
US20070200210A1 (en) 2006-02-28 2007-08-30 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in integrated circuit (IC) packages
US7714453B2 (en) 2006-05-12 2010-05-11 Broadcom Corporation Interconnect structure and formation for package stacking of molded plastic area array package
US8183680B2 (en) 2006-05-16 2012-05-22 Broadcom Corporation No-lead IC packages having integrated heat spreader for electromagnetic interference (EMI) shielding and thermal enhancement
US20070273023A1 (en) 2006-05-26 2007-11-29 Broadcom Corporation Integrated circuit package having exposed thermally conducting body
US7808087B2 (en) 2006-06-01 2010-10-05 Broadcom Corporation Leadframe IC packages having top and bottom integrated heat spreaders
US8581381B2 (en) 2006-06-20 2013-11-12 Broadcom Corporation Integrated circuit (IC) package stacking and IC packages formed by same
US9013035B2 (en) 2006-06-20 2015-04-21 Broadcom Corporation Thermal improvement for hotspots on dies in integrated circuit packages

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102822965A (zh) * 2010-03-01 2012-12-12 高通股份有限公司 具有内嵌式裸片的集成电路封装中的热通孔
CN102290393A (zh) * 2010-06-18 2011-12-21 星科金朋有限公司 具有导线架的集成电路封装系统及其制造方法
US10607913B2 (en) 2015-04-30 2020-03-31 Huawei Technologies Co., Ltd. Integrated circuit die and manufacture method thereof
CN109116140A (zh) * 2018-07-16 2019-01-01 中国航空综合技术研究所 一种用于pbga封装器件的测试方法

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