CN101127240B - 降低非易失性存储器存储元件间耦合效应的方法 - Google Patents
降低非易失性存储器存储元件间耦合效应的方法 Download PDFInfo
- Publication number
- CN101127240B CN101127240B CN2007101537555A CN200710153755A CN101127240B CN 101127240 B CN101127240 B CN 101127240B CN 2007101537555 A CN2007101537555 A CN 2007101537555A CN 200710153755 A CN200710153755 A CN 200710153755A CN 101127240 B CN101127240 B CN 101127240B
- Authority
- CN
- China
- Prior art keywords
- group
- data
- memory element
- memory
- programming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000015654 memory Effects 0.000 title claims abstract description 213
- 238000003860 storage Methods 0.000 title claims abstract description 28
- 230000008878 coupling Effects 0.000 title claims description 9
- 238000010168 coupling process Methods 0.000 title claims description 9
- 238000005859 coupling reaction Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title description 57
- 230000001603 reducing effect Effects 0.000 title description 3
- 238000009826 distribution Methods 0.000 claims abstract description 88
- 238000007667 floating Methods 0.000 claims abstract description 38
- 230000008672 reprogramming Effects 0.000 claims description 16
- 230000008859 change Effects 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 210000000352 storage cell Anatomy 0.000 claims 8
- 210000004027 cell Anatomy 0.000 claims 7
- 230000005684 electric field Effects 0.000 claims 6
- 230000000694 effects Effects 0.000 abstract description 37
- 238000000926 separation method Methods 0.000 abstract 1
- 238000012795 verification Methods 0.000 description 78
- 238000005516 engineering process Methods 0.000 description 23
- 230000008569 process Effects 0.000 description 20
- 230000000875 corresponding effect Effects 0.000 description 19
- 230000006835 compression Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 238000007906 compression Methods 0.000 description 7
- 238000013500 data storage Methods 0.000 description 6
- 238000012217 deletion Methods 0.000 description 4
- 230000037430 deletion Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 241001269238 Data Species 0.000 description 3
- 238000003491 array Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000002596 correlated effect Effects 0.000 description 2
- 230000001808 coupling effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000007115 recruitment Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
- 230000003245 working effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
Abstract
一种带有一列存储器单元的非易失性存储器系统，每一个存储器单元都有至少一个存储元件，该系统在每一个存储器元件多个存储等级下被操作。一种快擦写电可擦可编程只读存储器(EEPROM)是一个实例，其中的存储元件是电浮栅。该存储器减小了由于相邻浮栅之间耦合的电荷的影响，这是通过在相邻单元被编程之后对某些单元进行第二次编程来实现的。第二次编程步骤还在至少部分编程状态中压缩电荷等级分布。这样就提高了状态之间的分隔和/或允许在给定存储窗口中包括更多的状态。本发明所描述的具体实现形式是一种NAND型的快擦写EEPROM。
Description
本申请是申请号为02143467.0、申请日为2002年6月27日、发明名称为“降低非易失性存储器存储元件间耦合效应的方法”的专利申请的分案申请。
技术领域
本发明总体上涉及一种非易失性存储器以及其操作，更具体的说，涉及一种用来降低存储在一个存储器存储元件上的数据对从其它存储元件中所读取的数据的影响的技术。
背景技术
本发明的原则可以应用于不同类型的非易失性存储器，包括那些现有的以及将来利用新的技术被新开发的。然而，这里本发明的具体应用是根据电可擦可编程只读存储器(EEPROM)来进行说明的，其中存储元件是浮栅(FG)(floating gate)。
相邻的FG之间耦合的场效应在Jian Chen和Yupin Fong的美国专利第5867429中被描述，这里该发明被全文引用作为参考。作为集成电路制造技术改进的结果，当存储单元阵列的尺寸被减小的时候，耦合程度必然会增大。问题明显地产生于当两组相邻的在不同时间被编程的存储单元时候。一组单元被编程增加对应于一组数据的其FG的电荷(charge)等级。在第二组单元利用第二组数据编程之后，从第一组单元中的FG读出的电荷等级(level)往往由于对与第一组相耦合的第二组FG所产生的负载影响而变得与所编程的结果不符。这被称之为Yupin效应。前面所提到的第5867429号专利建议要么将两组FG从物理上进行绝缘隔断，要么再从第一组FG中读取数值的时候将第二组FG的电荷影响考虑在内。
这种效应出现在不同类型的快擦写EEPROM单元阵列中。一种NOR阵列的一个设计将其存储单元连接在相邻的位(行)线之间，将控制栅连接到字(列)线上。每一个单元都包括一个带有或者是不带有与之串联的选择晶体管的浮栅晶体管，或者是由一个单独的选择晶体管所分隔开的两个浮栅晶体管。此种阵列及其在存储系统中应用的实施例在下面所列的这些SanDisk公司的专利以及未获授权的申请中都提到了，这些相关文件在这里也被作为参考：专利第5095344，5172338，5602987，5663901，5430859，5657332，5712180，5890192，以及6151248号，还有于2000年02月17日提交的序列号为09/505555，以及于2000年09月22日提交的序列号为09/667334号专利申请。
一个NAND阵列的一种设计是带有一系列存储单元，例如8，16或者是32个通过位于任意一端的选择晶体管存储单元串联连接于一位线与一个参考电势之间。字线在不同的串联阵列中连接到控制栅上。这种排列的相关实例以及其操作都在下面这些Toshiba的美国专利或者是未获授权的申请中被提到，这些文件在这里也都全文被参考：第5570315，5774397和6046935号以及序列号第09/667610号。
在当今的商品中，通过在二进制下进行操作来向每一个浮栅内存入一个单独比特的数据是最普遍的做法，浮栅晶体管的阈值电平的两个范围被设定为存储等级。一个浮栅晶体管的阈值电平对应于存储在其浮栅上的电荷等级。除了减小存储器阵列的尺寸之外，趋势是通过在每一个浮栅晶体管上存储超过一比特的数据来提高这样的存储器阵列上所存储数据的密度。这是通过为每一个浮栅晶体管定义两个以上的阈值电平作为存储状态来实现的，四个这样的状态(每一个浮栅2比特数据)被包含在现有的商品中。更多的存储状态，诸如每个存储元件16个状态这样的情况也被考虑。每一个浮栅晶体管都具有某一个阈值电平电压的总范围(限幅器)，在这一范围内其可以被实际操作，并且该范围被分成多个定义的状态和位于状态间的余量，以便他们能被彼此清晰地辨认出来。
这种类型的非易失性存储器的通常操作是在对其重编程之前首先擦除存储单元块。在块内的单元接下来被分别在擦除后编程成为由要存储的输入数据表示的状态。编程通常包括在编程电压脉冲的同时交替向大量的存储器单元提出请求并且分别读出其状态以便确定各个单元是否分别达到了其预定的等级。对于那些被证实已经达到其预定阈值电平的单元编程就会停止，而同时对于其它被编程单元的编程仍将同时进行，一直到所有那些单元都被编程为止。当单位存储元件的存储状态数量被提高的时候，执行编程的时间就会变得更长因为每一个状态的更小的电压范围需要编程的更高精度。这将会给存储系统带来显著的负面影响。
由多状态操作导致的所定义浮栅存储等级的更窄范围提高了第一组存储元件加载在稍晚编程的相邻第二组存储元件上的电荷的敏感度等级。例如当第一组被读取的时候，第二组上的电荷在读取第一组状态的时候会导致错误。从相邻的存储元件耦合的场能够大大影响所读出的状态，至少是在一组所存储数据的一部分比特上会导致错误。如果错误比特的数量保持在误差校正码(ECC)的能力范围以内的话，这些错误还能够被修正，但是如果错误的数量超过了那个限度的话，就必须使用其他的结构和/或操作技术。在前面所提到的美国专利第5867429号中所披露的技术就适用于多阵列的情况，但是希望提供另外的技术以补偿相邻的浮栅之间耦合的场的工作效应。
发明内容
这样以来，根据本发明的一个基本方面，在第二组相邻的存储元件被编程之后，第一组存储元件重新编程到其希望状态。由于周期性读取单元的状态是编程过程中的一部分，用于确定何时停止，所以再编程会在第一组存储元件中加入补偿由于后来编程的相邻存储元件间耦合的场效应的所必要的电荷。一种常规的编程操作的交替脉冲和读取顺序可被用来对第一组存储单元进行重新编程，这是发生在第二组相邻的已编程存储元件影响出现的时候。尽管仍然会受到相邻单元的电荷影响，但是后来对于第一组存储元件的读取，会由于相邻单元电荷的影响已经由于重新编程被考虑在内而变得更加精确。为了避免必须保留一个足够大以保持在第一通道被编程的数据的数据缓冲器，以在第二编程通道使用，被第一通道所存储的数据可以从带有调整的读取余量的存储器中读出，并且这些数据在第二通道被重新编程。
根据本发明的第二个基本方面，被编程到相同状态的存储元件的编程等级分布被通过将在分布状态一侧的一些存储元件重新编程成到分布状态另一侧而被压缩(compact)。处在给定状态下的存储元件被读取，同时那些编程等级低于分布状态的预定阈值的存储元件被给予进一步的编程，以便将其等级提升到预定阈值以上。这样的方式起到了减少每一个存储器状态所需要的编程窗口的效果，从而允许了附加状态被包括在内和/或附加空间提供于状态之间。这样的压缩可以按照前面段落提到的方式独立执行，但更佳地也可以被作为再编程步骤的一部分。实际上，第二编程通道应该在相同组单元的首次编程后马上出现，以便于将编程等级分布状态缩小到一个范围，该范围是考虑了在相邻单元被编程之后所发生的这些分布状态的明显扩大。编程脉冲电压等级的步长增加量可以被设定为高于第一编程通道的通常等级，以便于快速在一个较宽的分布状态内将一组单元编程到其初始等级，并且接下来通常的小增量电压在第二通道提高编程脉冲以便压缩那些分布的扩展。这些技术通过那些编程存储单元的窄电压阈值分布状态可以被快速达到性能的提高。
根据本发明的另外一个方面，根据一个现有多状态编程技术对相邻存储器单元进行编程的顺序可以以这样方式实现，即将这样的相邻单元之间交叉耦合的Yupin效应最小化。根据现有编程技术，在一行或列中第一组交替相邻单元在第一编程步骤中，被部分编程成为第一数据比特等级，剩余的第二组交替单元接下来按照类似的方式被部分编程成为那些单元的第一数据比特等级，接下来是用每一个单元第二数据比特完成第一组编程，最终，第二组的编程用其第二比特完成。但是为了使在这些单元中的存储元件之间的Yupin效应最小，根据本发明的第三个方面，各比特都被以独立的步骤被编程到第一组单元，接下来，按独立的步骤用其两数据比特将第二组单元编程。该技术尤其适用于，但不仅限于，在对NAND存储器进行编程的时候使用。该技术可以独立使用，也可以根据上面总结的本发明的第一和/或第二基本方面一起使用，以便在不同等级下，抵消相邻存储元件之间耦合的Yupin效应。
本发明的其他方面，特性以及优点都在下面示例性实施例部分加以说明，其中是参考如下这些附图进行描述的。
附图说明
图1是具备本发明的各方面特性的非易失性存储器的方框图；
图2是当图1中的存储器阵列是NAND型时，图解说明现有电路以及组织结构；
图3是位于半导体基片上的NAND型存储器阵列沿列方向的剖面图；
图4是图3中的存储器阵列沿着4-4区域的剖面图；
图5是图3中的存储器阵列沿着5-5区域的剖面图；
图6是图2-5中的NAND存储器阵列的示例操作电压表I；
图7描述了图2-5中的NAND存储器阵列的另外一个特征；
图8显示了在四状态操作下，图2-5中的NAND存储器阵列阈值电压的示例性现有分布状态；
图9A显示了一个编程电压的波形信号；
图9B显示了响应用图9A所示的电压脉冲编程图2-5中的存储器单元阵列的现有电压阈值响应；
图10A以及10B是电压阈值等级分布状态，是用来举例说明对图2-5所示的存储器单元阵列进行编程的现有技术；
图11显示了在使用现有技术编程时Yupin对图2-5所示的存储单元阵列，在阈值分布效应；
图12显示了在使用根据本发明的第一种技术编程时Yupin对图2-5所示的存储器单元阵列阈值分布状态的效应；
图13显示了根据如图12所示结果的第一种技术对图2-5所示的存储器单元阵列进行编程的步骤；
图14A显示了根据图13所示的编程方法的编程电压的波形信号；
图14B显示了根据图13所示的编程方法，对图14A的编程脉冲，图2-5所示的存储器单元阵列的电压阈值等级响应；
图15A显示了根据图13所示的编程方法的编程电压的另一波形信号；
图15B显示了根据图13所示的编程方法，对图15A中的一组交替编程脉冲，图2-5所示的存储器阵列的电压阈值等级响应；
图16显示了在使用根据本发明的第二种技术编程时，Yuin对图2-5所示的存储单元阵列阈值分布状态的效应；
图17显示了根据如图16所示结果的第一种技术对图2-5所示的存储单元阵列进行编程的步骤；
图18显示了在使用根据本发明的第二种技术的一种变化编程时，对图2-5所示的存储单元阵列阈值分布状态的Yupin效应；
图19显示了根据如图18所示结果的第一种技术对图2-5所示的存储单元阵列进行编程的步骤；
图20显示了在使用根据本发明的第三种技术编程时，对图2-5所示的存储单元阵列进行阈值分布状态的Yupin效应；
图21是对图2-5所示的存储器阵列进行编程方法的第一个示例性实施例的第一部分流程图；
图22是对图2-5所示的存储器阵列进行编程方法的第一个示例性实施例的第二部分流程图；
图23是对图2-5所示的存储器阵列进行编程方法的第二个示例性实施例的第一部分流程图；
图24是对图2-5所示的存储器阵列进行编程方法的第二个示例性实施例的第二部分流程图；
图25是与图21组合时，对图2-5所示的存储器阵列进行编程方法的第三个示例性实施例的第一部分流程图；
图26是与图22组合时，对图2-5所示的存储器阵列进行编程方法的第三个示例性实施例的第二部分流程图；
图27是与图23组合时，对图2-5所示的存储器阵列进行编程方法的第四个示例性实施例的第一部分流程图；
图28是与图24组合时，对图2-5所示的存储器阵列进行编程方法的第四个示例性实施例的第二部分流程图；
图29说明了一种使用第三以及第四实施例的编程顺序；
图30显示了从图2-5中所示的存储器阵列中读出数据方法的第一部分；以及
图31显示了从图2-5中所示的存储器阵列中读出数据方法的第二部分。
具体实施方式
非易失性存储器系统示例
参照图1-7，为了提供具体的实例，说明了一种能够实现本发明的不同方面的具体的非易失性存储器。图1是一种闪存系统的方框图。包括多个成矩阵排列的存储器单元的存储器单元阵列1由列控制电路2、行控制电路3，c源控制电路4以及c-p-阱控制电路5来控制。列控制电路2被连接到存储器单元阵列1的位线(BL)上，以便读取存储在存储器单元(M)上的数据，在编程操作中确定存储器单元(M)的状态，以及控制位线(BL)的电势等级来促进编程或者是抑制编程。行控制电路3连接到字线(WL)上，用来选择其中的一个字线(WL)，提供读取电压，提供一个编程电压，该电压是与由列控制电路2所控制的位线电势等级相结合的，以及在存储器单元(M)形成的p区域(在图3中标为“c-p-阱”)的电压上外加一个擦除电压。c源控制电路4控制与存储器单元(M)相连接的普通源线(在图2中标为“c-源”)。c-p-阱控制电路5控制c-p-阱电压。
存储在存储器单元(M)内的数据由列控制电路2所读出，并且通过一个I/O线以及一个数据输入/输出缓冲器6输出到外部I/O线。要存储到存储器单元上的编程数据通过一个外部I/O线输入到输入/输出缓冲器6上，并且被传送到列控制电路2。外部I/O线连接到一个控制器20上。
控制闪存设备的命令数据被输入到一个命令接口，该接口是连接到与控制器20相连的外部控制线上的。命令数据告之闪存什么操作被请求。输入命令被传送到控制列控制电路2，行控制电路3，c源控制电路4，c-p-阱控制电路5以及数据输入/输出缓冲器6的状态机8上。状态机8可以输出闪存的状态数据，例如准备/忙或者是通过/失败。
控制器20被连接到或者是可连接到主系统上，该主系统可以是个人电脑，数码照相机，个人数码助理。是主系统发出指令，例如向/从存储器阵列1存储或者是读取数据，并且分别提供或者是接收这样的数据。控制器将这样的命令转换成为可以通过命令电路7来解释和执行的命令信号。控制器通常还包括用于从存储器阵列写入或读出的用户数据的缓冲存储器。典型的存储器系统包括一个集成电路片21，该片21包括控制器20，以及一个或更多集成电路片22，其中的每一个都包括一个存储器阵列以及相关的控制，输入/输出以及状态机电路。当然发展趋势是将存储器阵列以及系统控制电路都集成到一个或多个集成电路片上。存储器系统可以被嵌入到主系统中作为其一部分，也可以被包含在一个可以插入到主系统相匹配的插口内并可以移走的存储器卡上。这样的卡可以包括整个存储器系统，或者是控制器和存储器阵列，其他外围的相关电路可以在分开的卡上。
参照图2，存储器阵列1的一个示例性结构被说明。一种NAND快擦写EEPROM被作为示例说明。在一个具体示例中，存储器单元(M)被分成1024个块。存储在每一个块中的数据被同时擦除。块就成为同时可擦除的单元的最小单位。在本例的每一个块中，有被分成偶数列和奇数列的8512列。位线也被分成偶位线(BLw)和奇位线(BLo)。在每一个栅电极连接到字线(WL0到WL3)上的四个串联存储器单元形成一个NAND单元。NAND单元的一个终端通过连接到一个第一选择门线(SGD)上的第一选择晶体管(S)被连接到相应的位线(BL)上，另外一个终端通过一个栅电极连接到一个第二选择门线(SGS)上的第二选择晶体管(S)被连接到c源上。尽管为了简单只是在每一个单元中显示出了四个浮栅晶体管，然而实际当中通常会使用更多数量的晶体管，例如8，16或者甚至是32个。
在一个用户数据读取以及编程操作中，在本例中，有4256个单元(M)被同时选中。被选中的单元(M)带有相同的字线(WL)，例如WL2，以及相同类型的位线(BL)，例如偶数位线BLe0到BLe4255。因此，532比特的数据可以同时被读取或编程。这同时读出或编程的532B逻辑上成为一“页”。因此，一个块可以存储至少八页。当每一个存储器单元(M)存储两比特数据时，即多级单元的时候，一个块可以在每单元存储两比特的情况下存储16页。在本实施例中，每一个存储器单元的存储元件，这里是每一个存储器单元的浮动门都存储两比特用户数据。
图3显示了图2中示意性显示的NAND单元沿位线(BL)方向的剖面图。在一个P型半导体衬底9的表面，形成有一个p型区域c-p阱11，c-p阱由一个n型区域10所密封，以便使c-p阱与p型衬底相互电绝缘。n型区域10通过一个第一连接孔(CB)以及一个n型扩散层12连接到由第一金属M0制成的c-p阱线。p型区域c-p阱11通过一个第一连接孔(CB)以及一个p型扩散层13连接到c-p阱线。c-p阱线连接到c-p阱控制电路5上(图1)。
每一个存储器单元都带有一个存储一定数量的与存储在单元内的数据相对应的电荷的浮栅(FG)，字线(WL)形成栅极，漏极与源电极都由p型扩散层12构成。浮栅(FG)通过一个隧道氧化膜(14)形成在c-p阱的表面上。字线(WL)通过一个绝缘膜(15)层叠在浮栅(FG)上。源电极通过第二选择晶体管(S)以及第一连接孔(CB)连接到由第一金属(M0)制成的公用源线(c-源)上。公用源线连接到c-源控制电路(4)上。漏电极连接到由第二金属(M1)制成的位线(BL)上，这样的连接是通过第一选择晶体管(S)，第一连接孔(CB)，第一金属(M0)的中间配线以及第二连接孔(V1)。位线连接到列控制电路(2)。
图4以及图5分别显示了一个存储器单元(图3中的4-4部分)沿字线(WL2)方向的横剖图以及一个选择晶体管(图3的5-5部分)。每一列都通过一个形成在衬底上并且用绝缘材料填充的沟与相邻列绝缘，这样的材料可以是浅沟绝缘(STI)。浮栅通过STI以及绝缘膜15和字线(WL)彼此相互绝缘。近来，位于浮栅之间的空间将会小于0.1um，并且浮栅之间的电容耦合也有所增加。由于选择晶体管(S)的栅电极(SG)的形成处理步骤与浮栅(FG)和字线(WL)相同，于是就会显示出层状栅结构。这两个选择栅线(SG)在线终点分开。
图6中的表I显示了在一个特定示例中施加电压操作存储器单元阵列1的情况，每一个存储器单元的浮栅都存储两比特，具有状态“11”，“10”，“01”，“00”其中的一个状态。该表显示了当字线“WL2”以及位线“BLe”被选定进行读取以及编程的情况。通过将c-p阱提高到删除电压20V并且将选定块的字线(WL)接地，选定块的数据就被删除了。由于未被选中的块的字线(WL)，位线(BL)，选择线(SG)以及c-源都被处于一个浮动状态，所以这些也都因为与c-p阱容性耦合而都被升高到大约20V。这样以来，仅仅在选定存储器单元(M)的隧道氧化膜14(图4以及图5)上会施加一个强电场，所选定的存储器单元的数据就会由于流过隧道氧化膜14的隧道电流而被删除。被删除的单元，在本例中，处在四个可能编程状态之一，即“11”。
为了在编程过程中在浮栅(FG)内存储电子，选择字线WL2连接到编程脉冲Vpgm上，同时选择位线Ble接地。在另外一方面，为了禁止位于编程不应发生的存储器单元(M)上发生程序编制，相应的位线Ble与未选择位线Blo一样连接到电源Vdd上，例如3V。未选择字线WL0，WL1以及WL3都连接到10V上，第一选择栅(SGD)连接到Vdd上，第二选择栅(SGS)接地。因此，被编程的存储器单元(M)的通道电势被设为0V。位于编程禁止部位的通道电势由于被与字线(WL)容性耦合而被提高到大约6V左右。如上所述，在编程过程中仅仅在存储器单元(M)的隧道氧化膜14上施加了一个强电场，按照相反方向流过隧道氧化膜14的电流产生了删除作用，接下来逻辑状态从“11”变为其他的状态“10”，“01”，或者是“00”其中的一个状态。
在读取与校验操作中，选定栅(SGD与SGS)或未选定字线(WL0，WL1，WL2)升高到一个读取通过电压4.5V以便使其成为通过栅。选定字线(WL2)被连接到一个电压上，该电压等级根据每一个读取以及校验操作来设定以便确定所连接的存储器单元的阈值电压是否达到了这样的等级。例如，在READ10操作中，选定字线WL2接地，以此来检测阈值电压是否高于0V。在这个读取状态，可以说读取等级是0V。在VERIFY01操作中，选定字线WL2连接到2.4V，以此来校验是否阈值电压达到了2.4V。在该校验状态，可以说校验等级到2.4V。
选定位线(BLe)被预充电至高等级，例如0.7V。如果阈值电压高于读取或校验等级，由于不导电存储器单元(M)的原因，连接位线(BLe)的电势等级会保持该高等级。另一方面，如果阈值电压低于读取或校验等级的话，由于导电的存储器单元(M)的原因，连接位线(BLe)的电势等级会降低至一个例如低于0.5V这样的低等级。读取与校验操作的进一步详细情况将在下面进行说明。
图7显示了图1所示列控制电路2的一部分。每一对位线(BLe与BLo)都连接到包括两个数据存储(DS1和DS2)寄存器的数据存储部分16上，其中的每一个数据存储寄存器都可以存储一位数据。数据存储部分16在读取或校验操作中读出选定位线(BL)的电势等级并且按照二进制的方式存储数据，以及在编程操作中控制位线电压。数据存储部分16通过选择“EVENBL”和“ODDBL”中的一个信号而被有选择地连接到选定位线(BL)上。数据存储部分16也连接到I/O线上以便输出读取数据并且存储编程数据。I/O线参照前面图1中所述的那样连接到数据输入/输出缓冲器6上。
存储器系统的通常操作
图8显示了当每一个浮栅存储元件在每一个存储器单元(M)都存出两比特数据，即四个数据状态的时候，存储器单元阵列1的阈值电压分布状态。曲线25表示了在删除状态(“11”数据状态)下阵列1内部的单元的阈值等级V7的分布状态，它是负阈值电压等级。分别存储“10”和“11”用户数据的存储器的阈值电压分布状态曲线26和27，显示为介于0V至1V与1V至2V之间。曲线28显示了被编程至“01”数据状态的单元分布状态，读取通过电压最高阈值电压等级设定为高于2V而低于4.5V。
存放在每一个单独存储器单元(M)内的2位中的每一个在本例中都是来自不同的逻辑页。这就是说，存放在每一个存储器单元内的两个位中的每一个都携带彼此互不相同的逻辑页地址。图8中所示的右侧位是在较低页地址(＝0，2，4，...，16，382)被输入的时候被访问。左侧位是在较高页地址(＝1，3，5，...，17，383)被输入的时候被访问。
为了提供改进的可靠性，最好是使独立的分布状态紧密(分布状态窄化)，因为更近的分布状态会带来一个较宽的读取宽度(其间的距离)。根据本发明，分布状态宽度在不限制降低编程速度的前提下被变紧。
根据标题为“用于多等级NAND EEPROM的快速精确编程方法，第129-130页，VLSI技术论文集1995年目录”的文章，该文章以参考的方式被包含在本文中，该文章中将分布状态限制在0.2V宽度要求通常重复的编程脉冲在步长之间提高0.2V。为了将分布状态限定在0.05V宽度，就要求0.05V的步长脉冲增加量。为了用这样的小步长增加对单元编程会导致编程时间提高4倍。然而，根据本发明的主要方面，如下所述，这样的编程时间的明显增加并不会降低阈值电压分布状态的宽度。
图9A和图9B分别表示现有编程脉冲技术以及编程为特定状态的单元的阈值分布宽度。图9A显示了一个编程电压Vpgm的波形信号。编程电压Vpgm被分成为多个脉冲，每一个脉冲都递增0.2V。可以说一个Vpgm步长大小为0.2V。在本例中Vpgm的起始电平为12V。最快速编程存储器单元的阈值电压变化由图9B中的白色方形所代表。最快速编程存储器单元在14V脉冲之后达到第一通过校验等级。结果分布状态的最大宽度是ΔVT＝0.2V。
在脉冲间的阶段，编程校验操作被执行。这就是说，被编程的每一个单元的编程等级都在每一个编程脉冲间同时被读出以便决定其是否等于或大于要被编程的校验等级。如果确定给定存储器单元的阈值电压已经达到校验等级的话，通过提高位线的电压提高至给定单元的系列单元从0V至Vdd被连接来移除Vpmg。其他被编程单元的编程依然继续直到其依次达到它们的校验等级为止。当在单元的最后一个编程脉冲当中，阈值电压从低于校验等级到高于该等级的时候，阈值电压的漂移等于Vpgm的步长值0.2V。这样一来，阈值电压就被控制在一个0.2V宽度内。
图10A以及10B显示了对上述类型的4状态NAND存储器单元阵列进行编程的具体现有技术。在第一编程通道，单元的阈值等级根据来自较低逻辑页的位来设定。如果那个位是“1”，由于在那个状态是早期已经被删除的结果，所以什么都不会发生。然而，如果该位是“0”，单元等级被提高到第一编程状态34。这将结束第一编程通道。
在第二编程通道，单元的阈值等级根据来自较高逻辑页存储在单元中的位来设定。如果为“1”，由于单元处在状态33或34中的一个而不会对其进行编程，这些状态取决于较低页位的编程，每一种都带有上页位“1”。如果上页位是“0”，单元就会被第二次编程。如果第一通道导致单元保持在删除状态33，单元从该状态被编程至最高状态36，如图10B高箭头所示。如果单元由于第一编程通道被编程到状态34的话，那么该单元被进一步在第二通道被从该状态编程成为状态35，如图10B编程较低箭头所示。第二通道的结果是在不改变第一通道编程结果的前提下，将单元编程到被指定的状态以从上页存储“0”。
当然，如果存储器被按照多于四种状态进行操作的话，就会有多个分布在存储器单元的设定电压阈值内部窗口内，其与状态数量相等。进一步来说，尽管每一个分布状态都被分配了特定的位组合，但是不同的位组合也可以被分配，在这种情况下，介于编程发生之间的状态可以与图10A以及10B所示的不同。在背景技术参考的Toshiba专利中有这种变化。
通常，被同时编程的单元沿着字线是交替的。图11显示了沿着一个字线44排列的多个单元中的三个存储器单元41，42，43。一组交替的单元，包括单元41和43，存储逻辑页0和2(“偶数页”)的位，同时另外一个交替单元，包括单元42，存储逻辑页1和3(“奇数页”)的位。这导致在一个按照一次4页数据的顺序重复完整的编程周期当中，对在一行存储器单元上的至少4页数据进行编程。
在参照上图10A和10B对一行中的至少一部分存储器单元进行的第一编程步骤中，来自较低页0的位被首先编程到第一组独立的交替单元并且接下来来自较低页1的位到被编程到独立的第二交替单元。经过这些步骤之后，页0，2以及页1，3的编程状态分布“11”(还有删除状态)和“10”都如图11所示的实线存在了。来自于较高页2的位接下来被编程到第一组交替单元，接下来是将较高页3编程到第二组交替单元这一最终步骤。由于上述的Yupin效应，显现出来的“11”和“10”状态的分布变得比在其编程之后存在的实线所显示的阈值分布稍宽，如较宽的点划线所示。这是由于当最初低页0和1的数据编程是在一个没有相邻的浮栅包括代表状态“00”和“01”的高负载等级存在的环境下进行的。所显示出来的最初分布状态的变宽是发生在当相邻单元被编程至其较高阈值等级状态的时候。进一步说，由于相邻的浮栅被来自页3的数据写入以便将其电荷等级提高至奇数页的“00”和“01”状态的原因，页0，2的较高状态“00”和“01”也会受到该显现变宽的效应的影响。
该显现变宽的效应是向存储器可能被操作的状态数量增加了一个限制，并且产生了其他操作上的限制。这需要在状态分布之间保持一个足够大的富裕量以便较宽显现分布状态可以在数据读取操作中被清晰地辨别出来。仅仅是如图11所示的页1，3的不带有虚线阈值等级发散发生的最后两个被编程状态不会被Yupin效应所影响，这是因为相邻浮栅的电荷等级不会再变化的原因。如图10B所示，来自于图11所示的页1，3的存储器单元储存位的“00”以及“01”状态被最后编程。而对于其他六个来自页0，2以及1，3的单元存储位状态来说，由于介于浮栅之间的电场耦合，而使得相邻单元接下来的编程影响其显现阈值电压分布。
新编程技术示例
图12说明参照图9-11的上述编程技术的两个改进效果。首先，页被编程的顺序被改变，从而使得首个被编程的两页数据位被写入到一列中的第一交替存储器单元，接下来是将下面两个数据位写入到第二交替单元。这就会有去除来自Yupin效应的两个附加编程状态的效果。其次，初始状态分布被收缩(压缩)以便使得仍由Yupin效应所产生的显现变宽现象依然使有效分布状态宽度较小，最好是不超过首次编程的实际分布状态。上述优点的每一个都可以独立被实现，或者被同时采用。图12就显示了其被共同使用的例子。
在如图11所示的为第一和第三组交替存储器单元所设定的相同数据页被编程的时候，如图12显示的第一个改进是顺序将来自第0和2页的数据写入到第一组单元，接下来是将来自第1和3页的数据写入到第二组单元。这就是说，并不是交替将四页数据写入到第一和第二和选择单元，如图11的例子那样，而是在第二组被任何数据编程之前，第一组用两页数据编程。第二组交替存储器单元随后用第三和第四页数据编程。结果是如图所示的存储器单元存储页1，3的状态“10”相关的Yupin效应被消除了。这是因为相邻第一组交替存储器单元(存储页0，2)的浮栅电荷等级在第二组单元被数据页1，3所编程之后并没有增加。页1，3的所有三个编程状态都不会产生Yupin效应，从而降低了不正确读取所存储的数据页1，3的可能性。
但是因为在第一组单元被数据页0，2编程之后，第二组交替存储器单元被数据页1，3所编程，所以第一组的存储状态会受到Yipin效应的影响。为了克服这个问题，第一组单元的阈值电压分布状态被压缩。参照图10A，数据页0的最初编程会产生分布状态51。然而在数据页2被编程之前，分布状态被重新编程以便减少分布状态的宽度，如曲线52所示。在所有4页的编程都完成之后，Yupin效应会引发状态阈值分布“10”的显示范围扩大到如曲线53所示的范围。显示分布状态53最要被控制在等于或小于与最初分布状态51的范围。
在数据页0被编程并且压缩之后，当将数据页2编程到编程状态“00”和“01”之一的时候，相同的处理被执行。数据被首先写入到第一组交替单元，压缩并且通过Yupin效应从相邻第二组交替单元的后来编程过程有效扩展。
图13显示了实现如图12所示2种压缩状态分布之一的执行步骤。状态被首先针对第一校验等级61用数据编程。这就是说，在每一个编程电压脉冲施加到被编程的单元上以达到该状态之后，那些单元通过向其施加适当的电压条件被读取来确定单个单元的阈值电压等级是否达到或超过了等级61。如果是这样的话，编程就会停止。如果不是的话，一个附加编程脉冲就会被施加并且状态会被再次读取。结果是一组存储器单元被编程至给定的状态，该状态带有一个如曲线62所示的电压阈值分布状态。如上所述，分布状态62的宽度由所施加的编程脉冲的值，最初是脉冲之间的电压变化来控制。
为了收缩该分布，在所有的单元被同时编程到该状态完成之后，它们的状态通过使用一个比等极61稍低的阈值等级63来读取。这通过仅仅读取那些编程到所关心的一个状态的单元来区分那些编程到其它状态的单元。或者是，如数据可以通过寄存器来获取。通过使用高于第一校验等级61的阈值电压校验等级64以及将其限制在分布62范围内，那些单元到该状态的第二编程操作(第二通道)会被执行。该第二编程操作的效果就是要对那些低于等级64的编程阈值电压等级的单元再编程为高于校验等级64，如分布状态65所示。可以从图13上看出的实际阈值等级分布状态65要窄于初始分布状态62 。当其它相邻单元通过提高其存储电荷等级被编程后，显现出来的分布状态会由于Yupin效应而被加宽，如分布状态66所示。该显现出来的分布状态66的宽度要比如果没有第二编程过程的时候的宽度小，其数量是大约等于校验等级61以及64之间的差。
图14A和14B显示了包括参照图13所述的第二编程步骤的参照图9A和9B所述的编程方法改进。第二编程通道(第二通道写)步骤的使用，以及第一通道(61)和第二通道(64)的不同校验等级被显示出来。最快编程存储器单元的阈值电压变化通过图14B所示的白色方框表示，最慢的部分由黑色方框表示。第一编程通道(第一通道写)与现有编程步骤类似，但是使用一个相对较低的校验等级61。用于第二编程通道的校验等级64可以是与现在所使用的校验等级相同。
当阈值电压作为一个编程脉冲的结果从低于第一通道校验等级61开始变化的时候，在本例中阈值电压的漂移与ΔVpgm步长值0.2V相同。这样的话，阈值电压被控制在具有0.2V宽度的分布62内，与现有技术相同，但是由于较低校验等级61的原因，分布状态被置于低于来自现有技术的结果的位置。
在第一通道写完成之后和第二通道写开始之前，那些带有高于第一通道写的校验等级61并且低于第二通道写的校验等级64的存储器单元就成为第二通道写的目标。如果最快编程存储器单元在例如一个13.8V脉冲之后达到了第一通道写的校验等级61，第二通道写的起始Vpmg电平被设定为13.4V或者是低于13.4V，从而将阈值电压漂移降至低于0.2V。在本例中，第二通道写的起始编程电压Vpmg电平被设定为13.4V，然而第一通道写的是12V。当单元通道的阈值电压由于第二通道写的一个编程脉冲，从低于校验等级64变为高于该等级的时候，阈值电压的漂移被保持为低于0.05V。从而，目标存储器单元的阈值电压分布被控制在一个0.05V宽度的范围内，这是大大高于现有技术的。这样一来，如果第一通道写的校验等级61比第二通道写的校验等级64小至少0.15V的话，阈值电压分布的总宽度就是0.05V。
在本例中，第二通道写的最大Vpgm电平最坏的情况下也会比第一通道写的高出0.2V，这是因为在第二通道中使用了高出0.15V的校验等级。另外，由于第二通道写的起始Vpgm可以大大高于第一通道写，第二通道写的时长通常是短于第一通道写。所以，可以看出通过两个编程通道来将阈值电压分布宽度从0.2V降低到0.05V所需要的执行成本是小于双倍的编程时间的。使用0.05V的ΔVpgm步长大小达到相同的压缩编程分布宽度的现有的编程技术中，编程时间比宽度是0.2V时所用的时间延长了4倍。两编程通道技术所需要的编程时间比使用现有技术为了达到相同阈值电压分布所需要的时间快了几乎两倍。
图15A和15B分别对应于图14A和14B，显示了一个改进，其中第一编程通道的ΔVpgm步长大小变大，这是为了减少编程时间，同时第二编程通道保持相同以便限定一个较窄的分布状态宽度。在本例中， 第一通道写的ΔVpgm步长从0.2V提高到0.4V。第一通道写的校验等级被降低到0.2V，同时第一通道写和第二通道写的校验等级之间的差从0.2V提高到0.35V。0.2V的延伸等于ΔVpgm步长大小的差(0.4V-0.2V)。第一通道写和第二通道写的编程电压Vpgm起始电平与图14A中所示的0.2V步长Vpgm例子相同。第一通道写的持续时间被减少了大约一半，从而比图14A和14B所示的0.2V步长Vpgm的例子的编程时间降低了多于25％。
在图14A与15A中的每一个，第一通道写的最初少量编程脉冲也可以不需要其间(未显示)的时间来形成，以便读取和校验目标存储器单元上的编程等级。这是因为几乎没有目标单元在最初几个脉冲就能达到其设定的阈值等级。这也可以用在第二通道写的头几个脉冲被完成。其结果是可以进一步降低编程时间。
上述参照图12-15的具体实施例在初始编程一结束后，并且在执行对相邻单元的编程之前，从而在最初编程状态被Yupin效应失真之前，就使用在编程步骤来压缩编程分布状态。在下面参照图16-18所描述的实施例当中，分布状态的压缩重新编程步骤发生在全部状态都被初始编程完成，从而由于Yupin效应在对阈值等级分布状态的失真已经存在后的一个较晚的阶段。
参照图16，一种编程技术被说明，其中页0，2被首先编程到一行的第一组的交替存储元件，接下来是将页1，3被编程到同一行中的第二组交替存储元件。因为一组在另外一组存储元件被编程之前就被使用来自所有页的数据完全编程，所以就不会有因为Yupin现象而产生的显现出来的后编程页面，在本例中是页1，3，的状态分布变宽的现象出现。然而，因为沿着选定字线的相邻第一和第二组交替存储元件的容性耦合，因此这样的第一编程页面，这里是页0，2，状态分布的显现扩大也会发生。一种修正页0，2的显现分布漂移的方法是使用相同的校验等级，用通常方式使用相同数据对第一组存储元件进行重新编程。这会导致页0，2的状态分布漂移，这是因为其重新编程是在相邻存储元件的电荷等级影响下被执行的。新的重新编程分布然后修正初始编程数据，在本例中是页0，2，的Yupin效应。
然而，通常希望在重新编程的同时压缩状态分布。这不会导致性能下降，因为压缩的主要步骤是使用不同的校验等级重新编程。这已经参照图13被说明过了，其中压缩重新编程发生在相邻存储元件被编程之前，从而影响到被压缩的状态分布。在图16所显示的编程顺序下，压缩重新编程是在相邻的存储元件被编程之后发生的。
在图17所示的编程顺序下，显示了对数据页0，2的状态分布进行压缩重新编程的过程。在初始的使用校验等级71对页0，2进行编程之后，以及在对页1，3进行编程之前，每一个状态的分布如曲线72所示。在页1，3被编程之后，该分布会变宽，如曲线75所示。在该状态下使用读取等级73读取单元之外，并用一个校验等级74进行重新编程，结果就是如曲线76所示的显示分布状态，同时实际分布状态如点划线77所示。所施加的编程以及再编程脉冲与图14A所示的类似。通过比显示出来的分布状态75窄的显示出来的分布状态76执行了预定的压缩。
图18和19显示了分别与图16和17相对应的相同编程顺序与再编程步骤，除了初始编程使用的编程电压脉冲(第一通道写)在每一个脉冲都增加0.4V，而再编程电压脉冲(第二通道写)的每一个脉冲都增加0.2V，如图15A所示的那样。初始编程通道上的更高的ΔVpgm缩短了编程与再编程处理完成所需要的时间。
图20显示了在使用根据本发明的不同方面的另外一种可能的编程技术。该方法包括参照图12，13所说的步骤，接下来还包括对初始数据页0，2进行第二次再编程的附加步骤。该第二个再编程发生在其他数据页1，3已经被编程完成时候，并且不需要包括对状态分布的压缩，但是能够做到。
尽管根据本发明的前两个方面的示例性实施例是结合带有一个NAND存储器单元阵列结构的快擦写EEPROM系统进行说明的，应当认识到这些以及本发明的其他方面都可以应用于任何闪存结构(例如带有NOR存储器单元结构的快擦写EEPROM系统)或者其他类型的非易失性存储器，其中，在存储元件之间会有一些耦合影响表示相同存储器状态的存储等级显示分布，并且希望能够减小该效果。
示例性编程算法
图21显示了根据参照图12，13和14所说的技术，对较低页的偶数行进行编程的示例性算法。该算法可以分成三个部分。第一部分是由虚线(S1到S4)所包围的部分。该部分显示了界面程序。一开始(S1)，“数据加载”命令由闪存控制器发出并且输入到数据输入/输出缓冲器(6)。输入数据被作为命令识别并且锁存在状态机(8)，因为这个时候有一个未显示的命令锁存信号被输入到命令界面(7)。下一步(S2)，指定页面地址的地址数据被从控制器输入到数据输入如/输出缓冲器(6)，然后锁存。输入数据被识别为页面地址并且锁存在状态机(8)，因为这时有一个未显示出的锁存信号被输入到命令界面(7)。接下来(S3)，532B-编程-数据被输入到数据输入/输出缓冲器(6)上。输入数据被锁存到数据存储器1(DS1)，因为“数据加载”命令在此时被锁存。在最终(S4)，“编程”命令被闪存控制器发生并且输入到数据输入/输出缓冲器(6)上。该输入数据被识别为命令并且锁存在状态机(8)，因为此时命令锁存信号被输入到命令界面(7)。由“编程”命令所触发，锁存在数据存储器1(DS1)上的数据被自动编程(S5到S20)到状态机(8)所控制的选定存储器单元(M)。
该算法的第二部分是S5到S10步骤的第一通道写。首先，起始Vpgm被设定为12V同时嵌入在状态机(8)中的编程计数器被设定为0(S5)。接下来，第一编程脉冲施加到选定的字线上，例如表I所示的WL2(S6)。如果锁存在数据存储器1(DS1)中的是“0”数据，相应的位线(BL)就接地(“编程激发”表I)。另一方面，如果锁存在数据存储器1(DS1)中的是“1”数据，相应的位线(BL)就连接到Vdd上(“编程禁止”表I)。
在编程之后，选定存储单元的状态被校验。为了校验，第一通道的校验10被执行(S7)。在该项操作中，阈值电压被检测是否达到了第一通道的0.2V校验等级，如表I所示。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。以这种方式，由于数据“0”一个一个地变成数据“1”，而数据“1”也不依靠于存储器单元的状态独立保持，最终所有锁存在数据存储器DS1上的数据都会变成“1”数据。这意味着所有存储器都被通过来自第一通道的校验等级来判断之后而成功编程。
在校验操作之后，会检查是否所有的锁存在数据存储器DS1上的数据都变成了数据“1”(S8)。如果都已经变成了“1”，第一通道写就被终止并且第二通道写开始。如果没有变成“1”数据，算法前进至步骤S9。
在步骤S9，编程计数器的计数值被检查。如果计数值小于20，Vpgm等级提高0.2V，并且计数值增加1(S10)，同时算法返回到编程步骤S6。如果计数值不小于20，状态机中的状态数据被设定为“失败”，然后算法终止(S11)。
算法的第三部分是第二通道写(S12至S20)。起初，第二通道的读取10被执行(S12)。在该项操作中，阈值电压高于0V的存储器单元被抽出，并且“0”数据被设定到相应的数据存储器1(DS1)。“1”数据被设定到剩下的数据存储器1(DS1)。
接下来，第二通道的校验10被执行(S13)。在该项操作中，那些阈值电压在0V以上，0.4V以下的存储器单元通过使用0.4V的第二通道校验等级以及已经存储在数据存储器1(DS1)上的数据被抽出。阈值电压被检测是否达到了如表I所示的第二通道的校验等级。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。
在第二通道的校验10(S13)之后，起始Vpgm被重置为13.4V同时编程计数器被重新初始化为0(S14)。接下来，第一编程脉冲13.4V施加到选定字线上，如表I所示(S15)。如果锁存在数据存储器1(DS1)中的是“0”数据，相应的位线(BL)就接地(“编程激发”表I)。另一方面，如果锁存在数据存储器1(DS1)中的是“1”数据，相应的位线(BL)就连接到Vdd上(“编程禁止”表I)。
在编程之后(S15)，选定存储器单元的状态被校验。为了校验，第二通道的校验10被执行(S16)。在该项操作中，阈值电压被检测是否达到了第二通道的0.4V校验等级，如表I所示。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。以这种方式，由于数据“0”一个一个的变成数据“1”，而数据“1”也不依靠于存储器单元的状态独立保持，最终所有锁存在数据存储器DS1上的数据都会变成“1”数据。这意味着所有存储器都被成功编程。
在校验步骤之后(S16)，会检测是否所有的锁存在数据存储器DS1上的数据都变成了数据“1”(S17)。如果都已经变成了“1”，第二通道写就被终止并且整个程序算法被终止，设定状态数据为“通过”(S20)。如果没有变成“1”数据，算法前进至步骤S18。
在步骤S18，编程计数器的计数值被检测。如果计数值小于13，Vpgm等级提高0.2V，并且计数值增加1(S19)，同时算法返回到编程步骤S6。如果计数值不小于13，状态机当中的状态数据被设定为“失败”，然后算法终止(S11)。
图22显示了根据参照图12，13和14所说的技术，对较高页的偶数行进行编程的示例性算法。该算法可以分成三个部分。第一部分是由虚线(S1到S4)所包围的部分。该部分与图21所示的步骤S1至S4完全一致。
该算法的第二部分是S5到S13步骤的第一通道写。首先，第一通道的读取10被执行(S5)。在该项操作中，阈值电压高于0V的被选出，然后“0”数据被设定到相应的数据存储器2(DS2)。“1”数据被设定到剩余的数据存储器2(DS2)。存储器单元起始Vpgm被设定为14V同时编程计数器被设定为0(S6)。接下来，第一编程脉冲施加到选定的字线上，例如表I所示的WL2(S7)。如果锁存在数据存储器1(DS1)中的是“0”数据，相应的位线(BL)就接地(“编程激发”表I)。另一方面，如果锁存在数据存储器1(DS1)中的是“1”数据，相应的位线(BL)就连接到Vdd上(“编程禁止”表I)。
在编程之后，选定存储单元的状态被校验。为了校验，在第一地点校验01被执行(S8)。在该项操作中，阈值电压被检测是否达到了如表I所示的2.4V校验等级。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。在第二地点，第一通道的校验00被执行(S9)。在该项操作中，阈值电压被检测是否达到了第一通道的1.2V校验等级，如表I所示。如果检测到阈值电压已经达到并且在相应的数据存储器(DS2)中存储的数据为“0”数据，锁存在DS1中的数据“0”变为数据“1”。如果相关数据存储器2(DS2)具有“1”数据，存储在数据存储器1(DS1)中的“0”数据保持不变，而与检测结果无关。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。
以这种方式，由于数据“0”一个一个的变成数据“1”，而数据“1”也不依靠于存储器单元的状态独立保持，最终所有锁存在数据存储器DS1上的数据都会变成“1”数据。这意味着所有存储器都被通过来自第一通道的校验等级“01”状态以及第一通道的校验等级“00”状态来判断之后而成功编程。
在校验操作之后，会检查是否所有的锁存在数据存储器DS1上的数据都变成了数据“1”(S10)。如果都已经变成了“1”，第一通道写就被终止并且第二通道写开始。如果没有变成“1”数据，算法前进至步骤S11。
在步骤S11，编程计数器的计数值被检查。如果计数值小于20，Vpgm等级提高0.2V，并且计数值增加1(S12)，同时算法返回到编程步骤S7。如果计数值不小于20，状态机当中的状态数据被设定为“失败”，然后算法终止(S13)。
算法的第三部分是第二通道写(S14至S22)。起初，第二通道的读取00被执行(S14)。在该项操作中，阈值电压高于1V的存储器单元被抽出，并且“0”数据被设定到相应的各数据存储器1(DS1)。“1”数据被设定到剩下的每一个数据存储器1(DS1)。
接下来，第二通道的校验00被执行(S15)。在该项操作中，那些阈值电压在1V以上，1.4V以下的存储器单元通过使用1.4V的第二通道校验等级以及已经存储在数据存储器1(DS1)上的数据被抽出。阈值电压被检测是否达到了如表I所示的第二通道的1.4V校验等级。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。
在第二通道的校验00(S15)之后，起始Vpgm被重置为14.4V同时编程计数器被重新初始化为0(S16)。接下来，第一编程脉冲14.4V施加到选定字线上，如表I所示(S17)。如果锁存在数据存储器1(DS1)中的是“0”数据，相应的位线(BL)就接地(“编程激发”表I)。另一方面，如果锁存在数据存储器1(DS1)中的是“1”数据，相应的位线(BL)就连接到Vdd上(“编程禁止”表I)。
在编程之后(S17)，选定存储器单元的状态被校验。为了校验，第二通道的校验00被执行(S18)。在该项操作中，阈值电压被检测是否达到了第二通道的1.4V校验等级，如表I所示。如果检测到阈值电压已经达到的话，锁存在DS1中的数据“0”变为数据“1”。如果检测到阈值电压没有达到的话，锁存在DS1中的数据“0”继续保持。已经存在的数据“1”也被保持。以这种方式，由于数据“0”一个一个的变成数据“1”，而数据“1”也不依靠于存储器单元的状态独立保持，最终所有锁存在数据存储器DS1上的数据都会变成“1”数据。这意味着所有存储器都被成功编程。
在校验步骤之后(S18)，会检查是否所有的锁存在数据存储器DS1上的数据都变成了数据“1”(S19)。如果都已经变成了“1”，第二通道写就被终止并且整个程序算法被终止，设定状态数据为“通过”(S22)。如果没有变成“1”数据，算法前进至步骤S20。
在步骤S20，编程计数器的计数值被检测。如果计数值小于13，Vpgm等级提高0.2V，并且计数值增加1(S21)，同时算法返回到编程步骤S17。如果计数值不小于13，状态数据被设定为“失败”，然后算法终止(S13)。
在图22所述的算法中，对要编程到状态“01”的存储单元的第二通道写被避免，因为对“01”状态的第二通道写也要求最大的Vpgm并且也会导致不必要的编程中断。然而，如果有必要的话，根据本发明，可以很容易地实现。
图23显示了执行图12，19和15所说的技术，用较低数据页对偶数列进行编程的示例性算法。该算法与图21所示的类似。区别在于第一通道写的Vpgm步长大小(S10)以及相关的第一通道写的编程计数器最大计数值(S9)。这里的Vpgm步长大小从0.2V提高到0.4V，这是为了加速第一通道写。
图24显示了执行图12，19和15所说的技术，用较高数据页对偶数列进行编程的示例性算法。该算法与图22所示的类似。区别在于第一通道写的Vpgm步长大小(S12)以及相关的第一通道写的编程计数器最大计数值(S9)。这里的Vpgm步长大小从0.2V提高到0.4V，这是为了加速第一通道写。
图25和26显示了当分别与图21和22所示的编程算法组合时，用于执行如图12，13以及14所示的方法的示例性编程算法。图25所示的算法是对奇数列进行编程的算法。该算法不带有图21所示的对偶数列进行编程算法中的第二通道写这一过程。第一通道的校验10的校验等级从0.2V变成了0.4V，这是为了如在第二通道写中将分布设定为高于0.4V那样，将分布设定为高于0.4V。图26所示的算法是对奇数列进行编程的算法。该算法不带有图22所示的对偶数列进行编程算法中的第二通道写这一过程。第一通道的校验00的校验等级从1.2V变成了1.4V，这是为了如在第二通道写中将分布设定为高于1.4V那样，将分布设定为高于1.4V。图21，22，25与26所示算法的组合能够补偿Yupin效应。因此，编程能力被改进了。
图27和28显示了当分别与图23和24所示的编程算法组合时，用于执行如图12，19以及15所示的方法的示例性编程算法。图27所示的算法是对奇数列进行编程的算法。该算法不带有图23所示的对偶数列进行编程算法中的第二通道写这一过程。第一通道的校验10的校验等级从0.2V变成了0.4V，这是为了如在第二通道写中将分布设定为高于0.4V那样，将分布设定为高于0.4V。图28所示的算法是对奇数行进行编程的算法。该算法不带有图24所示的对偶数列进行编程算法中的第二通道写这一过程。第一通道的校验00的校验等级从1.2V变成了1.4V，这是为了如在第二通道写中将分布设定为高于1.4V那样，将分布设定为高于1.4V。
图23，24，27与28所示算法的组合能够补偿Yupin效应。因此，编程能力被改进了。
图29显示了用来执行如图12，13以及14所示的方法的示例性编程顺序。每一个方框中，数据编程是按页面地址的顺序执行的，是从字线WL0的偶数位线的较低页的到字线WL3的奇数位线的较高页。该顺序是将Yupin效应考虑在内的情况下形成的。
图30显示了根据图16，17所示的方法读取被压缩的低数据页的示例性读取算法。由虚线(S1以及S2)所包围的部分显示了接口的过程。起初(S1)，“数据读取”命令由闪存控制器发出并且输入到数据输入/输出缓冲器(6)。输入数据被作为命令识别并且锁存在状态机(8)，因为这个时候有一个未显示的命令锁存信号被输入到命令接口(7)。下一步(S2)，指定页面地址的地址数据被从控制器输入到数据输入/输出缓冲器(6)，然后锁存。输入数据被识别为页面地址并且锁存在状态机(8)，因为这时有一个未显示出的锁存信号被输入到命令接口(7)。由地址数据所触发，存储在选定存储器单元(M)上的数据被通过状态机(8)控制而自动读出(S4与S5)。
在读取01中，阈值电压高于2V的存储器单元被选出，然后“1”数据被设定到相应的数据存储器2(DS2)。“0”数据被设定到剩下的数据存储器2(DS2)。接下来，读取10被执行。在该操作中。阈值电压高于0V，低于2V的存储器单元被选出。如果检测到阈值电压低于0V或者是数据存储器2(DS2)存储“1”数据，“1”数据被设定到数据存储器1(DS1)，否则就是“0”。
存储在数据存储器1(DS1)中的数据通过数据输入/输出缓冲器与输入到命令接口(7)的读取信号(未示出)同步被输出到外部。
图31显示了根据图16，17所示的方法读取被压缩的低数据页的示例性读取算法。由虚线(S1以及S2)所包围的部分与图30所示的相同。在读取00中，阈值电压高于1V的存储器单元被选出，然后“0”数据被设定到相应的数据存储器1(DS1)。“1”数据被设定到剩下的数据存储器1(DS1)。存储在数据存储器1(DS1)中的数据通过数据输入/输出缓冲器与读取信号同步被输出到外部。
尽管本发明的不同方面都参考具体实施例进行了说明，但是应该理解本发明应该根据下面的权利要求的范围被保护。
Claims (19)
1.一种用于存储数据的非易失性存储器，其包括：
在集成电路片上的电荷存储元件的阵列，其特征在于，存储在一部分存储元件中的电荷的值由于至少在存储元件之间耦合的电场而影响从其它存储元件读出的值，以及
在所述集成电路片上的状态机，所述状态机控制将作为第一组存储值的第一组数据写入第一组存储元件中，然后将作为第二组存储值的第二组数据写入第二组存储元件中，其中，由于在它们之间耦合的电场，至少一部分第二组存储值会影响从至少一部分第一组存储元件所读出的值，然后改变第一组存储值，以便抵消至少由于在它们之间耦合的电场所引起的第二组存储值对从第一组存储元件中所读出的值的影响。
2.如权利要求1所述的存储器，其中状态机控制通过从第一组存储元件的第一组存储值读出第一组数据来改变第一组存储值，然后将所读出的第一组数据重新写入第一组存储元件，作为改变后的第一组存储值。
3.如权利要求2所述的存储器，其中状态机控制通过交替地编程并验证存储在各存储元件上的电荷等级直到各自达到所读取的第一组存储值，来将所读取的第一组数据重新写入第一组存储元件中。
4.如权利要求3所述的存储器，其中状态机控制在验证各存储元件上存储的电荷等级达到预定等级时重新设定数据存储器中锁存的数据，其后至少一个编程电压的增长速率降低。
5.如权利要求1所述的存储器，其中状态机控制写第一组数据、写第二组数据和改变第一组存储值的顺序。
6.如权利要求1所述的存储器，其中存储元件包括电浮栅，其中所存储的值是存储在通过存储器单元影响导通的浮栅上的电荷等级，其中浮栅是存储器单元的一部分。
7.如权利要求1所述的存储器，其中存储元件是在平行的排中设置的存储器单元的一部分，导通字线在其存储元件上正交地延伸横跨该排。
8.根据权利要求1所述的存储器，其中电荷存储元件阵列的特征还在于第二组存储元件上的存储值使第一组存储元件的第一组存储值的分布加宽，并且其中状态机控制通过压缩第一组存储元件的第一组存储值的加宽的分布来改变第一组存储值。
9.根据权利要求8所述的存储器，其中状态机控制通过从第一组存储元件的第一组存储值读出第一组数据来改变第一组存储值，然后将所读出的第一组数据重新写入第一组存储元件，作为改变后的第一组存储值。
10.根据权利要求1所述的存储器，其中每个存储元件存储多于一位的数据。
11.一种用于存储数据的非易失性存储器，其包括：
在集成电路片上的电荷存储元件的阵列，其特征在于，存储在存储元件的至少相邻的一部分中的电荷的值由于在存储元件之间耦合的电场而影响从其它存储元件读出的值；
数据存储器，用于临时存储要被编程到电荷存储元件的阵列中的数据；以及
在所述集成电路片上的状态机，所述状态机控制将作为第一组存储值的在所述数据存储器中存储的第一组数据写入第一组存储元件中，然后将作为第二组存储值的在所述数据存储器中存储的第二组数据写入第二组存储元件中，其中，由于在它们之间耦合的电场，至少一部分第二组存储值会影响从至少一部分第一组存储元件所读出的值，然后通过从第一组存储元件的第一组存储值读取第一组数据而不是从数据存储器读取第一组数据，来改变第一组存储值，以便抵消第二组存储值对从第一组存储元件中所读出的值的电荷耦合影响，然后将所读出的第一组数据重新写入第一组存储元件，作为改变后的第一组存储值。
12.根据权利要求11所述的存储器，其中状态机控制通过交替地编程并验证存储在各存储元件上的电荷等级直到各自达到所读取的第一组存储值，来将所读取的第一组数据重新写入第一组存储元件中。
13.如权利要求12所述的存储器，其中状态机控制在验证各存储元件上存储的电荷等级达到预定等级时重新设定数据存储器中锁存的数据，其后至少一个编程电压的增长速率降低。
14.如权利要求11所述的存储器，其中状态机控制写第一组数据、写第二组数据和重新写第一组数据的顺序。
15.一种在集成电路基板上形成的非易失性存储器，其包括：
多个导通位线；
多个存储器单元的排，其各自包括多个相互串行连接并通过位于该排的末端的选择晶体管选择性地连接到位线中的一个的存储器单元，其中存储器单元各自包括电荷存储元件，排具有取向为列的长度，沿第一方向横跨基板延伸并在第二方向上分开，第一和第二方向相互正交；
多个导通字线，其长度沿第二方向延伸、横跨多个排中的多行存储器单元的电荷存储元件，字线在第一方向上分开，以及
在基板上形成的状态机，其控制位线和字线，以将作为第一组存储值的第一组数据写到第一组存储元件中，然后将作为第二组存储值的第二组数据写到与第一组相邻的第二组存储元件中，然后将第一组存储值重新编程到第一组存储元件中，从而抵消由于第一和第二组存储元件之间耦合的电场所引起的第二组存储值对从第一组存储元件中所读出的值的影响。
16.根据权利要求15所述的存储器，其中电荷存储元件是导通的浮栅。
17.根据权利要求15所述的存储器，其中状态机控制通过从第一组存储元件中读出第一组数据重新编程第一组存储值，然后将所读出的第一组数据重新编程到第一组存储元件中。
18.根据权利要求17所述的存储器，其中电荷存储元件是导通的浮栅。
19.如权利要求18所述的存储器，其中状态机控制写第一和第二组数据和读第一组数据的顺序。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/893,277 US6522580B2 (en) | 2001-06-27 | 2001-06-27 | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
| US09/893,277 | 2001-06-27 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021434670A Division CN100350503C (zh) | 2001-06-27 | 2002-06-27 | 降低非易失性存储器存储元件间耦合效应的方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101127240A CN101127240A (zh) | 2008-02-20 |
| CN101127240B true CN101127240B (zh) | 2012-02-08 |
Family
ID=25401316
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021434670A Expired - Lifetime CN100350503C (zh) | 2001-06-27 | 2002-06-27 | 降低非易失性存储器存储元件间耦合效应的方法 |
| CN2007101537555A Expired - Lifetime CN101127240B (zh) | 2001-06-27 | 2002-06-27 | 降低非易失性存储器存储元件间耦合效应的方法 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021434670A Expired - Lifetime CN100350503C (zh) | 2001-06-27 | 2002-06-27 | 降低非易失性存储器存储元件间耦合效应的方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (4) | US6522580B2 (zh) |
| EP (2) | EP1271553B1 (zh) |
| JP (1) | JP4221196B2 (zh) |
| KR (1) | KR100926950B1 (zh) |
| CN (2) | CN100350503C (zh) |
| AT (1) | ATE364885T1 (zh) |
| DE (1) | DE60220590T2 (zh) |
| TW (1) | TW583672B (zh) |
Families Citing this family (702)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5657332A (en) * | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
| US7149110B2 (en) * | 1999-01-14 | 2006-12-12 | Silicon Storage Technology, Inc. | Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system |
| KR100544175B1 (ko) * | 1999-05-08 | 2006-01-23 | 삼성전자주식회사 | 링킹 타입 정보를 저장하는 기록 매체와 결함 영역 처리 방법 |
| USRE40110E1 (en) * | 1999-09-20 | 2008-02-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device for storing multivalued data |
| JP3631463B2 (ja) | 2001-12-27 | 2005-03-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US6584017B2 (en) * | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| JP4907011B2 (ja) * | 2001-04-27 | 2012-03-28 | 株式会社半導体エネルギー研究所 | 不揮発性メモリとその駆動方法、及び半導体装置 |
| US6522580B2 (en) * | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
| US6762092B2 (en) * | 2001-08-08 | 2004-07-13 | Sandisk Corporation | Scalable self-aligned dual floating gate memory cell array and methods of forming the array |
| US6985388B2 (en) * | 2001-09-17 | 2006-01-10 | Sandisk Corporation | Dynamic column block selection |
| US7170802B2 (en) * | 2003-12-31 | 2007-01-30 | Sandisk Corporation | Flexible and area efficient column redundancy for non-volatile memories |
| US6717847B2 (en) * | 2001-09-17 | 2004-04-06 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
| US7554842B2 (en) * | 2001-09-17 | 2009-06-30 | Sandisk Corporation | Multi-purpose non-volatile memory card |
| JP2003134414A (ja) * | 2001-10-22 | 2003-05-09 | Pioneer Electronic Corp | 映像処理装置及び映像処理方法並びに映像処理用プログラム |
| US6967872B2 (en) * | 2001-12-18 | 2005-11-22 | Sandisk Corporation | Method and system for programming and inhibiting multi-level, non-volatile memory cells |
| JP3977799B2 (ja) * | 2003-12-09 | 2007-09-19 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US7301806B2 (en) * | 2001-12-27 | 2007-11-27 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device adapted to store a multi-valued in a single memory cell |
| DE60134870D1 (de) * | 2001-12-28 | 2008-08-28 | St Microelectronics Srl | Programmierverfahren für eine Multibitspeicherzelle |
| US6542407B1 (en) * | 2002-01-18 | 2003-04-01 | Sandisk Corporation | Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells |
| US6894930B2 (en) | 2002-06-19 | 2005-05-17 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND |
| AU2003237515A1 (en) * | 2002-06-19 | 2004-01-06 | Sandisk Corporation | Deep wordline trench to shield cross coupling between adjacent cells for scaled nand |
| US6894931B2 (en) * | 2002-06-20 | 2005-05-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
| US6781877B2 (en) * | 2002-09-06 | 2004-08-24 | Sandisk Corporation | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells |
| US7254668B1 (en) * | 2002-10-28 | 2007-08-07 | Sandisk Corporation | Method and apparatus for grouping pages within a block |
| US7039788B1 (en) | 2002-10-28 | 2006-05-02 | Sandisk Corporation | Method and apparatus for splitting a logical block |
| JP3935139B2 (ja) | 2002-11-29 | 2007-06-20 | 株式会社東芝 | 半導体記憶装置 |
| US7073103B2 (en) * | 2002-12-05 | 2006-07-04 | Sandisk Corporation | Smart verify for multi-state memories |
| US6829167B2 (en) * | 2002-12-12 | 2004-12-07 | Sandisk Corporation | Error recovery for nonvolatile memory |
| US6944063B2 (en) | 2003-01-28 | 2005-09-13 | Sandisk Corporation | Non-volatile semiconductor memory with large erase blocks storing cycle counts |
| US6859397B2 (en) * | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
| KR100512181B1 (ko) * | 2003-07-11 | 2005-09-05 | 삼성전자주식회사 | 멀티 레벨 셀을 갖는 플래시 메모리 장치와 그것의 독출방법 및 프로그램 방법 |
| US6914823B2 (en) * | 2003-07-29 | 2005-07-05 | Sandisk Corporation | Detecting over programmed memory after further programming |
| US6917542B2 (en) | 2003-07-29 | 2005-07-12 | Sandisk Corporation | Detecting over programmed memory |
| US6933557B2 (en) * | 2003-08-11 | 2005-08-23 | Atmel Corporation | Fowler-Nordheim block alterable EEPROM memory cell |
| US7046555B2 (en) | 2003-09-17 | 2006-05-16 | Sandisk Corporation | Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance |
| US6958936B2 (en) * | 2003-09-25 | 2005-10-25 | Sandisk Corporation | Erase inhibit in non-volatile memories |
| US7188228B1 (en) | 2003-10-01 | 2007-03-06 | Sandisk Corporation | Hybrid mapping implementation within a non-volatile memory system |
| US7173852B2 (en) * | 2003-10-03 | 2007-02-06 | Sandisk Corporation | Corrected data storage and handling methods |
| US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
| JP2005116132A (ja) * | 2003-10-10 | 2005-04-28 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US7177199B2 (en) * | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
| US7265499B2 (en) * | 2003-12-16 | 2007-09-04 | Microsemi Corporation | Current-mode direct-drive inverter |
| US7433993B2 (en) * | 2003-12-30 | 2008-10-07 | San Disk Corportion | Adaptive metablocks |
| US7383375B2 (en) * | 2003-12-30 | 2008-06-03 | Sandisk Corporation | Data run programming |
| US8504798B2 (en) * | 2003-12-30 | 2013-08-06 | Sandisk Technologies Inc. | Management of non-volatile memory systems having large erase blocks |
| US7173863B2 (en) | 2004-03-08 | 2007-02-06 | Sandisk Corporation | Flash controller cache architecture |
| US7631138B2 (en) | 2003-12-30 | 2009-12-08 | Sandisk Corporation | Adaptive mode switching of flash memory address mapping based on host usage characteristics |
| US20050144363A1 (en) * | 2003-12-30 | 2005-06-30 | Sinclair Alan W. | Data boundary management |
| US7139864B2 (en) * | 2003-12-30 | 2006-11-21 | Sandisk Corporation | Non-volatile memory and method with block management system |
| US7594135B2 (en) * | 2003-12-31 | 2009-09-22 | Sandisk Corporation | Flash memory system startup operation |
| US7154779B2 (en) * | 2004-01-21 | 2006-12-26 | Sandisk Corporation | Non-volatile memory cell using high-k material inter-gate programming |
| US6888758B1 (en) | 2004-01-21 | 2005-05-03 | Sandisk Corporation | Programming non-volatile memory |
| US7372730B2 (en) * | 2004-01-26 | 2008-05-13 | Sandisk Corporation | Method of reading NAND memory to compensate for coupling between storage elements |
| US7068539B2 (en) * | 2004-01-27 | 2006-06-27 | Sandisk Corporation | Charge packet metering for coarse/fine programming of non-volatile memory |
| US7139198B2 (en) * | 2004-01-27 | 2006-11-21 | Sandisk Corporation | Efficient verification for coarse/fine programming of non-volatile memory |
| US7002843B2 (en) * | 2004-01-27 | 2006-02-21 | Sandisk Corporation | Variable current sinking for coarse/fine programming of non-volatile memory |
| JP4170952B2 (ja) | 2004-01-30 | 2008-10-22 | 株式会社東芝 | 半導体記憶装置 |
| JP2008176924A (ja) * | 2004-01-30 | 2008-07-31 | Toshiba Corp | 半導体記憶装置 |
| US7161833B2 (en) | 2004-02-06 | 2007-01-09 | Sandisk Corporation | Self-boosting system for flash memory cells |
| US7466590B2 (en) | 2004-02-06 | 2008-12-16 | Sandisk Corporation | Self-boosting method for flash memory cells |
| US7355237B2 (en) * | 2004-02-13 | 2008-04-08 | Sandisk Corporation | Shield plate for limiting cross coupling between floating gates |
| US7716413B2 (en) * | 2004-02-15 | 2010-05-11 | Sandisk Il Ltd. | Method of making a multi-bit-cell flash memory |
| US8019928B2 (en) * | 2004-02-15 | 2011-09-13 | Sandisk Il Ltd. | Method of managing a multi-bit-cell flash memory |
| JP2005235287A (ja) * | 2004-02-19 | 2005-09-02 | Nec Electronics Corp | 不揮発性半導体記憶装置のプログラミング方法、プログラミング装置、及び、不揮発性半導体記憶装置 |
| US7310347B2 (en) * | 2004-03-14 | 2007-12-18 | Sandisk, Il Ltd. | States encoding in multi-bit flash cells |
| US20050213393A1 (en) * | 2004-03-14 | 2005-09-29 | M-Systems Flash Disk Pioneers, Ltd. | States encoding in multi-bit flash cells for optimizing error rate |
| JP4427361B2 (ja) * | 2004-03-16 | 2010-03-03 | 株式会社東芝 | 不揮発性半導体メモリ |
| US7177977B2 (en) * | 2004-03-19 | 2007-02-13 | Sandisk Corporation | Operating non-volatile memory without read disturb limitations |
| US7020017B2 (en) * | 2004-04-06 | 2006-03-28 | Sandisk Corporation | Variable programming of non-volatile memory |
| KR100847587B1 (ko) * | 2004-04-06 | 2008-07-22 | 샌디스크 코포레이션 | 비휘발성 메모리의 가변 프로그래밍 |
| US7057939B2 (en) | 2004-04-23 | 2006-06-06 | Sandisk Corporation | Non-volatile memory and control with improved partial page program capability |
| US7023733B2 (en) * | 2004-05-05 | 2006-04-04 | Sandisk Corporation | Boosting to control programming of non-volatile memory |
| US7020026B2 (en) * | 2004-05-05 | 2006-03-28 | Sandisk Corporation | Bitline governed approach for program control of non-volatile memory |
| US8429313B2 (en) * | 2004-05-27 | 2013-04-23 | Sandisk Technologies Inc. | Configurable ready/busy control |
| US7274596B2 (en) * | 2004-06-30 | 2007-09-25 | Micron Technology, Inc. | Reduction of adjacent floating gate data pattern sensitivity |
| US7110298B2 (en) * | 2004-07-20 | 2006-09-19 | Sandisk Corporation | Non-volatile system with program time control |
| US8607016B2 (en) * | 2004-07-21 | 2013-12-10 | Sandisk Technologies Inc. | FAT analysis for optimized sequential cluster management |
| US8375146B2 (en) * | 2004-08-09 | 2013-02-12 | SanDisk Technologies, Inc. | Ring bus structure and its use in flash memory systems |
| US7294882B2 (en) * | 2004-09-28 | 2007-11-13 | Sandisk Corporation | Non-volatile memory with asymmetrical doping profile |
| US20060067127A1 (en) * | 2004-09-30 | 2006-03-30 | Matrix Semiconductor, Inc. | Method of programming a monolithic three-dimensional memory |
| US8179711B2 (en) * | 2004-10-26 | 2012-05-15 | Samsung Electronics Co., Ltd. | Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell |
| KR100645055B1 (ko) * | 2004-10-28 | 2006-11-10 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 방법 |
| US7493457B2 (en) * | 2004-11-08 | 2009-02-17 | Sandisk Il. Ltd | States encoding in multi-bit flash cells for optimizing error rate |
| US7441067B2 (en) | 2004-11-15 | 2008-10-21 | Sandisk Corporation | Cyclic flash memory wear leveling |
| US7173859B2 (en) * | 2004-11-16 | 2007-02-06 | Sandisk Corporation | Faster programming of higher level states in multi-level cell flash memory |
| US7092290B2 (en) * | 2004-11-16 | 2006-08-15 | Sandisk Corporation | High speed programming system with reduced over programming |
| US7315916B2 (en) * | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
| US7395404B2 (en) | 2004-12-16 | 2008-07-01 | Sandisk Corporation | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array |
| US7366826B2 (en) | 2004-12-16 | 2008-04-29 | Sandisk Corporation | Non-volatile memory and method with multi-stream update tracking |
| US7412560B2 (en) | 2004-12-16 | 2008-08-12 | Sandisk Corporation | Non-volatile memory and method with multi-stream updating |
| US7386655B2 (en) | 2004-12-16 | 2008-06-10 | Sandisk Corporation | Non-volatile memory and method with improved indexing for scratch pad and update blocks |
| US7149111B2 (en) * | 2004-12-17 | 2006-12-12 | Msystems Ltd. | Method of handling limitations on the order of writing to a non-volatile memory |
| US7882299B2 (en) * | 2004-12-21 | 2011-02-01 | Sandisk Corporation | System and method for use of on-chip non-volatile memory write cache |
| US7437653B2 (en) | 2004-12-22 | 2008-10-14 | Sandisk Corporation | Erased sector detection mechanisms |
| US7230851B2 (en) * | 2004-12-23 | 2007-06-12 | Sandisk Corporation | Reducing floating gate to floating gate coupling effect |
| US6980471B1 (en) * | 2004-12-23 | 2005-12-27 | Sandisk Corporation | Substrate electron injection techniques for programming non-volatile charge storage memory cells |
| US7369438B2 (en) * | 2004-12-28 | 2008-05-06 | Aplus Flash Technology, Inc. | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications |
| US7450433B2 (en) | 2004-12-29 | 2008-11-11 | Sandisk Corporation | Word line compensation in non-volatile memory erase operations |
| KR100729351B1 (ko) * | 2004-12-31 | 2007-06-15 | 삼성전자주식회사 | 낸드 플래시 메모리 장치 및 그것의 프로그램 방법 |
| US7308525B2 (en) * | 2005-01-10 | 2007-12-11 | Sandisk Il Ltd. | Method of managing a multi-bit cell flash memory with improved reliablility and performance |
| US7315917B2 (en) * | 2005-01-20 | 2008-01-01 | Sandisk Corporation | Scheduling of housekeeping operations in flash memory systems |
| US20060184719A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct data file storage implementation techniques in flash memories |
| EP1688959B1 (en) * | 2005-02-04 | 2013-04-24 | Micron Technology, Inc. | Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells |
| US7877539B2 (en) * | 2005-02-16 | 2011-01-25 | Sandisk Corporation | Direct data file storage in flash memories |
| US20060184718A1 (en) * | 2005-02-16 | 2006-08-17 | Sinclair Alan W | Direct file data programming and deletion in flash memories |
| US9104315B2 (en) | 2005-02-04 | 2015-08-11 | Sandisk Technologies Inc. | Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage |
| US7212436B2 (en) * | 2005-02-28 | 2007-05-01 | Micron Technology, Inc. | Multiple level programming in a non-volatile memory device |
| US8000502B2 (en) | 2005-03-09 | 2011-08-16 | Sandisk Technologies Inc. | Portable memory storage device with biometric identification security |
| US7187585B2 (en) * | 2005-04-05 | 2007-03-06 | Sandisk Corporation | Read operation for non-volatile storage that includes compensation for coupling |
| US7196946B2 (en) * | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling in non-volatile storage |
| US7196928B2 (en) * | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling during read operations of non-volatile memory |
| JP2006302345A (ja) * | 2005-04-15 | 2006-11-02 | Sony Corp | データ処理装置、データ再生装置、データ処理方法及びプログラム |
| ITMI20050798A1 (it) * | 2005-05-03 | 2006-11-04 | Atmel Corp | Metodo e sistema per la generazi0ne di impulsi di programmazione durante la programmazione di dispositivi elettronici non volatili |
| WO2006119327A2 (en) * | 2005-05-03 | 2006-11-09 | Atmel Corporation | Method and system for program pulse generation during programming of nonvolatile electronic devices |
| US7275140B2 (en) * | 2005-05-12 | 2007-09-25 | Sandisk Il Ltd. | Flash memory management method that is resistant to data corruption by power loss |
| US7339834B2 (en) | 2005-06-03 | 2008-03-04 | Sandisk Corporation | Starting program voltage shift with cycling of non-volatile memory |
| KR100719368B1 (ko) * | 2005-06-27 | 2007-05-17 | 삼성전자주식회사 | 플래시 메모리 장치의 적응적 프로그램 방법 및 장치 |
| US7457910B2 (en) | 2005-06-29 | 2008-11-25 | Sandisk Corproation | Method and system for managing partitions in a storage device |
| EP1746604B1 (en) * | 2005-07-22 | 2009-02-04 | STMicroelectronics S.r.l. | Method for accessing a multilevel nonvolatile memory device of the flash NAND type |
| US7230854B2 (en) * | 2005-08-01 | 2007-06-12 | Sandisk Corporation | Method for programming non-volatile memory with self-adjusting maximum program loop |
| US7023737B1 (en) * | 2005-08-01 | 2006-04-04 | Sandisk Corporation | System for programming non-volatile memory with self-adjusting maximum program loop |
| US7949845B2 (en) * | 2005-08-03 | 2011-05-24 | Sandisk Corporation | Indexing of file data in reprogrammable non-volatile memories that directly store data files |
| US7627733B2 (en) * | 2005-08-03 | 2009-12-01 | Sandisk Corporation | Method and system for dual mode access for storage devices |
| US7480766B2 (en) * | 2005-08-03 | 2009-01-20 | Sandisk Corporation | Interfacing systems operating through a logical address space and on a direct data file basis |
| US7558906B2 (en) | 2005-08-03 | 2009-07-07 | Sandisk Corporation | Methods of managing blocks in nonvolatile memory |
| US7409489B2 (en) | 2005-08-03 | 2008-08-05 | Sandisk Corporation | Scheduling of reclaim operations in non-volatile memory |
| US7669003B2 (en) * | 2005-08-03 | 2010-02-23 | Sandisk Corporation | Reprogrammable non-volatile memory systems with indexing of directly stored data files |
| US7552271B2 (en) | 2005-08-03 | 2009-06-23 | Sandisk Corporation | Nonvolatile memory with block management |
| US20070036007A1 (en) * | 2005-08-09 | 2007-02-15 | Saifun Semiconductors, Ltd. | Sticky bit buffer |
| US7170788B1 (en) | 2005-09-09 | 2007-01-30 | Sandisk Corporation | Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb |
| US7218552B1 (en) | 2005-09-09 | 2007-05-15 | Sandisk Corporation | Last-first mode and method for programming of non-volatile memory with reduced program disturb |
| KR100705220B1 (ko) * | 2005-09-15 | 2007-04-06 | 주식회사 하이닉스반도체 | 프로그램 속도를 증가시키기 위한 플래시 메모리 장치의소거 및 프로그램 방법 |
| US7529905B2 (en) * | 2005-10-13 | 2009-05-05 | Sandisk Corporation | Method of storing transformed units of data in a memory system having fixed sized storage blocks |
| US7814262B2 (en) * | 2005-10-13 | 2010-10-12 | Sandisk Corporation | Memory system storing transformed units of data in fixed sized storage blocks |
| US7681109B2 (en) * | 2005-10-13 | 2010-03-16 | Ramot At Tel Aviv University Ltd. | Method of error correction in MBC flash memory |
| US7286406B2 (en) * | 2005-10-14 | 2007-10-23 | Sandisk Corporation | Method for controlled programming of non-volatile memory exhibiting bit line coupling |
| US7206235B1 (en) | 2005-10-14 | 2007-04-17 | Sandisk Corporation | Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling |
| US7526715B2 (en) * | 2005-10-17 | 2009-04-28 | Ramot At Tel Aviv University Ltd. | Probabilistic error correction in multi-bit-per-cell flash memory |
| US7954037B2 (en) * | 2005-10-25 | 2011-05-31 | Sandisk Il Ltd | Method for recovering from errors in flash memory |
| US7631162B2 (en) | 2005-10-27 | 2009-12-08 | Sandisck Corporation | Non-volatile memory with adaptive handling of data writes |
| US7366022B2 (en) * | 2005-10-27 | 2008-04-29 | Sandisk Corporation | Apparatus for programming of multi-state non-volatile memory using smart verify |
| US7301817B2 (en) * | 2005-10-27 | 2007-11-27 | Sandisk Corporation | Method for programming of multi-state non-volatile memory using smart verify |
| JP4855474B2 (ja) * | 2005-10-27 | 2012-01-18 | サンディスク コーポレイション | スマート検証を利用してマルチステート不揮発性メモリをプログラミングする方法 |
| US7509471B2 (en) * | 2005-10-27 | 2009-03-24 | Sandisk Corporation | Methods for adaptively handling data writes in non-volatile memories |
| US7447066B2 (en) * | 2005-11-08 | 2008-11-04 | Sandisk Corporation | Memory with retargetable memory cell redundancy |
| US8683082B2 (en) * | 2005-11-14 | 2014-03-25 | Sandisk Technologies Inc. | Removable memory devices for displaying advertisement content on host systems using applications launched from removable memory devices |
| US8683081B2 (en) * | 2005-11-14 | 2014-03-25 | Sandisk Technologies Inc. | Methods for displaying advertisement content on host system using application launched from removable memory device |
| US7739078B2 (en) * | 2005-12-01 | 2010-06-15 | Sandisk Corporation | System for managing appliances |
| US7353073B2 (en) * | 2005-12-01 | 2008-04-01 | Sandisk Corporation | Method for managing appliances |
| KR100948200B1 (ko) | 2005-12-06 | 2010-03-17 | 샌디스크 코포레이션 | 비휘발성 저장 장치에서 판독 장애 저감 |
| US7349258B2 (en) * | 2005-12-06 | 2008-03-25 | Sandisk Corporation | Reducing read disturb for non-volatile storage |
| US7737483B2 (en) * | 2005-12-06 | 2010-06-15 | Sandisk Corporation | Low resistance void-free contacts |
| US7262994B2 (en) * | 2005-12-06 | 2007-08-28 | Sandisk Corporation | System for reducing read disturb for non-volatile storage |
| US7615448B2 (en) * | 2005-12-06 | 2009-11-10 | Sandisk Corporation | Method of forming low resistance void-free contacts |
| US7877540B2 (en) * | 2005-12-13 | 2011-01-25 | Sandisk Corporation | Logically-addressed file storage methods |
| US7355888B2 (en) * | 2005-12-19 | 2008-04-08 | Sandisk Corporation | Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages |
| US7355889B2 (en) * | 2005-12-19 | 2008-04-08 | Sandisk Corporation | Method for programming non-volatile memory with reduced program disturb using modified pass voltages |
| US7917949B2 (en) * | 2005-12-21 | 2011-03-29 | Sandisk Corporation | Voice controlled portable memory storage device |
| US20070143117A1 (en) * | 2005-12-21 | 2007-06-21 | Conley Kevin M | Voice controlled portable memory storage device |
| US7747837B2 (en) * | 2005-12-21 | 2010-06-29 | Sandisk Corporation | Method and system for accessing non-volatile storage devices |
| US20070156998A1 (en) * | 2005-12-21 | 2007-07-05 | Gorobets Sergey A | Methods for memory allocation in non-volatile memories with a directly mapped file storage system |
| US7495294B2 (en) * | 2005-12-21 | 2009-02-24 | Sandisk Corporation | Flash devices with shared word lines |
| US7655536B2 (en) * | 2005-12-21 | 2010-02-02 | Sandisk Corporation | Methods of forming flash devices with shared word lines |
| US20070143378A1 (en) * | 2005-12-21 | 2007-06-21 | Gorobets Sergey A | Non-volatile memories with adaptive file handling in a directly mapped file storage system |
| US20070143561A1 (en) * | 2005-12-21 | 2007-06-21 | Gorobets Sergey A | Methods for adaptive file data handling in non-volatile memories with a directly mapped file storage system |
| US20070143566A1 (en) * | 2005-12-21 | 2007-06-21 | Gorobets Sergey A | Non-volatile memories with data alignment in a directly mapped file storage system |
| US8161289B2 (en) * | 2005-12-21 | 2012-04-17 | SanDisk Technologies, Inc. | Voice controlled portable memory storage device |
| US7793068B2 (en) * | 2005-12-21 | 2010-09-07 | Sandisk Corporation | Dual mode access for non-volatile storage devices |
| US20070143567A1 (en) * | 2005-12-21 | 2007-06-21 | Gorobets Sergey A | Methods for data alignment in non-volatile memories with a directly mapped file storage system |
| US7769978B2 (en) * | 2005-12-21 | 2010-08-03 | Sandisk Corporation | Method and system for accessing non-volatile storage devices |
| US20070143111A1 (en) * | 2005-12-21 | 2007-06-21 | Conley Kevin M | Voice controlled portable memory storage device |
| US8484632B2 (en) * | 2005-12-22 | 2013-07-09 | Sandisk Technologies Inc. | System for program code execution with memory storage controller participation |
| US8479186B2 (en) * | 2005-12-22 | 2013-07-02 | Sandisk Technologies Inc. | Method for program code execution with memory storage controller participation |
| US7362615B2 (en) * | 2005-12-27 | 2008-04-22 | Sandisk Corporation | Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices |
| JP4864097B2 (ja) | 2005-12-27 | 2012-01-25 | サンディスク コーポレイション | ブースタープレートを備えたフラッシュメモリデバイス |
| US7436703B2 (en) * | 2005-12-27 | 2008-10-14 | Sandisk Corporation | Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices |
| US7365018B2 (en) * | 2005-12-28 | 2008-04-29 | Sandisk Corporation | Fabrication of semiconductor device for flash memory with increased select gate width |
| US7443726B2 (en) * | 2005-12-29 | 2008-10-28 | Sandisk Corporation | Systems for alternate row-based reading and writing for non-volatile memory |
| US7349260B2 (en) * | 2005-12-29 | 2008-03-25 | Sandisk Corporation | Alternate row-based reading and writing for non-volatile memory |
| US7352629B2 (en) * | 2005-12-29 | 2008-04-01 | Sandisk Corporation | Systems for continued verification in non-volatile memory write operations |
| US7307887B2 (en) * | 2005-12-29 | 2007-12-11 | Sandisk Corporation | Continued verification in non-volatile memory write operations |
| TW200727303A (en) * | 2006-01-08 | 2007-07-16 | Ememory Technology Inc | A method and memory capable of improving the endurance of memory |
| KR100683858B1 (ko) * | 2006-01-12 | 2007-02-15 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
| KR100673026B1 (ko) * | 2006-01-24 | 2007-01-24 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
| KR100841336B1 (ko) * | 2006-01-24 | 2008-06-26 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리를 구비한 메모리 시스템 |
| KR100684909B1 (ko) * | 2006-01-24 | 2007-02-22 | 삼성전자주식회사 | 읽기 에러를 방지할 수 있는 플래시 메모리 장치 |
| JP4157563B2 (ja) | 2006-01-31 | 2008-10-01 | 株式会社東芝 | 半導体集積回路装置 |
| KR100732631B1 (ko) * | 2006-02-01 | 2007-06-27 | 삼성전자주식회사 | 전하 손실로 인해 감소된 읽기 마진을 보상할 수 있는플래시 메모리 장치의 프로그램 방법 |
| KR100666223B1 (ko) * | 2006-02-22 | 2007-01-09 | 삼성전자주식회사 | 메모리셀 사이의 커플링 노이즈를 저감시키는 3-레벨불휘발성 반도체 메모리 장치 및 이에 대한 구동방법 |
| US7499319B2 (en) * | 2006-03-03 | 2009-03-03 | Sandisk Corporation | Read operation for non-volatile storage with compensation for coupling |
| US7436733B2 (en) * | 2006-03-03 | 2008-10-14 | Sandisk Corporation | System for performing read operation on non-volatile storage with compensation for coupling |
| ATE494614T1 (de) | 2006-03-03 | 2011-01-15 | Sandisk Corp | Leseoperation für nichtflüchtige speicherung mit floating-gate-kopplungskompensation |
| US8848442B2 (en) * | 2006-03-06 | 2014-09-30 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
| US7388781B2 (en) * | 2006-03-06 | 2008-06-17 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
| US7327608B2 (en) * | 2006-03-28 | 2008-02-05 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in programming method |
| US7330373B2 (en) * | 2006-03-28 | 2008-02-12 | Sandisk Corporation | Program time adjustment as function of program voltage for improved programming speed in memory system |
| US7428165B2 (en) * | 2006-03-30 | 2008-09-23 | Sandisk Corporation | Self-boosting method with suppression of high lateral electric fields |
| US7511995B2 (en) * | 2006-03-30 | 2009-03-31 | Sandisk Corporation | Self-boosting system with suppression of high lateral electric fields |
| EP1840901B1 (en) * | 2006-03-31 | 2010-04-28 | STMicroelectronics Srl | Method for programming a memory device suitable to minimize floating gate couplings and memory device |
| US7515463B2 (en) | 2006-04-12 | 2009-04-07 | Sandisk Corporation | Reducing the impact of program disturb during read |
| KR101012130B1 (ko) | 2006-04-12 | 2011-02-07 | 샌디스크 코포레이션 | 프로그램 혼란의 영향을 감소시키는 방법 |
| US7426137B2 (en) | 2006-04-12 | 2008-09-16 | Sandisk Corporation | Apparatus for reducing the impact of program disturb during read |
| US7436713B2 (en) | 2006-04-12 | 2008-10-14 | Sandisk Corporation | Reducing the impact of program disturb |
| US7499326B2 (en) * | 2006-04-12 | 2009-03-03 | Sandisk Corporation | Apparatus for reducing the impact of program disturb |
| US7467253B2 (en) * | 2006-04-13 | 2008-12-16 | Sandisk Corporation | Cycle count storage systems |
| US7451264B2 (en) * | 2006-04-13 | 2008-11-11 | Sandisk Corporation | Cycle count storage methods |
| US7440322B2 (en) * | 2006-04-20 | 2008-10-21 | Sandisk Corporation | Method and system for flash memory devices |
| US7516261B2 (en) * | 2006-04-21 | 2009-04-07 | Sandisk Corporation | Method for U3 adapter |
| US7447821B2 (en) * | 2006-04-21 | 2008-11-04 | Sandisk Corporation | U3 adapter |
| US7701779B2 (en) * | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| US7436709B2 (en) * | 2006-05-05 | 2008-10-14 | Sandisk Corporation | NAND flash memory with boosting |
| US7286408B1 (en) | 2006-05-05 | 2007-10-23 | Sandisk Corporation | Boosting methods for NAND flash memory |
| CN103280239B (zh) | 2006-05-12 | 2016-04-06 | 苹果公司 | 存储设备中的失真估计和消除 |
| WO2007132456A2 (en) * | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
| US8156403B2 (en) * | 2006-05-12 | 2012-04-10 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
| WO2007132452A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies | Reducing programming error in memory devices |
| US20070266296A1 (en) * | 2006-05-15 | 2007-11-15 | Conley Kevin M | Nonvolatile Memory with Convolutional Coding |
| US7840875B2 (en) * | 2006-05-15 | 2010-11-23 | Sandisk Corporation | Convolutional coding methods for nonvolatile memory |
| KR100778082B1 (ko) * | 2006-05-18 | 2007-11-21 | 삼성전자주식회사 | 단일의 래치 구조를 갖는 멀티-비트 플래시 메모리 장치,그것의 프로그램 방법, 그리고 그것을 포함하는 메모리카드 |
| US7876613B2 (en) | 2006-05-18 | 2011-01-25 | Samsung Electronics Co., Ltd. | Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards |
| US7583545B2 (en) * | 2006-05-21 | 2009-09-01 | Sandisk Il Ltd | Method of storing data in a multi-bit-cell flash memory |
| US7870736B2 (en) * | 2006-06-01 | 2011-01-18 | Virginia Tech Intellectual Properties, Inc. | Premixing injector for gas turbine engines |
| US7440331B2 (en) * | 2006-06-01 | 2008-10-21 | Sandisk Corporation | Verify operation for non-volatile storage using different voltages |
| US7457163B2 (en) * | 2006-06-01 | 2008-11-25 | Sandisk Corporation | System for verifying non-volatile storage using different voltages |
| US7310272B1 (en) * | 2006-06-02 | 2007-12-18 | Sandisk Corporation | System for performing data pattern sensitivity compensation using different voltage |
| US7450421B2 (en) * | 2006-06-02 | 2008-11-11 | Sandisk Corporation | Data pattern sensitivity compensation using different voltage |
| US7952922B2 (en) * | 2006-06-06 | 2011-05-31 | Micron Technology, Inc. | Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect |
| KR100733952B1 (ko) | 2006-06-12 | 2007-06-29 | 삼성전자주식회사 | 플래그 셀들 사이의 커플링을 최소화시킬 수 있는멀티-비트 플래시 메모리 장치 및 그것의 프로그램 방법 |
| US7372715B2 (en) * | 2006-06-14 | 2008-05-13 | Micron Technology, Inc. | Architecture and method for NAND flash memory |
| US7391650B2 (en) * | 2006-06-16 | 2008-06-24 | Sandisk Corporation | Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
| US7342831B2 (en) * | 2006-06-16 | 2008-03-11 | Sandisk Corporation | System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates |
| US7492633B2 (en) * | 2006-06-19 | 2009-02-17 | Sandisk Corporation | System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines |
| US7606084B2 (en) * | 2006-06-19 | 2009-10-20 | Sandisk Corporation | Programming differently sized margins and sensing with compensations at select states for improved read operations in non-volatile memory |
| US7352628B2 (en) * | 2006-06-19 | 2008-04-01 | Sandisk Corporation | Systems for programming differently sized margins and sensing with compensations at select states for improved read operations in a non-volatile memory |
| US7349261B2 (en) * | 2006-06-19 | 2008-03-25 | Sandisk Corporation | Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines |
| US7489549B2 (en) * | 2006-06-22 | 2009-02-10 | Sandisk Corporation | System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| WO2007149677A2 (en) * | 2006-06-22 | 2007-12-27 | Sandisk Corporation | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| US7486561B2 (en) * | 2006-06-22 | 2009-02-03 | Sandisk Corporation | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| US20070297247A1 (en) * | 2006-06-26 | 2007-12-27 | Gerrit Jan Hemink | Method for programming non-volatile memory using variable amplitude programming pulses |
| US7304893B1 (en) | 2006-06-30 | 2007-12-04 | Sandisk Corporation | Method of partial page fail bit detection in flash memory devices |
| US7355892B2 (en) * | 2006-06-30 | 2008-04-08 | Sandisk Corporation | Partial page fail bit detection in flash memory devices |
| US7533328B2 (en) * | 2006-07-04 | 2009-05-12 | Sandisk Il, Ltd. | Method of error correction in a multi-bit-per-cell flash memory |
| US7495953B2 (en) * | 2006-07-20 | 2009-02-24 | Sandisk Corporation | System for configuring compensation |
| KR101048834B1 (ko) * | 2006-07-20 | 2011-07-13 | 샌디스크 코포레이션 | 프로그래밍 중의 커플링 보상 |
| US7506113B2 (en) * | 2006-07-20 | 2009-03-17 | Sandisk Corporation | Method for configuring compensation |
| US7400535B2 (en) * | 2006-07-20 | 2008-07-15 | Sandisk Corporation | System that compensates for coupling during programming |
| US7885119B2 (en) | 2006-07-20 | 2011-02-08 | Sandisk Corporation | Compensating for coupling during programming |
| US7894269B2 (en) * | 2006-07-20 | 2011-02-22 | Sandisk Corporation | Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells |
| US7522454B2 (en) * | 2006-07-20 | 2009-04-21 | Sandisk Corporation | Compensating for coupling based on sensing a neighbor using coupling |
| US7443729B2 (en) * | 2006-07-20 | 2008-10-28 | Sandisk Corporation | System that compensates for coupling based on sensing a neighbor using coupling |
| WO2008011441A2 (en) * | 2006-07-20 | 2008-01-24 | Sandisk Corporation | Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory |
| US7716415B2 (en) | 2006-08-01 | 2010-05-11 | Sandisk Il Ltd. | Method of avoiding errors in flash memory |
| JP5047288B2 (ja) | 2006-08-05 | 2012-10-10 | ベンホフ ゲーエムベーハー エルエルシー | 固体記憶素子及び方法 |
| US7474560B2 (en) | 2006-08-21 | 2009-01-06 | Micron Technology, Inc. | Non-volatile memory with both single and multiple level cells |
| JP2008052808A (ja) | 2006-08-24 | 2008-03-06 | Toshiba Corp | 不揮発性半導体記憶装置及びそのデータの読出方法並びにメモリカード |
| KR100919156B1 (ko) * | 2006-08-24 | 2009-09-28 | 삼성전자주식회사 | 멀티-비트 플래시 메모리 장치 및 그것의 프로그램 방법 |
| US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
| KR100805839B1 (ko) | 2006-08-29 | 2008-02-21 | 삼성전자주식회사 | 고전압 발생기를 공유하는 플래시 메모리 장치 |
| US7684243B2 (en) | 2006-08-31 | 2010-03-23 | Micron Technology, Inc. | Reducing read failure in a memory device |
| KR100771883B1 (ko) | 2006-09-06 | 2007-11-01 | 삼성전자주식회사 | 멀티-레벨 불휘발성 메모리 장치 및 프로그램 방법 |
| US7440326B2 (en) * | 2006-09-06 | 2008-10-21 | Sandisk Corporation | Programming non-volatile memory with improved boosting |
| US7593259B2 (en) * | 2006-09-13 | 2009-09-22 | Mosaid Technologies Incorporated | Flash multi-level threshold distribution scheme |
| KR100753156B1 (ko) * | 2006-09-13 | 2007-08-30 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 메모리 셀 어레이 |
| US7646054B2 (en) * | 2006-09-19 | 2010-01-12 | Sandisk Corporation | Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
| US7696044B2 (en) * | 2006-09-19 | 2010-04-13 | Sandisk Corporation | Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
| KR100879387B1 (ko) * | 2006-09-22 | 2009-01-20 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 방법 |
| US7961511B2 (en) * | 2006-09-26 | 2011-06-14 | Sandisk Corporation | Hybrid programming methods and systems for non-volatile memory storage elements |
| US7886204B2 (en) * | 2006-09-27 | 2011-02-08 | Sandisk Corporation | Methods of cell population distribution assisted read margining |
| US8184478B2 (en) * | 2006-09-27 | 2012-05-22 | Sandisk Technologies Inc. | Apparatus with reduced program disturb in non-volatile storage |
| US7716538B2 (en) * | 2006-09-27 | 2010-05-11 | Sandisk Corporation | Memory with cell population distribution assisted read margining |
| US8189378B2 (en) * | 2006-09-27 | 2012-05-29 | Sandisk Technologies Inc. | Reducing program disturb in non-volatile storage |
| US8773934B2 (en) | 2006-09-27 | 2014-07-08 | Silicon Storage Technology, Inc. | Power line compensation for flash memory sense amplifiers |
| US7805663B2 (en) * | 2006-09-28 | 2010-09-28 | Sandisk Corporation | Methods of adapting operation of nonvolatile memory |
| US7705387B2 (en) * | 2006-09-28 | 2010-04-27 | Sandisk Corporation | Non-volatile memory with local boosting control implant |
| US7977186B2 (en) * | 2006-09-28 | 2011-07-12 | Sandisk Corporation | Providing local boosting control implant for non-volatile memory |
| US20080092015A1 (en) * | 2006-09-28 | 2008-04-17 | Yigal Brandman | Nonvolatile memory with adaptive operation |
| US7818653B2 (en) * | 2006-09-28 | 2010-10-19 | Sandisk Corporation | Methods of soft-input soft-output decoding for nonvolatile memory |
| US7904783B2 (en) * | 2006-09-28 | 2011-03-08 | Sandisk Corporation | Soft-input soft-output decoder for nonvolatile memory |
| US7656735B2 (en) | 2006-09-29 | 2010-02-02 | Sandisk Corporation | Dual voltage flash memory methods |
| US7675802B2 (en) | 2006-09-29 | 2010-03-09 | Sandisk Corporation | Dual voltage flash memory card |
| US7447076B2 (en) * | 2006-09-29 | 2008-11-04 | Sandisk Corporation | Systems for reverse reading in non-volatile memory with compensation for coupling |
| US7684247B2 (en) * | 2006-09-29 | 2010-03-23 | Sandisk Corporation | Reverse reading in non-volatile memory with compensation for coupling |
| KR100773742B1 (ko) | 2006-09-30 | 2007-11-09 | 삼성전자주식회사 | 저장 소자들 사이의 커플링 효과를 감소시킬 수 있는비휘발성 메모리 장치와 그 방법 |
| KR100782329B1 (ko) | 2006-10-02 | 2007-12-06 | 삼성전자주식회사 | 메모리 셀 어레이에 분산 배열된 플래그 셀 어레이를구비하는 비휘발성 메모리 장치 및 상기 메모리 장치의구동 방법 |
| US7474561B2 (en) * | 2006-10-10 | 2009-01-06 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
| WO2008045805A1 (en) * | 2006-10-10 | 2008-04-17 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
| US7450426B2 (en) * | 2006-10-10 | 2008-11-11 | Sandisk Corporation | Systems utilizing variable program voltage increment values in non-volatile memory program operations |
| US20080091871A1 (en) * | 2006-10-12 | 2008-04-17 | Alan David Bennett | Non-volatile memory with worst-case control data management |
| JP4990978B2 (ja) | 2006-10-13 | 2012-08-01 | サンディスク コーポレイション | 不揮発性記憶素子における部分的な消去と消去の検証 |
| US7372748B2 (en) * | 2006-10-16 | 2008-05-13 | Sandisk Corporation | Voltage regulator in a non-volatile memory device |
| US7616490B2 (en) * | 2006-10-17 | 2009-11-10 | Sandisk Corporation | Programming non-volatile memory with dual voltage select gate structure |
| US7586157B2 (en) * | 2006-10-17 | 2009-09-08 | Sandisk Corporation | Non-volatile memory with dual voltage select gate structure |
| US7691710B2 (en) * | 2006-10-17 | 2010-04-06 | Sandisk Corporation | Fabricating non-volatile memory with dual voltage select gate structure |
| US7975192B2 (en) | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
| WO2008053473A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Memory cell readout using successive approximation |
| US7596031B2 (en) * | 2006-10-30 | 2009-09-29 | Sandisk Corporation | Faster programming of highest multi-level state for non-volatile memory |
| KR101130332B1 (ko) * | 2006-10-30 | 2012-03-26 | 샌디스크 코포레이션 | 비휘발성 메모리에 대한 최상위 다중-레벨 상태의 고속 프로그래밍 |
| US7426139B2 (en) * | 2006-11-02 | 2008-09-16 | Macronix International Co., Ltd. | Dynamic program and read adjustment for multi-level cell memory array |
| US7468911B2 (en) * | 2006-11-02 | 2008-12-23 | Sandisk Corporation | Non-volatile memory using multiple boosting modes for reduced program disturb |
| US7440323B2 (en) * | 2006-11-02 | 2008-10-21 | Sandisk Corporation | Reducing program disturb in non-volatile memory using multiple boosting modes |
| US7904788B2 (en) * | 2006-11-03 | 2011-03-08 | Sandisk Corporation | Methods of varying read threshold voltage in nonvolatile memory |
| US7558109B2 (en) * | 2006-11-03 | 2009-07-07 | Sandisk Corporation | Nonvolatile memory with variable read threshold |
| US8001441B2 (en) * | 2006-11-03 | 2011-08-16 | Sandisk Technologies Inc. | Nonvolatile memory with modulated error correction coding |
| US7904780B2 (en) * | 2006-11-03 | 2011-03-08 | Sandisk Corporation | Methods of modulating error correction coding |
| US7696035B2 (en) * | 2006-11-13 | 2010-04-13 | Sandisk Corporation | Method for fabricating non-volatile memory with boost structures |
| US7508710B2 (en) * | 2006-11-13 | 2009-03-24 | Sandisk Corporation | Operating non-volatile memory with boost structures |
| US7508703B2 (en) * | 2006-11-13 | 2009-03-24 | Sandisk Corporation | Non-volatile memory with boost structures |
| KR100851853B1 (ko) * | 2006-11-22 | 2008-08-13 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 및 프로그램 검증방법 |
| US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
| WO2008068747A2 (en) * | 2006-12-03 | 2008-06-12 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
| US7706182B2 (en) * | 2006-12-03 | 2010-04-27 | Anobit Technologies Ltd. | Adaptive programming of analog memory cells using statistical characteristics |
| US7474565B2 (en) * | 2006-12-11 | 2009-01-06 | Macronix International Co., Ltd. | Programming scheme for non-volatile flash memory |
| US7623386B2 (en) * | 2006-12-12 | 2009-11-24 | Sandisk Corporation | Reducing program disturb in non-volatile storage using early source-side boosting |
| US7623387B2 (en) * | 2006-12-12 | 2009-11-24 | Sandisk Corporation | Non-volatile storage with early source-side boosting for reducing program disturb |
| US8504890B2 (en) * | 2006-12-17 | 2013-08-06 | Ramot At Tel Aviv University Ltd. | Scheduling for LDPC decoding |
| US7900102B2 (en) * | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
| US7593263B2 (en) * | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
| US7800161B2 (en) * | 2006-12-21 | 2010-09-21 | Sandisk Corporation | Flash NAND memory cell array with charge storage elements positioned in trenches |
| US7642160B2 (en) * | 2006-12-21 | 2010-01-05 | Sandisk Corporation | Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches |
| US8370561B2 (en) * | 2006-12-24 | 2013-02-05 | Sandisk Il Ltd. | Randomizing for suppressing errors in a flash memory |
| US8127200B2 (en) * | 2006-12-24 | 2012-02-28 | Sandisk Il Ltd. | Flash memory device and system with randomizing for suppressing errors |
| US7917686B2 (en) * | 2006-12-26 | 2011-03-29 | Sandisk Corporation | Host system with direct data file interface configurability |
| US20080155175A1 (en) * | 2006-12-26 | 2008-06-26 | Sinclair Alan W | Host System That Manages a LBA Interface With Flash Memory |
| US8046522B2 (en) * | 2006-12-26 | 2011-10-25 | SanDisk Technologies, Inc. | Use of a direct data file system with a continuous logical address space interface and control of file address storage in logical blocks |
| US7739444B2 (en) | 2006-12-26 | 2010-06-15 | Sandisk Corporation | System using a direct data file system with a continuous logical address space interface |
| US8209461B2 (en) | 2006-12-26 | 2012-06-26 | Sandisk Technologies Inc. | Configuration of host LBA interface with flash memory |
| US8166267B2 (en) * | 2006-12-26 | 2012-04-24 | Sandisk Technologies Inc. | Managing a LBA interface in a direct data file memory system |
| US7570520B2 (en) * | 2006-12-27 | 2009-08-04 | Sandisk Corporation | Non-volatile storage system with initial programming voltage based on trial |
| US7551482B2 (en) * | 2006-12-27 | 2009-06-23 | Sandisk Corporation | Method for programming with initial programming voltage based on trial |
| US7539052B2 (en) * | 2006-12-28 | 2009-05-26 | Micron Technology, Inc. | Non-volatile multilevel memory cell programming |
| KR100816155B1 (ko) * | 2006-12-28 | 2008-03-21 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 멀티레벨 셀 프로그램 방법 |
| US7616506B2 (en) | 2006-12-28 | 2009-11-10 | Sandisk Corporation | Systems for complete word line look ahead with efficient data latch assignment in non-volatile memory read operations |
| US7616505B2 (en) | 2006-12-28 | 2009-11-10 | Sandisk Corporation | Complete word line look ahead with efficient data latch assignment in non-volatile memory read operations |
| US7701765B2 (en) * | 2006-12-28 | 2010-04-20 | Micron Technology, Inc. | Non-volatile multilevel memory cell programming |
| US7440324B2 (en) * | 2006-12-29 | 2008-10-21 | Sandisk Corporation | Apparatus with alternating read mode |
| US7489548B2 (en) * | 2006-12-29 | 2009-02-10 | Sandisk Corporation | NAND flash memory cell array with adaptive memory state partitioning |
| US7890723B2 (en) * | 2006-12-29 | 2011-02-15 | Sandisk Corporation | Method for code execution |
| US7450430B2 (en) * | 2006-12-29 | 2008-11-11 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
| US7590002B2 (en) * | 2006-12-29 | 2009-09-15 | Sandisk Corporation | Resistance sensing and compensation for non-volatile storage |
| US7606070B2 (en) * | 2006-12-29 | 2009-10-20 | Sandisk Corporation | Systems for margined neighbor reading for non-volatile memory read operations including coupling compensation |
| US7489547B2 (en) * | 2006-12-29 | 2009-02-10 | Sandisk Corporation | Method of NAND flash memory cell array with adaptive memory state partitioning |
| US7433241B2 (en) * | 2006-12-29 | 2008-10-07 | Sandisk Corporation | Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
| US7616498B2 (en) * | 2006-12-29 | 2009-11-10 | Sandisk Corporation | Non-volatile storage system with resistance sensing and compensation |
| US7890724B2 (en) * | 2006-12-29 | 2011-02-15 | Sandisk Corporation | System for code execution |
| US7495962B2 (en) * | 2006-12-29 | 2009-02-24 | Sandisk Corporation | Alternating read mode |
| US7463531B2 (en) * | 2006-12-29 | 2008-12-09 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages |
| US7518923B2 (en) * | 2006-12-29 | 2009-04-14 | Sandisk Corporation | Margined neighbor reading for non-volatile memory read operations including coupling compensation |
| US7468918B2 (en) * | 2006-12-29 | 2008-12-23 | Sandisk Corporation | Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data |
| US7554853B2 (en) * | 2006-12-30 | 2009-06-30 | Sandisk Corporation | Non-volatile storage with bias based on selective word line |
| US7468920B2 (en) | 2006-12-30 | 2008-12-23 | Sandisk Corporation | Applying adaptive body bias to non-volatile storage |
| US7468919B2 (en) * | 2006-12-30 | 2008-12-23 | Sandisk Corporation | Biasing non-volatile storage based on selected word line |
| US7525843B2 (en) * | 2006-12-30 | 2009-04-28 | Sandisk Corporation | Non-volatile storage with adaptive body bias |
| US7583535B2 (en) * | 2006-12-30 | 2009-09-01 | Sandisk Corporation | Biasing non-volatile storage to compensate for temperature variations |
| US7583539B2 (en) * | 2006-12-30 | 2009-09-01 | Sandisk Corporation | Non-volatile storage with bias for temperature compensation |
| KR100816161B1 (ko) * | 2007-01-23 | 2008-03-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 프로그램 방법 |
| US8151166B2 (en) * | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
| US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
| US7679965B2 (en) * | 2007-01-31 | 2010-03-16 | Sandisk Il Ltd | Flash memory with improved programming precision |
| US7397705B1 (en) * | 2007-02-01 | 2008-07-08 | Macronix International Co., Ltd. | Method for programming multi-level cell memory array |
| JP5113195B2 (ja) | 2007-02-20 | 2013-01-09 | サンディスク テクノロジーズ インコーポレイテッド | 閾値電圧区分に基づく動的検証 |
| US7564715B2 (en) * | 2007-02-20 | 2009-07-21 | Sandisk Corporation | Variable initial program voltage magnitude for non-volatile storage |
| WO2008111058A2 (en) * | 2007-03-12 | 2008-09-18 | Anobit Technologies Ltd. | Adaptive estimation of memory cell read thresholds |
| US7535764B2 (en) * | 2007-03-21 | 2009-05-19 | Sandisk Corporation | Adjusting resistance of non-volatile memory using dummy memory cells |
| US7477547B2 (en) * | 2007-03-28 | 2009-01-13 | Sandisk Corporation | Flash memory refresh techniques triggered by controlled scrub data reads |
| US7573773B2 (en) * | 2007-03-28 | 2009-08-11 | Sandisk Corporation | Flash memory with data refresh triggered by controlled scrub data reads |
| US7904793B2 (en) * | 2007-03-29 | 2011-03-08 | Sandisk Corporation | Method for decoding data in non-volatile storage using reliability metrics based on multiple reads |
| WO2008121553A1 (en) * | 2007-03-29 | 2008-10-09 | Sandisk Corporation | Non-volatile storage with decoding of data using reliability metrics based on multiple reads |
| US7797480B2 (en) * | 2007-03-29 | 2010-09-14 | Sandisk Corporation | Method for reading non-volatile storage using pre-conditioning waveforms and modified reliability metrics |
| US7745285B2 (en) | 2007-03-30 | 2010-06-29 | Sandisk Corporation | Methods of forming and operating NAND memory with side-tunneling |
| US7447079B2 (en) * | 2007-04-05 | 2008-11-04 | Sandisk Corporation | Method for sensing negative threshold voltages in non-volatile storage using current sensing |
| US7606076B2 (en) * | 2007-04-05 | 2009-10-20 | Sandisk Corporation | Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise |
| US8001320B2 (en) * | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
| US7876621B2 (en) | 2007-04-23 | 2011-01-25 | Sandisk Il Ltd. | Adaptive dynamic reading of flash memories |
| US7606072B2 (en) * | 2007-04-24 | 2009-10-20 | Sandisk Corporation | Non-volatile storage with compensation for source voltage drop |
| US7606071B2 (en) * | 2007-04-24 | 2009-10-20 | Sandisk Corporation | Compensating source voltage drop in non-volatile storage |
| US7440327B1 (en) | 2007-04-25 | 2008-10-21 | Sandisk Corporation | Non-volatile storage with reduced power consumption during read operations |
| US7606079B2 (en) * | 2007-04-25 | 2009-10-20 | Sandisk Corporation | Reducing power consumption during read operations in non-volatile storage |
| US7656709B2 (en) | 2007-05-03 | 2010-02-02 | Micron Technology, Inc. | NAND step up voltage switching method |
| US7577029B2 (en) * | 2007-05-04 | 2009-08-18 | Mosaid Technologies Incorporated | Multi-level cell access buffer with dual function |
| US7460404B1 (en) * | 2007-05-07 | 2008-12-02 | Sandisk Corporation | Boosting for non-volatile storage using channel isolation switching |
| US7463522B2 (en) * | 2007-05-07 | 2008-12-09 | Sandisk Corporation | Non-volatile storage with boosting using channel isolation switching |
| US7577026B2 (en) * | 2007-05-07 | 2009-08-18 | Sandisk Corporation | Source and drain side early boosting using local self boosting for non-volatile storage |
| KR100890016B1 (ko) * | 2007-05-10 | 2009-03-25 | 삼성전자주식회사 | 비휘발성 메모리 장치, 그것을 포함하는 메모리 시스템 및그것의 프로그램 방법 |
| US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
| US8234545B2 (en) * | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
| US8073648B2 (en) * | 2007-05-14 | 2011-12-06 | Sandisk Il Ltd. | Measuring threshold voltage distribution in memory using an aggregate characteristic |
| US20080294814A1 (en) * | 2007-05-24 | 2008-11-27 | Sergey Anatolievich Gorobets | Flash Memory System with Management of Housekeeping Operations |
| US20080294813A1 (en) * | 2007-05-24 | 2008-11-27 | Sergey Anatolievich Gorobets | Managing Housekeeping Operations in Flash Memory |
| US20080307156A1 (en) * | 2007-06-08 | 2008-12-11 | Sinclair Alan W | System For Interfacing A Host Operating Through A Logical Address Space With A Direct File Storage Medium |
| US8239639B2 (en) * | 2007-06-08 | 2012-08-07 | Sandisk Technologies Inc. | Method and apparatus for providing data type and host file information to a mass storage system |
| US8713283B2 (en) * | 2007-06-08 | 2014-04-29 | Sandisk Technologies Inc. | Method of interfacing a host operating through a logical address space with a direct file storage medium |
| US8429352B2 (en) * | 2007-06-08 | 2013-04-23 | Sandisk Technologies Inc. | Method and system for memory block flushing |
| KR100892583B1 (ko) | 2007-06-08 | 2009-04-08 | 삼성전자주식회사 | 커플링을 고려한 메모리 셀의 데이터 프로그램 장치 및 그방법 |
| US7936599B2 (en) * | 2007-06-15 | 2011-05-03 | Micron Technology, Inc. | Coarse and fine programming in a solid state memory |
| US7630252B2 (en) * | 2007-06-25 | 2009-12-08 | Sandisk Corporation | Systems for programming multilevel cell nonvolatile memory |
| US7719889B2 (en) | 2007-06-25 | 2010-05-18 | Sandisk Corporation | Methods of programming multilevel cell nonvolatile memory |
| KR100888847B1 (ko) * | 2007-06-28 | 2009-03-17 | 삼성전자주식회사 | 불휘발성 반도체 메모리 장치 및 그것의 프로그램 방법 |
| US7471567B1 (en) | 2007-06-29 | 2008-12-30 | Sandisk Corporation | Method for source bias all bit line sensing in non-volatile storage |
| US7545678B2 (en) * | 2007-06-29 | 2009-06-09 | Sandisk Corporation | Non-volatile storage with source bias all bit line sensing |
| US7508715B2 (en) * | 2007-07-03 | 2009-03-24 | Sandisk Corporation | Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing |
| US7599224B2 (en) * | 2007-07-03 | 2009-10-06 | Sandisk Corporation | Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing |
| US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
| US7898885B2 (en) * | 2007-07-19 | 2011-03-01 | Micron Technology, Inc. | Analog sensing of memory cells in a solid state memory device |
| US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
| KR100908560B1 (ko) * | 2007-08-06 | 2009-07-21 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 프로그램 방법 |
| KR101425958B1 (ko) * | 2007-09-06 | 2014-08-04 | 삼성전자주식회사 | 멀티-비트 데이터를 저장하는 메모리 시스템 및 그것의읽기 방법 |
| US7818493B2 (en) * | 2007-09-07 | 2010-10-19 | Sandisk Corporation | Adaptive block list management |
| US8151034B2 (en) * | 2007-09-12 | 2012-04-03 | Sandisk Technologies Inc. | Write abort and erase abort handling |
| US7652929B2 (en) * | 2007-09-17 | 2010-01-26 | Sandisk Corporation | Non-volatile memory and method for biasing adjacent word line for verify during programming |
| US8174905B2 (en) * | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
| US7751237B2 (en) * | 2007-09-25 | 2010-07-06 | Sandisk Il, Ltd. | Post-facto correction for cross coupling in a flash memory |
| US7577034B2 (en) * | 2007-09-26 | 2009-08-18 | Sandisk Corporation | Reducing programming voltage differential nonlinearity in non-volatile storage |
| US8026170B2 (en) * | 2007-09-26 | 2011-09-27 | Sandisk Technologies Inc. | Method of forming a single-layer metal conductors with multiple thicknesses |
| US7978520B2 (en) | 2007-09-27 | 2011-07-12 | Sandisk Corporation | Compensation of non-volatile memory chip non-idealities by program pulse adjustment |
| US20090088876A1 (en) * | 2007-09-28 | 2009-04-02 | Conley Kevin M | Portable, digital media player and associated methods |
| US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
| KR101403429B1 (ko) * | 2007-10-09 | 2014-06-03 | 삼성전자주식회사 | 멀티 비트 프로그래밍 장치 및 방법 |
| US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
| US8068360B2 (en) * | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
| US8527819B2 (en) * | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
| US7668012B2 (en) * | 2007-10-31 | 2010-02-23 | Micron Technology, Inc. | Memory cell programming |
| US7742335B2 (en) | 2007-10-31 | 2010-06-22 | Micron Technology, Inc. | Non-volatile multilevel memory cells |
| US7848142B2 (en) | 2007-10-31 | 2010-12-07 | Micron Technology, Inc. | Fractional bits in memory cells |
| WO2009063450A2 (en) * | 2007-11-13 | 2009-05-22 | Anobit Technologies | Optimized selection of memory units in multi-unit memory devices |
| US8296498B2 (en) * | 2007-11-13 | 2012-10-23 | Sandisk Technologies Inc. | Method and system for virtual fast access non-volatile RAM |
| US8565019B2 (en) * | 2007-11-20 | 2013-10-22 | Kabushiki Kaisha Toshiba | Method for controlling threshold value in nonvolatile semiconductor memory device |
| US7613045B2 (en) * | 2007-11-26 | 2009-11-03 | Sandisk Il, Ltd. | Operation sequence and commands for measuring threshold voltage distribution in memory |
| US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
| US8209588B2 (en) * | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
| US7602639B2 (en) * | 2007-12-14 | 2009-10-13 | Spansion Llc | Reading electronic memory utilizing relationships between cell state distributions |
| US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
| US8880483B2 (en) * | 2007-12-21 | 2014-11-04 | Sandisk Technologies Inc. | System and method for implementing extensions to intelligently manage resources of a mass storage system |
| US8443260B2 (en) * | 2007-12-27 | 2013-05-14 | Sandisk Il Ltd. | Error correction in copy back memory operations |
| US8085586B2 (en) * | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
| US7813169B2 (en) | 2008-01-18 | 2010-10-12 | Qimonda Flash Gmbh | Integrated circuit and method to operate an integrated circuit |
| KR101391361B1 (ko) * | 2008-01-28 | 2014-05-07 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 소거 방법 |
| US7808833B2 (en) * | 2008-01-28 | 2010-10-05 | Qimonda Flash Gmbh | Method of operating an integrated circuit, integrated circuit and method to determine an operating point |
| US8156398B2 (en) * | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
| US7924587B2 (en) * | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
| US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
| KR101448851B1 (ko) * | 2008-02-26 | 2014-10-13 | 삼성전자주식회사 | 비휘발성 메모리 장치에서의 프로그래밍 방법 |
| US8230300B2 (en) * | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
| US8724381B2 (en) | 2008-03-11 | 2014-05-13 | Agere Systems Llc | Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding |
| US8059457B2 (en) * | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
| US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
| US20090271562A1 (en) * | 2008-04-25 | 2009-10-29 | Sinclair Alan W | Method and system for storage address re-mapping for a multi-bank memory device |
| CA2629960C (en) * | 2008-04-28 | 2009-12-08 | Westport Power Inc. | Apparatus and method for improving the accuracy of measurements taken with a capacitance-type sensor |
| US7808836B2 (en) * | 2008-04-29 | 2010-10-05 | Sandisk Il Ltd. | Non-volatile memory with adaptive setting of state voltage levels |
| US7808819B2 (en) * | 2008-04-29 | 2010-10-05 | Sandisk Il Ltd. | Method for adaptive setting of state voltage levels in non-volatile memory |
| US9594679B2 (en) * | 2008-05-01 | 2017-03-14 | Sandisk Il Ltd. | Flash cache flushing method and system |
| US8051240B2 (en) * | 2008-05-09 | 2011-11-01 | Sandisk Technologies Inc. | Compensating non-volatile storage using different pass voltages during program-verify and read |
| KR101378602B1 (ko) * | 2008-05-13 | 2014-03-25 | 삼성전자주식회사 | 메모리 장치 및 메모리 프로그래밍 방법 |
| US20090287893A1 (en) * | 2008-05-16 | 2009-11-19 | Skymedi Corporation | Method for managing memory |
| US7719902B2 (en) * | 2008-05-23 | 2010-05-18 | Sandisk Corporation | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage |
| US7952928B2 (en) * | 2008-05-27 | 2011-05-31 | Sandisk Il Ltd. | Increasing read throughput in non-volatile memory |
| CN102089827B (zh) * | 2008-06-12 | 2017-05-17 | 桑迪士克科技有限责任公司 | 非易失性存储器和关联多遍编程的方法 |
| US7813172B2 (en) | 2008-06-12 | 2010-10-12 | Sandisk Corporation | Nonvolatile memory with correlated multiple pass programming |
| US7848144B2 (en) * | 2008-06-16 | 2010-12-07 | Sandisk Corporation | Reverse order page writing in flash memories |
| JP2009301679A (ja) * | 2008-06-17 | 2009-12-24 | Vantel Corp | 不揮発性半導体記憶装置とその書き込み方法 |
| US7751250B2 (en) * | 2008-06-27 | 2010-07-06 | Sandisk Corporation | Memory device with power noise minimization during sensing |
| US7751249B2 (en) * | 2008-06-27 | 2010-07-06 | Sandisk Corporation | Minimizing power noise during sensing in memory device |
| US7800956B2 (en) * | 2008-06-27 | 2010-09-21 | Sandisk Corporation | Programming algorithm to reduce disturb with minimal extra time penalty |
| US8014209B2 (en) * | 2008-07-02 | 2011-09-06 | Sandisk Technologies Inc. | Programming and selectively erasing non-volatile storage |
| US8762654B1 (en) * | 2008-07-02 | 2014-06-24 | Marvell International Ltd. | Selectively scheduling memory accesses in parallel based on access speeds of memory |
| US8706951B2 (en) | 2008-07-18 | 2014-04-22 | Marvell World Trade Ltd. | Selectively accessing faster or slower multi-level cell memory |
| KR101662621B1 (ko) | 2008-07-22 | 2016-10-05 | 엘에스아이 코포레이션 | 플래시 메모리 디바이스 프로그래밍 방법 및 시스템 |
| KR101468099B1 (ko) * | 2008-07-24 | 2014-12-03 | 삼성전자주식회사 | 불휘발성 메모리 장치의 프로그램 방법 |
| KR101528167B1 (ko) * | 2008-08-01 | 2015-06-12 | 삼성전자주식회사 | 메모리 장치 및 메모리 데이터 판정 방법 |
| US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
| US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
| US7876611B2 (en) * | 2008-08-08 | 2011-01-25 | Sandisk Corporation | Compensating for coupling during read operations in non-volatile storage |
| US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
| US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
| US8145855B2 (en) * | 2008-09-12 | 2012-03-27 | Sandisk Technologies Inc. | Built in on-chip data scrambler for non-volatile memory |
| US8429330B2 (en) * | 2008-09-12 | 2013-04-23 | Sandisk Technologies Inc. | Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations |
| US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
| WO2010035241A1 (en) * | 2008-09-28 | 2010-04-01 | Ramot At Tel Aviv University Ltd. | Method and system for adaptive coding in flash memories |
| US8671327B2 (en) | 2008-09-28 | 2014-03-11 | Sandisk Technologies Inc. | Method and system for adaptive coding in flash memories |
| US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
| US7839687B2 (en) * | 2008-10-16 | 2010-11-23 | Sandisk Corporation | Multi-pass programming for memory using word line coupling |
| KR101486980B1 (ko) * | 2008-10-27 | 2015-01-30 | 삼성전자주식회사 | 불휘발성 메모리의 문턱 전압 산포의 분석 방법 |
| US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
| US8208304B2 (en) * | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
| KR101518039B1 (ko) * | 2008-12-08 | 2015-05-07 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 방법 |
| JP2010160871A (ja) * | 2008-12-12 | 2010-07-22 | Toshiba Corp | 不揮発性半導体記憶装置 |
| KR101642465B1 (ko) * | 2008-12-12 | 2016-07-25 | 삼성전자주식회사 | 불휘발성 메모리 장치의 액세스 방법 |
| KR101559336B1 (ko) * | 2008-12-29 | 2015-10-13 | 삼성전자주식회사 | 메모리 장치의 동작 방법 및 이에 따른 메모리 장치 |
| US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
| US8248831B2 (en) * | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
| US8700840B2 (en) * | 2009-01-05 | 2014-04-15 | SanDisk Technologies, Inc. | Nonvolatile memory with write cache having flush/eviction methods |
| US8040744B2 (en) * | 2009-01-05 | 2011-10-18 | Sandisk Technologies Inc. | Spare block management of non-volatile memories |
| US8094500B2 (en) * | 2009-01-05 | 2012-01-10 | Sandisk Technologies Inc. | Non-volatile memory and method with write cache partitioning |
| US20100174845A1 (en) * | 2009-01-05 | 2010-07-08 | Sergey Anatolievich Gorobets | Wear Leveling for Non-Volatile Memories: Maintenance of Experience Count and Passive Techniques |
| US8244960B2 (en) * | 2009-01-05 | 2012-08-14 | Sandisk Technologies Inc. | Non-volatile memory and method with write cache partition management methods |
| US7974133B2 (en) | 2009-01-06 | 2011-07-05 | Sandisk Technologies Inc. | Robust sensing circuit and method |
| US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
| US7924614B2 (en) * | 2009-01-19 | 2011-04-12 | Macronix International Co., Ltd. | Memory and boundary searching method thereof |
| US8023345B2 (en) * | 2009-02-24 | 2011-09-20 | International Business Machines Corporation | Iteratively writing contents to memory locations using a statistical model |
| US8166368B2 (en) * | 2009-02-24 | 2012-04-24 | International Business Machines Corporation | Writing a special symbol to a memory to indicate the absence of a data signal |
| US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
| US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
| US8832354B2 (en) * | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
| US8026544B2 (en) | 2009-03-30 | 2011-09-27 | Sandisk Technologies Inc. | Fabricating and operating a memory array having a multi-level cell region and a single-level cell region |
| US8832353B2 (en) * | 2009-04-07 | 2014-09-09 | Sandisk Technologies Inc. | Host stop-transmission handling |
| KR101793286B1 (ko) | 2009-04-08 | 2017-11-02 | 샌디스크 테크놀로지스 엘엘씨 | 수직의 비트 라인들 및 단면 워드 라인 아키텍처를 가지는 재프로그래밍 가능한 메모리 요소들의 3차원 어레이 |
| US8351236B2 (en) | 2009-04-08 | 2013-01-08 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture |
| US8199576B2 (en) * | 2009-04-08 | 2012-06-12 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture |
| US7983065B2 (en) * | 2009-04-08 | 2011-07-19 | Sandisk 3D Llc | Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines |
| US7907449B2 (en) | 2009-04-09 | 2011-03-15 | Sandisk Corporation | Two pass erase for non-volatile storage |
| US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
| US8223555B2 (en) * | 2009-05-07 | 2012-07-17 | Micron Technology, Inc. | Multiple level program verify in a memory device |
| US8027195B2 (en) * | 2009-06-05 | 2011-09-27 | SanDisk Technologies, Inc. | Folding data stored in binary format into multi-state format within non-volatile memory devices |
| US8102705B2 (en) * | 2009-06-05 | 2012-01-24 | Sandisk Technologies Inc. | Structure and method for shuffling data within non-volatile memory devices |
| US8307241B2 (en) * | 2009-06-16 | 2012-11-06 | Sandisk Technologies Inc. | Data recovery in multi-level cell nonvolatile memory |
| US7974124B2 (en) * | 2009-06-24 | 2011-07-05 | Sandisk Corporation | Pointer based column selection techniques in non-volatile memories |
| US8054691B2 (en) | 2009-06-26 | 2011-11-08 | Sandisk Technologies Inc. | Detecting the completion of programming for non-volatile storage |
| US20110002169A1 (en) * | 2009-07-06 | 2011-01-06 | Yan Li | Bad Column Management with Bit Information in Non-Volatile Memory Systems |
| US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
| US8134871B2 (en) | 2009-08-05 | 2012-03-13 | Sandisk Technologies Inc. | Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage |
| US8144511B2 (en) * | 2009-08-19 | 2012-03-27 | Sandisk Technologies Inc. | Selective memory cell program and erase |
| US8254170B2 (en) * | 2009-08-25 | 2012-08-28 | Sandisk Il Ltd. | Preloading data into a flash storage device |
| TW201108235A (en) | 2009-08-31 | 2011-03-01 | Sandisk Il Ltd | Preloading data into a flash storage device |
| US8400854B2 (en) | 2009-09-11 | 2013-03-19 | Sandisk Technologies Inc. | Identifying at-risk data in non-volatile storage |
| US8386739B2 (en) * | 2009-09-28 | 2013-02-26 | International Business Machines Corporation | Writing to memory using shared address buses |
| US8230276B2 (en) * | 2009-09-28 | 2012-07-24 | International Business Machines Corporation | Writing to memory using adaptive write techniques |
| US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
| US8473809B2 (en) | 2009-11-20 | 2013-06-25 | Sandisk Technologies Inc. | Data coding for improved ECC efficiency |
| US8243521B2 (en) * | 2009-12-04 | 2012-08-14 | Micron Technology, Inc. | Method for kink compensation in a memory |
| US8473669B2 (en) * | 2009-12-07 | 2013-06-25 | Sandisk Technologies Inc. | Method and system for concurrent background and foreground operations in a non-volatile memory array |
| US8174895B2 (en) | 2009-12-15 | 2012-05-08 | Sandisk Technologies Inc. | Programming non-volatile storage with fast bit detection and verify skip |
| US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
| US8468294B2 (en) * | 2009-12-18 | 2013-06-18 | Sandisk Technologies Inc. | Non-volatile memory with multi-gear control using on-chip folding of data |
| US8725935B2 (en) | 2009-12-18 | 2014-05-13 | Sandisk Technologies Inc. | Balanced performance for on-chip folding of non-volatile memories |
| US8054684B2 (en) * | 2009-12-18 | 2011-11-08 | Sandisk Technologies Inc. | Non-volatile memory and method with atomic program sequence and write abort detection |
| US8144512B2 (en) | 2009-12-18 | 2012-03-27 | Sandisk Technologies Inc. | Data transfer flows for on-chip folding |
| US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
| US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
| WO2011092532A1 (en) | 2010-01-28 | 2011-08-04 | Sandisk Il Ltd. | Sliding-window error correction |
| JP5504936B2 (ja) * | 2010-02-03 | 2014-05-28 | 富士通株式会社 | ストレージ装置およびデータ格納制御方法 |
| US8213255B2 (en) | 2010-02-19 | 2012-07-03 | Sandisk Technologies Inc. | Non-volatile storage with temperature compensation based on neighbor state information |
| US8463985B2 (en) | 2010-03-31 | 2013-06-11 | International Business Machines Corporation | Constrained coding to reduce floating gate coupling in non-volatile memories |
| US8775913B2 (en) | 2010-03-31 | 2014-07-08 | Lsi Corporation | Methods and apparatus for computing soft data or log likelihood ratios for received values in communication or storage systems |
| US8429500B2 (en) | 2010-03-31 | 2013-04-23 | Lsi Corporation | Methods and apparatus for computing a probability value of a received value in communication or storage systems |
| US8504885B2 (en) | 2010-03-31 | 2013-08-06 | Lsi Corporation | Methods and apparatus for approximating a probability density function or distribution for a received value in communication or storage systems |
| TWI447733B (zh) * | 2010-04-14 | 2014-08-01 | Phison Electronics Corp | 計算補償電壓與調整門檻值電壓之方法及記憶體裝置與控制器 |
| US8218366B2 (en) | 2010-04-18 | 2012-07-10 | Sandisk Technologies Inc. | Programming non-volatile storage including reducing impact from other memory cells |
| US8546214B2 (en) | 2010-04-22 | 2013-10-01 | Sandisk Technologies Inc. | P-type control gate in non-volatile storage and methods for forming same |
| US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
| US8208310B2 (en) | 2010-05-04 | 2012-06-26 | Sandisk Technologies Inc. | Mitigating channel coupling effects during sensing of non-volatile storage elements |
| US8254167B2 (en) | 2010-05-17 | 2012-08-28 | Seagate Technologies Llc | Joint encoding of logical pages in multi-page memory architecture |
| US8406051B2 (en) | 2010-05-17 | 2013-03-26 | Seagate Technology Llc | Iterative demodulation and decoding for multi-page memory architecture |
| US8274831B2 (en) | 2010-05-24 | 2012-09-25 | Sandisk Technologies Inc. | Programming non-volatile storage with synchronized coupling |
| KR101692451B1 (ko) * | 2010-05-24 | 2017-01-04 | 삼성전자주식회사 | 메모리 반도체 장치 및 그 동작 방법 |
| US8526237B2 (en) | 2010-06-08 | 2013-09-03 | Sandisk 3D Llc | Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof |
| US8547720B2 (en) | 2010-06-08 | 2013-10-01 | Sandisk 3D Llc | Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines |
| US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
| US8503233B2 (en) | 2010-07-07 | 2013-08-06 | Skymedi Corporation | Method of twice programming a non-volatile flash memory with a sequence |
| US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
| US8369156B2 (en) | 2010-07-13 | 2013-02-05 | Sandisk Technologies Inc. | Fast random access to non-volatile storage |
| US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
| US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
| US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
| KR101682666B1 (ko) * | 2010-08-11 | 2016-12-07 | 삼성전자주식회사 | 비휘발성 메모리 장치, 그것의 채널 부스팅 방법, 그것의 프로그램 방법 및 그것을 포함하는 메모리 시스템 |
| US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
| JP5259667B2 (ja) * | 2010-09-22 | 2013-08-07 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
| US8374031B2 (en) | 2010-09-29 | 2013-02-12 | SanDisk Technologies, Inc. | Techniques for the fast settling of word lines in NAND flash memory |
| US8452911B2 (en) | 2010-09-30 | 2013-05-28 | Sandisk Technologies Inc. | Synchronized maintenance operations in a multi-bank storage system |
| US8464137B2 (en) | 2010-12-03 | 2013-06-11 | International Business Machines Corporation | Probabilistic multi-tier error correction in not-and (NAND) flash memory |
| US8837216B2 (en) | 2010-12-13 | 2014-09-16 | Sandisk Technologies Inc. | Non-volatile storage system with shared bit lines connected to a single selection device |
| US9227456B2 (en) | 2010-12-14 | 2016-01-05 | Sandisk 3D Llc | Memories with cylindrical read/write stacks |
| EP2731110B1 (en) | 2010-12-14 | 2016-09-07 | SanDisk Technologies LLC | Architecture for three dimensional non-volatile storage with vertical bit lines |
| US9898361B2 (en) | 2011-01-04 | 2018-02-20 | Seagate Technology Llc | Multi-tier detection and decoding in flash memories |
| US8917553B2 (en) * | 2011-03-25 | 2014-12-23 | Micron Technology, Inc. | Non-volatile memory programming |
| US9342446B2 (en) | 2011-03-29 | 2016-05-17 | SanDisk Technologies, Inc. | Non-volatile memory system allowing reverse eviction of data updates to non-volatile binary cache |
| US8456911B2 (en) | 2011-06-07 | 2013-06-04 | Sandisk Technologies Inc. | Intelligent shifting of read pass voltages for non-volatile storage |
| US8745369B2 (en) | 2011-06-24 | 2014-06-03 | SanDisk Technologies, Inc. | Method and memory system for managing power based on semaphores and timers |
| US8694719B2 (en) | 2011-06-24 | 2014-04-08 | Sandisk Technologies Inc. | Controller, storage device, and method for power throttling memory operations |
| US8537623B2 (en) * | 2011-07-07 | 2013-09-17 | Micron Technology, Inc. | Devices and methods of programming memory cells |
| JP2011204356A (ja) * | 2011-07-19 | 2011-10-13 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US8743615B2 (en) | 2011-08-22 | 2014-06-03 | Sandisk Technologies Inc. | Read compensation for partially programmed blocks of non-volatile storage |
| JP2012014827A (ja) * | 2011-09-12 | 2012-01-19 | Toshiba Corp | 半導体記憶装置 |
| US8638606B2 (en) | 2011-09-16 | 2014-01-28 | Sandisk Technologies Inc. | Substrate bias during program of non-volatile storage |
| WO2013043602A2 (en) | 2011-09-19 | 2013-03-28 | SanDisk Technologies, Inc. | High endurance non-volatile storage |
| US8406053B1 (en) | 2011-09-21 | 2013-03-26 | Sandisk Technologies Inc. | On chip dynamic read for non-volatile storage |
| US9588883B2 (en) | 2011-09-23 | 2017-03-07 | Conversant Intellectual Property Management Inc. | Flash memory system |
| JP5380510B2 (ja) * | 2011-09-30 | 2014-01-08 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| KR101845509B1 (ko) * | 2011-10-05 | 2018-04-05 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 이의 프로그램 방법 |
| US8711619B2 (en) | 2011-10-18 | 2014-04-29 | Seagate Technology Llc | Categorizing bit errors of solid-state, non-volatile memory |
| US8737133B2 (en) | 2011-10-18 | 2014-05-27 | Seagate Technology Llc | Shifting cell voltage based on grouping of solid-state, non-volatile memory cells |
| US8693257B2 (en) | 2011-10-18 | 2014-04-08 | Seagate Technology Llc | Determining optimal read reference and programming voltages for non-volatile memory using mutual information |
| US8760932B2 (en) | 2011-10-18 | 2014-06-24 | Seagate Technology Llc | Determination of memory read reference and programming voltages |
| CN103065678B (zh) * | 2011-10-21 | 2016-01-13 | 点序科技股份有限公司 | 闪速存储器装置及其数据储存方法 |
| US8917554B2 (en) | 2011-10-26 | 2014-12-23 | Sandisk Technologies Inc. | Back-biasing word line switch transistors |
| US9076544B2 (en) | 2011-11-18 | 2015-07-07 | Sandisk Technologies Inc. | Operation for non-volatile storage system with shared bit lines |
| EP2780912B1 (en) | 2011-11-18 | 2016-10-26 | SanDisk Technologies LLC | Non-volatile storage with data recovery |
| US8687421B2 (en) | 2011-11-21 | 2014-04-01 | Sandisk Technologies Inc. | Scrub techniques for use with dynamic read |
| KR101893145B1 (ko) | 2011-12-06 | 2018-10-05 | 삼성전자주식회사 | 메모리 시스템들 및 그것들의 블록 복사 방법들 |
| US8762627B2 (en) | 2011-12-21 | 2014-06-24 | Sandisk Technologies Inc. | Memory logical defragmentation during garbage collection |
| US8885404B2 (en) | 2011-12-24 | 2014-11-11 | Sandisk Technologies Inc. | Non-volatile storage system with three layer floating gate |
| US8737132B2 (en) | 2012-01-06 | 2014-05-27 | Sandisk Technologies Inc. | Charge cycling by equalizing the source and bit line levels between pulses during no-verify write operations for NAND flash memory |
| US8582381B2 (en) | 2012-02-23 | 2013-11-12 | SanDisk Technologies, Inc. | Temperature based compensation during verify operations for non-volatile storage |
| US8937835B2 (en) | 2012-03-13 | 2015-01-20 | Sandisk Technologies Inc. | Non-volatile storage with read process that reduces disturb |
| US8842473B2 (en) | 2012-03-15 | 2014-09-23 | Sandisk Technologies Inc. | Techniques for accessing column selecting shift register with skipped entries in non-volatile memories |
| US8638608B2 (en) | 2012-03-26 | 2014-01-28 | Sandisk Technologies Inc. | Selected word line dependent select gate voltage during program |
| US8902659B2 (en) | 2012-03-26 | 2014-12-02 | SanDisk Technologies, Inc. | Shared-bit-line bit line setup scheme |
| US8804425B2 (en) | 2012-03-26 | 2014-08-12 | Sandisk Technologies Inc. | Selected word line dependent programming voltage |
| US8804430B2 (en) | 2012-03-26 | 2014-08-12 | Sandisk Technologies Inc. | Selected word line dependent select gate diffusion region voltage during programming |
| US9135192B2 (en) | 2012-03-30 | 2015-09-15 | Sandisk Technologies Inc. | Memory system with command queue reordering |
| US9171627B2 (en) | 2012-04-11 | 2015-10-27 | Aplus Flash Technology, Inc. | Non-boosting program inhibit scheme in NAND design |
| US9087595B2 (en) | 2012-04-20 | 2015-07-21 | Aplus Flash Technology, Inc. | Shielding 2-cycle half-page read and program schemes for advanced NAND flash design |
| KR101915719B1 (ko) | 2012-04-26 | 2019-01-08 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 프로그램 동작 방법 |
| US8681548B2 (en) | 2012-05-03 | 2014-03-25 | Sandisk Technologies Inc. | Column redundancy circuitry for non-volatile memory |
| US8937837B2 (en) | 2012-05-08 | 2015-01-20 | Sandisk Technologies Inc. | Bit line BL isolation scheme during erase operation for non-volatile storage |
| US8923050B2 (en) | 2012-06-15 | 2014-12-30 | Sandisk 3D Llc | 3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof |
| US9281029B2 (en) | 2012-06-15 | 2016-03-08 | Sandisk 3D Llc | Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof |
| US9142305B2 (en) | 2012-06-28 | 2015-09-22 | Sandisk Technologies Inc. | System to reduce stress on word line select transistor during erase operation |
| US9053819B2 (en) | 2012-07-11 | 2015-06-09 | Sandisk Technologies Inc. | Programming method to tighten threshold voltage width with avoiding program disturb |
| US8824203B2 (en) * | 2012-07-13 | 2014-09-02 | Micron Technology, Inc. | Multiple step programming in a memory device |
| US8750045B2 (en) | 2012-07-27 | 2014-06-10 | Sandisk Technologies Inc. | Experience count dependent program algorithm for flash memory |
| US9036417B2 (en) | 2012-09-06 | 2015-05-19 | Sandisk Technologies Inc. | On chip dynamic read level scan and error detection for nonvolatile storage |
| US20140071761A1 (en) | 2012-09-10 | 2014-03-13 | Sandisk Technologies Inc. | Non-volatile storage with joint hard bit and soft bit reading |
| US9490035B2 (en) | 2012-09-28 | 2016-11-08 | SanDisk Technologies, Inc. | Centralized variable rate serializer and deserializer for bad column management |
| US9076506B2 (en) | 2012-09-28 | 2015-07-07 | Sandisk Technologies Inc. | Variable rate parallel to serial shift register |
| US8897080B2 (en) | 2012-09-28 | 2014-11-25 | Sandisk Technologies Inc. | Variable rate serial to parallel shift register |
| US20140108705A1 (en) | 2012-10-12 | 2014-04-17 | Sandisk Technologies Inc. | Use of High Endurance Non-Volatile Memory for Read Acceleration |
| US9159406B2 (en) | 2012-11-02 | 2015-10-13 | Sandisk Technologies Inc. | Single-level cell endurance improvement with pre-defined blocks |
| US9087601B2 (en) | 2012-12-06 | 2015-07-21 | Sandisk Technologies Inc. | Select gate bias during program of non-volatile storage |
| US9336133B2 (en) | 2012-12-31 | 2016-05-10 | Sandisk Technologies Inc. | Method and system for managing program cycles including maintenance programming operations in a multi-layer memory |
| US9465731B2 (en) | 2012-12-31 | 2016-10-11 | Sandisk Technologies Llc | Multi-layer non-volatile memory system having multiple partitions in a layer |
| US9223693B2 (en) | 2012-12-31 | 2015-12-29 | Sandisk Technologies Inc. | Memory system having an unequal number of memory die on different control channels |
| US9348746B2 (en) | 2012-12-31 | 2016-05-24 | Sandisk Technologies | Method and system for managing block reclaim operations in a multi-layer memory |
| US8873284B2 (en) | 2012-12-31 | 2014-10-28 | Sandisk Technologies Inc. | Method and system for program scheduling in a multi-layer memory |
| US9734911B2 (en) | 2012-12-31 | 2017-08-15 | Sandisk Technologies Llc | Method and system for asynchronous die operations in a non-volatile memory |
| US9734050B2 (en) | 2012-12-31 | 2017-08-15 | Sandisk Technologies Llc | Method and system for managing background operations in a multi-layer memory |
| US9076545B2 (en) | 2013-01-17 | 2015-07-07 | Sandisk Tecnologies Inc. | Dynamic adjustment of read voltage levels based on memory cell threshold voltage distribution |
| US9026757B2 (en) | 2013-01-25 | 2015-05-05 | Sandisk Technologies Inc. | Non-volatile memory programming data preservation |
| US8913428B2 (en) | 2013-01-25 | 2014-12-16 | Sandisk Technologies Inc. | Programming non-volatile storage system with multiple memory die |
| KR102106866B1 (ko) | 2013-01-29 | 2020-05-06 | 삼성전자주식회사 | 멀티레벨 불휘발성 메모리 장치 및 프로그램 방법 |
| US8885416B2 (en) | 2013-01-30 | 2014-11-11 | Sandisk Technologies Inc. | Bit line current trip point modulation for reading nonvolatile storage elements |
| US8971128B2 (en) | 2013-01-31 | 2015-03-03 | Sandisk Technologies Inc. | Adaptive initial program voltage for non-volatile memory |
| US9064547B2 (en) | 2013-03-05 | 2015-06-23 | Sandisk 3D Llc | 3D non-volatile memory having low-current cells and methods |
| US9349452B2 (en) | 2013-03-07 | 2016-05-24 | Sandisk Technologies Inc. | Hybrid non-volatile memory cells for shared bit line |
| US9165656B2 (en) | 2013-03-11 | 2015-10-20 | Sandisk Technologies Inc. | Non-volatile storage with shared bit lines and flat memory cells |
| US9135109B2 (en) | 2013-03-11 | 2015-09-15 | Seagate Technology Llc | Determination of optimum threshold voltage to read data values in memory cells |
| US9367389B2 (en) | 2013-03-14 | 2016-06-14 | Seagate Technology Llc | Recovery strategy that reduces errors misidentified as reliable |
| US9037902B2 (en) | 2013-03-15 | 2015-05-19 | Sandisk Technologies Inc. | Flash memory techniques for recovering from write interrupt resulting from voltage fault |
| US8988947B2 (en) | 2013-03-25 | 2015-03-24 | Sandisk Technologies Inc. | Back bias during program verify of non-volatile storage |
| TWI511156B (zh) * | 2013-05-13 | 2015-12-01 | Winbond Electronics Corp | 參考記憶胞的偏壓產生器及偏壓提供方法 |
| US9183940B2 (en) | 2013-05-21 | 2015-11-10 | Aplus Flash Technology, Inc. | Low disturbance, power-consumption, and latency in NAND read and program-verify operations |
| US9123430B2 (en) | 2013-06-14 | 2015-09-01 | Sandisk 3D Llc | Differential current sense amplifier and method for non-volatile memory |
| US8933516B1 (en) | 2013-06-24 | 2015-01-13 | Sandisk 3D Llc | High capacity select switches for three-dimensional structures |
| US9263137B2 (en) | 2013-06-27 | 2016-02-16 | Aplus Flash Technology, Inc. | NAND array architecture for multiple simutaneous program and read |
| KR102125376B1 (ko) | 2013-07-01 | 2020-06-23 | 삼성전자주식회사 | 저장 장치 및 그것의 쓰기 방법 |
| KR102076231B1 (ko) * | 2013-07-09 | 2020-02-12 | 에스케이하이닉스 주식회사 | 데이터 저장 장치, 그것의 동작 방법 및 그것을 포함하는 데이터 처리 시스템 |
| WO2015013689A2 (en) | 2013-07-25 | 2015-01-29 | Aplus Flash Technology, Inc. | Nand array hiarchical bl structures for multiple-wl and all -bl simultaneous erase, erase-verify, program, program-verify, and read operations |
| US9293205B2 (en) | 2013-09-14 | 2016-03-22 | Aplus Flash Technology, Inc | Multi-task concurrent/pipeline NAND operations on all planes |
| US9007841B1 (en) * | 2013-10-24 | 2015-04-14 | Western Digital Technologies, Inc. | Programming scheme for improved voltage distribution in solid-state memory |
| US9613704B2 (en) | 2013-12-25 | 2017-04-04 | Aplus Flash Technology, Inc | 2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify |
| US9202559B2 (en) | 2014-03-12 | 2015-12-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of controlling the same |
| US9230689B2 (en) | 2014-03-17 | 2016-01-05 | Sandisk Technologies Inc. | Finding read disturbs on non-volatile memories |
| US9123392B1 (en) | 2014-03-28 | 2015-09-01 | Sandisk 3D Llc | Non-volatile 3D memory with cell-selectable word line decoding |
| US9343141B2 (en) * | 2014-07-15 | 2016-05-17 | Sandisk Technologies Inc. | Reprogramming memory with single program pulse per data state |
| US9659636B2 (en) | 2014-07-22 | 2017-05-23 | Peter Wung Lee | NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations |
| US9588701B2 (en) | 2014-09-09 | 2017-03-07 | Sandisk Technologies Llc | Multi-stage programming at a storage device using multiple instructions from a host |
| US10114562B2 (en) | 2014-09-16 | 2018-10-30 | Sandisk Technologies Llc | Adaptive block allocation in nonvolatile memory |
| US9443606B2 (en) | 2014-10-28 | 2016-09-13 | Sandisk Technologies Llc | Word line dependent two strobe sensing mode for nonvolatile storage elements |
| US9552171B2 (en) | 2014-10-29 | 2017-01-24 | Sandisk Technologies Llc | Read scrub with adaptive counter management |
| US9934872B2 (en) | 2014-10-30 | 2018-04-03 | Sandisk Technologies Llc | Erase stress and delta erase loop count methods for various fail modes in non-volatile memory |
| US9978456B2 (en) * | 2014-11-17 | 2018-05-22 | Sandisk Technologies Llc | Techniques for reducing read disturb in partially written blocks of non-volatile memory |
| US9349479B1 (en) | 2014-11-18 | 2016-05-24 | Sandisk Technologies Inc. | Boundary word line operation in nonvolatile memory |
| US20160181435A1 (en) * | 2014-12-22 | 2016-06-23 | Wafertech, Llc | Floating gate transistors and method for forming the same |
| US9224502B1 (en) | 2015-01-14 | 2015-12-29 | Sandisk Technologies Inc. | Techniques for detection and treating memory hole to local interconnect marginality defects |
| US10032524B2 (en) | 2015-02-09 | 2018-07-24 | Sandisk Technologies Llc | Techniques for determining local interconnect defects |
| US9449700B2 (en) | 2015-02-13 | 2016-09-20 | Sandisk Technologies Llc | Boundary word line search and open block read methods with reduced read disturb |
| US9564219B2 (en) | 2015-04-08 | 2017-02-07 | Sandisk Technologies Llc | Current based detection and recording of memory hole-interconnect spacing defects |
| US9269446B1 (en) | 2015-04-08 | 2016-02-23 | Sandisk Technologies Inc. | Methods to improve programming of slow cells |
| US10157681B2 (en) | 2015-09-14 | 2018-12-18 | Sandisk Technologies Llc | Programming of nonvolatile memory with verify level dependent on memory state and programming loop count |
| US9653154B2 (en) | 2015-09-21 | 2017-05-16 | Sandisk Technologies Llc | Write abort detection for multi-state memories |
| US9711211B2 (en) * | 2015-10-29 | 2017-07-18 | Sandisk Technologies Llc | Dynamic threshold voltage compaction for non-volatile memory |
| US9778855B2 (en) | 2015-10-30 | 2017-10-03 | Sandisk Technologies Llc | System and method for precision interleaving of data writes in a non-volatile memory |
| US10133490B2 (en) | 2015-10-30 | 2018-11-20 | Sandisk Technologies Llc | System and method for managing extended maintenance scheduling in a non-volatile memory |
| US10120613B2 (en) | 2015-10-30 | 2018-11-06 | Sandisk Technologies Llc | System and method for rescheduling host and maintenance operations in a non-volatile memory |
| US10042553B2 (en) | 2015-10-30 | 2018-08-07 | Sandisk Technologies Llc | Method and system for programming a multi-layer non-volatile memory having a single fold data path |
| KR102451154B1 (ko) | 2015-12-07 | 2022-10-06 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 불휘발성 메모리 장치의 동작 방법 |
| US10248499B2 (en) | 2016-06-24 | 2019-04-02 | Sandisk Technologies Llc | Non-volatile storage system using two pass programming with bit error control |
| US9817593B1 (en) | 2016-07-11 | 2017-11-14 | Sandisk Technologies Llc | Block management in non-volatile memory system with non-blocking control sync system |
| US10048887B2 (en) * | 2016-10-27 | 2018-08-14 | Micron Technology, Inc. | Apparatuses and methods for single level cell caching |
| JP2018160056A (ja) * | 2017-03-22 | 2018-10-11 | 東芝メモリ株式会社 | メモリコントローラ、メモリシステムおよび制御方法 |
| US10146460B1 (en) | 2017-06-01 | 2018-12-04 | Apple Inc. | Programming schemes for avoidance or recovery from cross-temperature read failures |
| US10877827B2 (en) * | 2017-09-15 | 2020-12-29 | Pure Storage, Inc. | Read voltage optimization |
| US10304550B1 (en) | 2017-11-29 | 2019-05-28 | Sandisk Technologies Llc | Sense amplifier with negative threshold sensing for non-volatile memory |
| JP7051546B2 (ja) * | 2018-04-16 | 2022-04-11 | キオクシア株式会社 | メモリシステムおよび制御方法 |
| CN110827904B (zh) * | 2018-08-09 | 2023-04-14 | 旺宏电子股份有限公司 | 存储器装置及其编程方法 |
| KR20200076524A (ko) * | 2018-12-19 | 2020-06-29 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
| US10643695B1 (en) | 2019-01-10 | 2020-05-05 | Sandisk Technologies Llc | Concurrent multi-state program verify for non-volatile memory |
| US11024392B1 (en) | 2019-12-23 | 2021-06-01 | Sandisk Technologies Llc | Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory |
| US11205473B2 (en) * | 2020-02-04 | 2021-12-21 | Western Digital Technologies, Inc. | Dual SLC/QLC programming and resource releasing |
| KR20220068541A (ko) | 2020-11-19 | 2022-05-26 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 이의 동작 방법 |
| US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
| US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230752A (zh) * | 1998-03-31 | 1999-10-06 | 日本电气株式会社 | 非易失性半导体存储装置 |
| US6044006A (en) * | 1998-03-23 | 2000-03-28 | Siemens Aktiengesellschaft | Method for programming a ROM cell arrangement |
| US6091640A (en) * | 1996-09-30 | 2000-07-18 | Hitachi, Ltd. | Semiconductor integrated circuit with multiple write operation modes |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939690A (en) * | 1987-12-28 | 1990-07-03 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with NAND cell structure that suppresses memory cell threshold voltage variation |
| US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
| US5172338B1 (en) * | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
| DE69033262T2 (de) * | 1989-04-13 | 2000-02-24 | Sandisk Corp | EEPROM-Karte mit Austauch von fehlerhaften Speicherzellen und Zwischenspeicher |
| US5663901A (en) * | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
| US5430859A (en) * | 1991-07-26 | 1995-07-04 | Sundisk Corporation | Solid state memory system including plural memory chips and a serialized bus |
| US5712180A (en) * | 1992-01-14 | 1998-01-27 | Sundisk Corporation | EEPROM with split gate source side injection |
| US5657332A (en) * | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
| US5555204A (en) * | 1993-06-29 | 1996-09-10 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
| KR0169267B1 (ko) * | 1993-09-21 | 1999-02-01 | 사토 후미오 | 불휘발성 반도체 기억장치 |
| KR0172401B1 (ko) * | 1995-12-07 | 1999-03-30 | 김광호 | 다수상태 불휘발성 반도체 메모리 장치 |
| US5903495A (en) * | 1996-03-18 | 1999-05-11 | Kabushiki Kaisha Toshiba | Semiconductor device and memory system |
| JP3976839B2 (ja) * | 1996-07-09 | 2007-09-19 | 株式会社ルネサステクノロジ | 不揮発性メモリシステムおよび不揮発性半導体メモリ |
| US5890192A (en) * | 1996-11-05 | 1999-03-30 | Sandisk Corporation | Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM |
| JPH10228784A (ja) * | 1997-02-12 | 1998-08-25 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
| US5926409A (en) * | 1997-09-05 | 1999-07-20 | Information Storage Devices, Inc. | Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application |
| US6108238A (en) * | 1997-09-11 | 2000-08-22 | Kabushiki Kaisha Toshiba | Programmable semiconductor memory device having program voltages and verify voltages |
| US5867429A (en) * | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
| US6151248A (en) * | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
| JP2001067884A (ja) * | 1999-08-31 | 2001-03-16 | Hitachi Ltd | 不揮発性半導体記憶装置 |
| JP3863330B2 (ja) * | 1999-09-28 | 2006-12-27 | 株式会社東芝 | 不揮発性半導体メモリ |
| KR100318325B1 (ko) * | 1999-10-19 | 2001-12-22 | 박종섭 | 플래쉬 메모리 셀의 소거 방법 |
| US6426893B1 (en) | 2000-02-17 | 2002-07-30 | Sandisk Corporation | Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks |
| US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
| US6522580B2 (en) | 2001-06-27 | 2003-02-18 | Sandisk Corporation | Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states |
| US6456528B1 (en) * | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
| US6717847B2 (en) * | 2001-09-17 | 2004-04-06 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
-
2001
- 2001-06-27 US US09/893,277 patent/US6522580B2/en not_active Expired - Lifetime
-
2002
- 2002-06-25 TW TW091113894A patent/TW583672B/zh not_active IP Right Cessation
- 2002-06-26 EP EP02254491A patent/EP1271553B1/en not_active Expired - Lifetime
- 2002-06-26 DE DE60220590T patent/DE60220590T2/de not_active Expired - Lifetime
- 2002-06-26 EP EP07006344.1A patent/EP1814122B1/en not_active Expired - Lifetime
- 2002-06-26 AT AT02254491T patent/ATE364885T1/de not_active IP Right Cessation
- 2002-06-27 KR KR1020020036424A patent/KR100926950B1/ko active IP Right Grant
- 2002-06-27 CN CNB021434670A patent/CN100350503C/zh not_active Expired - Lifetime
- 2002-06-27 JP JP2002187020A patent/JP4221196B2/ja not_active Expired - Fee Related
- 2002-06-27 CN CN2007101537555A patent/CN101127240B/zh not_active Expired - Lifetime
- 2002-12-18 US US10/323,534 patent/US6807095B2/en not_active Expired - Lifetime
-
2004
- 2004-10-15 US US10/966,451 patent/US7061798B2/en not_active Expired - Lifetime
-
2005
- 2005-08-16 US US11/205,595 patent/US7224613B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6091640A (en) * | 1996-09-30 | 2000-07-18 | Hitachi, Ltd. | Semiconductor integrated circuit with multiple write operation modes |
| US6044006A (en) * | 1998-03-23 | 2000-03-28 | Siemens Aktiengesellschaft | Method for programming a ROM cell arrangement |
| CN1230752A (zh) * | 1998-03-31 | 1999-10-06 | 日本电气株式会社 | 非易失性半导体存储装置 |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2001-35173A 2001.02.09 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030128586A1 (en) | 2003-07-10 |
| CN1414566A (zh) | 2003-04-30 |
| TW583672B (en) | 2004-04-11 |
| CN101127240A (zh) | 2008-02-20 |
| US7224613B2 (en) | 2007-05-29 |
| US6807095B2 (en) | 2004-10-19 |
| EP1814122B1 (en) | 2013-05-15 |
| CN100350503C (zh) | 2007-11-21 |
| JP4221196B2 (ja) | 2009-02-12 |
| US7061798B2 (en) | 2006-06-13 |
| DE60220590T2 (de) | 2008-02-14 |
| EP1814122A1 (en) | 2007-08-01 |
| KR20030011248A (ko) | 2003-02-07 |
| EP1271553B1 (en) | 2007-06-13 |
| EP1271553A2 (en) | 2003-01-02 |
| KR100926950B1 (ko) | 2009-11-17 |
| US20030002348A1 (en) | 2003-01-02 |
| US6522580B2 (en) | 2003-02-18 |
| ATE364885T1 (de) | 2007-07-15 |
| EP1271553A3 (en) | 2004-05-06 |
| US20050276101A1 (en) | 2005-12-15 |
| DE60220590D1 (de) | 2007-07-26 |
| US20050047223A1 (en) | 2005-03-03 |
| JP2003109386A (ja) | 2003-04-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101127240B (zh) | 降低非易失性存储器存储元件间耦合效应的方法 | |
| CN1926635B (zh) | 读取nand存储器以补偿存储元件之间的耦合效应的方法 | |
| CN101584006B (zh) | 非易失性存储器中的经分割的软编程 | |
| CN100589206C (zh) | 确定存储器数据单元是否被擦除及处理存储器数据单元的方法 | |
| EP1324343B1 (en) | Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell | |
| EP1700312B1 (en) | Flash storage system with write/erase abort detection mechanism | |
| CN101584005B (zh) | 非易失性存储器中的经分割擦除及擦除验证 | |
| CN102270501B (zh) | 利用编程定序器的闪存器件和系统，以及编程方法 | |
| KR101127413B1 (ko) | 개선된 부분 페이지 프로그램 능력을 가진 비휘발성 메모리및 제어 | |
| CN100547688C (zh) | 非易失性存储装置的编程校验方法 | |
| CN107025944A (zh) | 检测非易失性存储器设备中的擦除失败字线的方法 | |
| CN101095198A (zh) | 非易失性存储器擦除作业中的字线补偿 | |
| CN102306501A (zh) | 编程不同大小的容限及在选择状态下使用补偿进行感测以改进非易失性存储器中的读取操作 | |
| KR102250454B1 (ko) | 3d 비휘발성 메모리에 대한 서브블록 크기 감소 | |
| US7672163B2 (en) | Control gate line architecture | |
| CN113196401B (zh) | 对由于块氧化物减薄引起的编程速度变化进行补偿的存储器设备 | |
| DE112020000174T5 (de) | Adaptive vpass für 3d-flash-speicher mit paarkettenstruktur | |
| CN107103933B (zh) | 反及型闪存及其编程方法 | |
| US7558118B2 (en) | NAND flash memory device | |
| US9449701B1 (en) | Non-volatile storage systems and methods | |
| CN113345503A (zh) | 半导体存储装置以及读出方法 | |
| WO1998056002A1 (en) | Novel flash memory array and decoding architecture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: California, USA Co-patentee after: Toshiba Corp. Patentee after: Sandisk Co.,Ltd. Address before: California, USA Co-patentee before: Toshiba Corp. Patentee before: Sandisk Corp. |
|
| CP01 | Change in the name or title of a patent holder | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190315 Address after: California, USA Co-patentee after: TOSHIBA MEMORY Corp. Patentee after: Sandisk Co.,Ltd. Address before: California, USA Co-patentee before: Toshiba Corp. Patentee before: Sandisk Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191028 Address after: California, USA Co-patentee after: TOSHIBA MEMORY Corp. Patentee after: Western Digital Technologies, Inc. Address before: California, USA Co-patentee before: TOSHIBA MEMORY Corp. Patentee before: Sandisk Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120208 |
|
| CX01 | Expiry of patent term |