CN101140930A - 半导体元件及其制造方法 - Google Patents

半导体元件及其制造方法 Download PDF

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CN101140930A
CN101140930A CNA2007101410465A CN200710141046A CN101140930A CN 101140930 A CN101140930 A CN 101140930A CN A2007101410465 A CNA2007101410465 A CN A2007101410465A CN 200710141046 A CN200710141046 A CN 200710141046A CN 101140930 A CN101140930 A CN 101140930A
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semiconductor element
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boron
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CN101140930B (zh
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黄麒铨
林世安
徐振富
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体元件及其制造方法，包括一电容器及一相邻的高电压栅极，其具有一硼阻障层，此硼阻障层可作为电容器介电层及高电压栅极氧化层。硼阻障层较佳形成于一多晶硅氧化层之上，多晶硅氧化层依序沉积于基板上，而基板可掺杂杂质以形成相邻的阱区，电容器形成于n型阱之上，且HV栅极形成于p型阱上。此硼阻障层可降低或消除在沉积栅极氧化材料时由p型阱扩散出来的硼及其所造成的不良影响。

Description

半导体元件及其制造方法
技术领域
本发明涉及半导体元件及其形成方法，且特别涉及改善半导体元件在生长程序时，因硼扩散至高电压栅极氧化层所导致的不稳定。
背景技术
微电子元件已被大量的使用在各种的应用上，且变为现今社会不可或缺的一部分。其中的应用包括计算机、电话及家庭娱乐等。而电子元件被大量应用的理由之一是其性能的扩充及成本的降低。因此技术上的改进已成为发展半导体元件的重要部分。
以下将简要说明用来形成半导体元件的工艺。将一材料，如硅，作为一基底或基板，并在其上方形成各种电子元件。将此材料形成一适当的形状，通常是称为晶片的薄片。接着选择性地以一种或多种掺质，如硼离子或磷离子，处理此材料。通过导入上述杂质可获得所需的半导体特性。最后各种结构会形成于晶片上以获得所需的元件。
晶片上的表面结构可以蚀刻程序来完成。将晶片表面暴露于一蚀刻剂中。一般来说，可利用公知的光刻技术来进行选择性蚀刻。在光刻技术中，光致抗蚀剂或其它抗蚀材料平匀地沉积于晶片表面。此抗蚀材料可选择性通过一掩模来将部分的抗蚀材料曝光而其它部分则未曝光。曝光后的光致抗蚀剂会变得更坚硬或更脆弱，接着可利用溶剂清除较脆弱的部分，而存留的光致抗蚀剂可保护晶片表面不被蚀刻剂所侵蚀。当晶片蚀刻程序完成后，再将之前存留的光致抗蚀剂以一适当的溶剂去除。
此外，可利用各种沉积技术将其它材料，例如金属或其它导电及绝缘材料等沉积于晶片表面，例如，以化学气相沉积(CVD)或溅镀法进行沉积。也可额外注入离子。接着，选择性地沉积及移除各种材料，使层状堆叠的电子元件结构形成于晶片表面。
单一晶片通常含有多个晶粒，通常各晶粒皆为相同结构，但并非绝对。在所有工艺结束后(或在中间程序时)，可对晶片进行检查及测试，并将损坏的部分移除或修复。最后将分离及测试过的晶粒封装于一硬塑料材料中并以外部导线连接晶粒内部。封装完成的晶粒具有许多的导线，又可称为芯片。
在工艺当中，电子元件可同时形成于晶片上。当某一材料在沉积或选择性蚀刻后，此材料可被用于许多相同或不同的元件。因此需要小心的设计使其符合经济效益。
例如，在高电压混合信号模式(high voltage mixed mode，HV-M.M)的应用方面，半导体元件具有一电容器结构，置于NMOS低电压(LV)栅极及NMOS高电压(HV)栅极之间，如图1A-1F所示。图1A-1F为半导体元件10的传统工艺剖面图，应注意的是，本发明所述的“半导体元件”可为一或多个晶粒所形成的芯片，且在其它情况下，则是描述晶粒特定部分的元件或工艺。
图1A-1F显示半导体元件10的制造，首先形成基板12，其被选择性地掺杂以形成三个不同的区域。此三个区域包括p型阱15、n型阱20及p型阱25。在此步骤中所形成三个区域可用来支持三个元件(请参照图1F)。如上所述，图1的半导体元件包含此三种元件及其相关结构。接着形成场氧化结构30、31、32、33。同时(或之后)HV栅极氧化层35形成于p型阱15之上，如图1B所示。HV栅极氧化层35可利用四乙氧基硅烷(TEOS，tetraethylorthosilicate)化学气相沉积及选择性蚀刻来形成。在沉积的材料上进行蚀刻程序以产生所需要的图案，又称为“图案化”。
第二栅极氧化层40形成于半导体元件的整个表面，如图1C所示。接着形成一导电层(如多晶硅)，并选择性蚀刻此导电层以形成导电结构45、46及47，如图1D所示。结构46形成一电容器的下导电层，导电结构45为一HV栅极，导电结构47为一LV栅极。多晶硅间氧化层/高温氧化层50形成于导电结构46之上，如图1E所示。最后，第二导电层55沉积于多晶硅间氧化层/高温氧化层50之上以形成电容器的上导电层。半导体元件10的表面配置如图1F所示。
然而，由上述传统工艺所形成的HV栅极氧化层具有可靠度不佳等缺点。而栅极氧化层的低稳定度显然是在进行TEOS沉积时由p型阱15的硼扩散所造成的结果。因此，半导体业界急需一种可制造高稳定度HV栅极的方法。
发明内容
本发明的目的是提供一种高稳定度的半导体元件，其在形成栅极氧化层之前沉积一离子阻障层，以增加HV栅极氧化层的稳定度。
为实现本发明的目的提供一种半导体元件，包括一电容器，一高电压栅极，邻近该电容器；所述电容器包括一第一导电层，一第二导电层，设置于该第一导电层上方；以及一硼阻障层，设置于该第一及第二导电层之间作为一介电层；所述高电压栅极包括一硼阻障层；以及一导电层，设置于该硼阻障层上。
为实现本发明的目的又提供了一种半导体元件，包括：一电容器以及一高电压栅极，邻近该电容器。所述电容器包括一第一导电层；一第二导电层，设置于该第一导电层上；以及一氮化硅层，设置于该第一及第二导电层之间，其作为一介电层；所述高电压栅极包括一第一氧化层；一氮化硅层一第二氧化层；以及一导电层，设置于该第一氧化层、该氮化硅层及该第二氧化层之上。
本发明另提供一种半导体元件，包括一电容器设置于HV栅极及LV栅极之间，此电容器形成一第一导电层及一第二导电层。导电层可以沉积或生长多晶硅材料并图案化成适当结构以形成电容器极板。极板之间由介电层结构所隔离，介电层可为多晶硅氧化层及氮化硅层，氮化硅层可为一薄膜。在一实施例中，一离子阻障层形成于基板上(或一多晶硅氧化层形成于基板上)以防止栅极氧化层分解所造成的离子扩散。一般来说，因为硼扩散的影响大于磷扩散，因此当HV栅极形成于p型阱上时，可显现本发明的优点。在一实施例中，离子阻障层为一氧化硅层。在另一实施例中，离子阻障层由一或多个氮氧化钽(TaxOyNz)、氮氧化锆(ZrOyNz)、氮氧化锌(ZnOyNz)、碳化硅(SixCy)及氮氧化硅(SixOyNz)所构成，其中x为任何正整数，y及z为任何非负整数。理想上，在同一程序中沉积电容器介电层及离子阻障层。
本发明另提供一种半导体元件的形成方法，包括提供一基板，例如单晶硅晶片，且在基板中形成多个阱，包括p型阱及相邻的n型阱，形成一第一氧化层于多个阱上，以及形成一第一导电结构于氧化层及n型阱上。在此实施例中，一多晶硅氧化层接着形成于整个元件上，且一氮化硅层形成于多晶硅氧化层上。氮化硅层较佳为一薄膜。在此实施例中，多晶硅氧化层形成电容器介电层的一部分。一栅极氧化层形成于p型阱上，氮化硅层可作为一硼停止层，以防止因栅极氧化材料的分解所造成的硼扩散。可利用TEOS程序沉积栅极氧化层。在一较佳实施例中，沉积及图案化最后的导电层以形成电容器上极板及HV栅极。
为了让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合所附图示，作详细说明如下。
附图说明
图1A显示在基板上形成p型阱及n型阱区。
图1B显示形成场氧化结构，及一HV栅极氧化层形成于p型阱区上。
图1C显示第二栅极氧化层形成于半导体元件的整个表面。
图1D显示形成导电结构。
图1E显示多晶硅间氧化层/高温氧化层形成于导电结构上。
图1F显示第二导电层沉积于多晶硅间氧化层/高温氧化层上以形成电容器的上导电层。
图2A显示半导体基板上形成p型阱及n型阱区。
图2B显示依序形成薄栅极氧化层及场氧化结构。
图2C显示多晶硅结构形成于栅极氧化层上。
图2D显示形成场氧化结构后沉积氮化硅材料层。
图2E显示形成栅极氧化结构。
图2F显示本发明的半导体结构。
其中，附图标记说明如下：
10～半导体元件；           12～基板；
15、25～P型阱；            20～N型阱；
30、31、32、33～场氧化结构；
35～HV栅极氧化层；         40～第二栅极氧化层；
45、46、47～导电结构；
50～多晶硅间氧化层/高温氧化层；
55～第二导电层；           100～半导体元件；
105～基板；                110、120～p型阱；
115～n型阱；                 125～薄栅极氧化层；
126、127、128、129～场氧化结构；
130、135～多晶硅结构；       138～多晶硅氧化层；
140～氮化硅(Si3N4)层；       145～栅极氧化结构；
150～上极板；155～栅极；     160～电容器结构。
具体实施方式
本发明提供一种利用高电压混合信号模式(HV-M.M)技术来制造半导体元件的方法，本发明的半导体元件包括一电容器设置于一高电压栅极及一低电压栅极之间。本发明也可应用于其它的半导体元件之上。本发明的半导体元件工艺可降低因硼扩散至HV氧化区所造成的不良影响。(相较之下，磷扩散至n型阱上方所造成的影响较低)。以下图2A至2F显示本发明的一实施例。
图2A至2F为半导体元件100的工艺剖面图，本发明实施例的元件与图1A-1F的元件类似，具有一电容器基板与一HV栅极。与前述类似，首先在半导体基板上形成三个阱区。在此实施例中，n型阱115形成于基板105中，且介于p型阱110及p型阱120之间，如图2A所示。接着依序形成薄栅极氧化层125及场氧化结构126、127、128、129，如图2B所示。应注意的是，上述各结构的相对尺寸可适度的改变。
利用沉积与图案化程序，如光刻技术形成第一多晶硅层，如图2C所示的多晶硅结构130及135。应注意的是，在此程序中多晶硅结构并未形成于p型阱100上。形成多晶硅氧化层138，例如，以沉积或生长步骤形成于上述结构之上。接着再沉积一层材料，优选为氮化硅(Si3N4)140，但也可使用其它材料，例如氮氧化钽(TaxOyNz)、氮氧化锆(ZrOyNz)、氮氧化锌(ZnOyNz)、碳化硅(SixCy)及氮氧化硅(SixOyNz)的至少一种，其中x为任何正整数，y及z为任何非负整数，如图2D所示。
由此可发现，Si3N4层140在电容器结构160的上下极板之间，可作为一良好的介电层(参照图2F)。更重要的是，在此实施例中，Si3N4层140可作为一硼停止层，以阻止或减缓在沉积HV栅极氧化层时由p型阱110所扩散出来的硼。在此实施例中，以TEOS沉积技术沉积一栅极氧化材料，并利用湿式蚀刻程序图案化此栅极氧化材料以形成栅极氧化结构145，如图2E所示。
在半导体元件100上全面性沉积第二多晶硅层，接着图案化此多晶硅层以形成电容器160的上极板150，如图2E所示。上极板150形成于Si3N4层140上，且栅极155形成于栅极氧化层145上。如上所述，由于利用Si3N4(或其它离子阻障)层140来保护栅极氧化层145以避免硼扩散，使栅极具有良好的可靠度。由于离子阻障层是用来阻止或减缓由p型阱110所扩散出来的硼，因此又称为“硼阻障层”。
本发明的半导体元件的制造方法包括设置第一阱于第二阱及第三阱之间，形成第一氧化层于第一、第二及第三阱上，形成第一导电结构于氧化层及第一阱上以及形成第二导电结构于氧化层及第二阱上方。接着沉积一氮化硅(Si3N4)离子阻障层于第一、第二、及第三阱上，其中此Si3N4层形成于第一及第二导电结构之上。形成第二氧化层，形成第三导电结构于第一阱上，其中该第一导电结构具有Si3N4层，且第二氧化层为一介电层，最后形成第四导电结构于第三阱上。此第四导电结构可形成一栅极，以作为一高电压栅极。在一实施例中，第三阱为一p型阱。
在另一实施例中，Si3N4层可包括一或多个氮氧化钽(TaxOyNz)、氮氧化锆(ZrOyNz)、氮氧化锌(ZnOyNz)、碳化硅(SixCy)及氮氧化硅(SixOyNz)，其中x为任何正整数，y及z为任何非负整数。
此实施例的形成方法包括形成一多晶硅氧化膜，例如在沉积Si3N4层前利用一外延生成程序(epitaxial-growth)形成。在另一实施例中，以TEOS沉积程序形成第二氧化层。第三及第四导电结构，如多晶硅，可在同一程序中沉积而成。
在另一实施例中，本发明提供一种半导体元件的形成方法，包括提供一基板，形成一p型阱于该基板上，沉积一氮化硅层于p型阱上，形成一氧化层于此氮化硅(或其它离子阻障层)及p型阱上，例如，以TEOS沉积程序形成此氧化层，以及形成一导电结构于氧化层上。此导电结构可为一栅极，例如，可作为一高电压栅极，且以多晶硅制成。此方法还包括形成一电容器邻接至此栅极，电容器的形成方法包括形成一第一极板，形成一介电层于第一极板之上，此介电层包括氧化硅，以及形成一第二极板于介电层之上。栅极及第二极板可以相同的材料及单一的多晶硅图案化层形成。
在一实施例中，优选地同时形成氮化硅介电层及沉积此氮化硅于p型阱上。此方法包括形成一含多晶硅氧化物的介电层于第一极板上，且在沉积氮化硅前先形成此多晶硅氧化物。
虽然本发明已以优选实施例揭示如上，然而其并非用以限定本发明，任何熟悉此技术的技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视后附的权利要求书为准。

Claims (10)

1.一种半导体元件，包括：
一电容器；包括：
一第一导电层；
一第二导电层，设置于该第一导电层上方；以及
一硼阻障层，设置于该第一及第二导电层之间作为一介电层，以及一高电压栅极，邻近该电容器；包括：
一硼阻障层；以及
一导电层，设置于该硼阻障层上。
2.如权利要求1所述的半导体元件，其特征是该硼阻障层包括氮化硅。
3.如权利要求1所述的半导体元件，其特征是该硼阻障层包括氮氧化钽、氮氧化锆、氮氧化锌、碳化硅及氮氧化硅的至少一种材料，其中x为任何正整数，y及z为任何非负整数。
4.如权利要求1所述的半导体元件，其特征是该高电压栅极还包括一第一氧化层及一第二氧化层，且两者以该硼阻障层隔离。
5.一种半导体元件，包括：
一基板，包括一p型阱；以及
一高电压栅极结构，形成于该p型阱之上，其中该高电压栅极结构包括一形成于一硼阻障层上的栅极。
6.如权利要求5所述的半导体元件，其特征是该硼阻障层包括氮化硅。
7.如权利要求5所述的半导体元件，其特征是该硼阻障层包括氮氧化钽、氮氧化锆、氮氧化锌、碳化硅及氮氧化硅至少一种材料，其中x为任何正整数，y及z为任何非负整数。
8.如权利要求5所述的半导体元件，还包括一氧化层，该氧化层以一氮化硅层与该p型阱隔离。
9.如权利要求5所述的半导体元件，还包括一电容器，该电容器包括一下极板、上极板及一介电层介于上极板与下极板之间。
10.一种半导体元件，包括：
一电容器，包括
一第一导电层；
一第二导电层，设置于该第一导电层上；以及
一氮化硅层，设置于该第一及第二导电层之间，其作为一介电层；以及
一高电压栅极，邻近该电容器，包括：
一第一氧化层；
一氮化硅层
一第二氧化层；以及
一导电层，设置于该第一氧化层、该氮化硅层及该第二氧化层之上。
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