CN101142688A - 具有应变沟道区的非平面mos结构 - Google Patents

具有应变沟道区的非平面mos结构 Download PDF

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CN101142688A
CN101142688A CNA2006800087117A CN200680008711A CN101142688A CN 101142688 A CN101142688 A CN 101142688A CN A2006800087117 A CNA2006800087117 A CN A2006800087117A CN 200680008711 A CN200680008711 A CN 200680008711A CN 101142688 A CN101142688 A CN 101142688A
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strained
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B·多伊尔
S·达塔
B·-Y·金
R·曹
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Intel Corp
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Abstract

实施方案是包括应变沟道区的非平面MOS晶体管结构。非平面MOS晶体管结构，尤其是NMOS三栅晶体管，和应变沟道优点的结合，使得与具有非应变沟道的非平面MOS结构或者包含应变沟道的平面MOS结构相比，就给定栅长度宽度而言，改善了晶体管驱动电流、开关速度，并减少了漏电流。

Description

具有应变沟道区的非平面MOS结构
技术领域
本发明的实施方案涉及晶体管结构，尤其涉及结合有应变沟道(strained channel)的非平面晶体管结构。
背景技术
传统平面金属氧化物半导体(MOS)晶体管技术就某些晶体管特征而言正在接近基础物理极限，越过这些极限就将需要采用替换性材料、加工技术和/或晶体管结构来支持晶体管性能根据摩尔定律的持续改善。
一种示范性的此类转变是非平面MOS结构。一种特殊非平面MOS结构是非平面三栅晶体管(tri-gate transistor)。三栅晶体管采用三维栅极结构，使得电信号可以沿着晶体管栅极的顶部以及沿着栅极的两个垂直侧壁来传导。沿着栅极三个侧壁的传导使得和平面MOS结构相比较，驱动电流更大，开关速度(switching speed)更快，栅极长度(gate length)更短，同时晶体管性能得以提高而占据的衬底面积却更小，并具有其它改进。三栅结构通过改善晶体管的短沟道性质(short channelcharacteristics)，进一步降低了漏电流的量，而这是一直在缩小的平面MOS器件容易出现的问题。
另一种示范性转变涉及对晶体管的各个部分采用应变半导体材料(strained semiconductor material)。为半导体晶格添加拉伸或者压缩应变(取决于特定应用)，提高了载流子在应变半导体中的迁移率。具体而言，对于NMOS器件而言，为半导体赋予拉伸应变提高了电子迁移率(即，在NMOS器件中占优势地位的电荷载流子)。增加的载流子迁移率进而使得可以具有更大的驱动电流和相应更快的开关速度。
附图简述
图1示出了绝缘体上硅(SOI)衬底的横截面。
图2示出了图1的衬底、应变硅锗以及具有用于Smart Cut工艺的氢注入(hydrogen implant)的硅。
图3示出了在应变硅锗和硅的Smart Cut成形后图2的衬底的横截面。
图4示出了在退火形成松弛的(relaxed)硅锗后图3的衬底的横截面。
图5示出了在所述松弛的硅锗实现图案化之后图4的衬底的横截面。
图6示出了在松弛的硅锗上形成应变硅之后图5的衬底的横截面。
图7示出了在形成栅电介质和栅极以形成包括应变沟道的非平面MOS结构之后，图6的衬底的横截面。
图8示出了图7的衬底的透视图。
图9示出了在注入以形成源极区和漏极区之后图8的透视图。
发明详述
下面描述具有应变沟道区的非平面MOS晶体管结构的实施方案。现在详细参考对如附图中所示的这些实施方案的描述。虽然将结合这些附图对实施方案进行描述，但是并不试图将其限制到在本文公开的附图中。相反，旨在覆盖落在所附权利要求限定的所述实施方案的精神和范围之内的所有备选方案、变体和等同方案。
简而言之，一个实施方案是包括应变沟道区的非平面MOS晶体管结构。非平面MOS晶体管结构，尤其是NMOS三栅晶体管，和应变沟道优点的结合，使得和具有非应变沟道的非平面MOS结构或者包含应变沟道的平面MOS结构相比，就给定栅极长度、栅极宽度和操作电压而言，改善了晶体管驱动电流、开关速度，并减少了漏电流。
图1示出了绝缘体上硅(SOI)衬底的横截面。如同本领域公知的，SOI衬底尤其通过减少在杂质层(例如，平面MOS结构的杂质掺杂的源极区和漏极区)和衬底之间的结电容层(junction capacitance layer)中形成的电容这一特征来改善晶体管性能。例如，在一个实施方案中，衬底100包含硅。在衬底100上面的是掩埋的氧化物101。在一个实施方案中，掩埋的氧化物包含二氧化硅。在掩埋的氧化物101上方是硅102。市售的SOI衬底通常包括大约500埃厚的硅102层。为了进一步减少结电容面积，一个实施方案将硅102平坦化和抛光(例如，通过化学机械抛光或者CMP)至大约20-100埃。但是，应该理解衬底100、掩埋的氧化物101和硅102的SOI组合，也可如本领域公知的那样通过采用如下方式来制备：通过注入氧分离(SIMOX)、粘合和回蚀刻(BESOI)制备或者通过在BESOI工艺之前的氢注入(Smart Cut)制备。
图2示出了图1的衬底100的横截面，包括应变硅锗201和硅202，其中应变硅锗201和硅202还没有通过本领域公知的、由SOITEC开发的Smart Cut技术转移到硅201上。Smart Cut方法的具体应用涉及在作为独立衬底的硅202上生长应变硅锗层201，其如图2所示包括大型牺牲性硅202层。将高剂量(即，1017/cm2)的氢注入到硅202中的靠近应变硅锗201的厚度，或者注入到处于硅锗层201中的深度，如氢注入203所示(所示的是在硅202内部沉积)。使包括硅202和应变硅锗201的独立衬底与包括掩埋的氧化物101和硅102的衬底100接触。具体而言，在高温退火后，硅102和应变硅锗201的表面通过化学疏水键合结合。换一种说法，即应变硅锗201通过共价力(covalent force)键合到硅102上。在一个实施方案中，退火是在大约800℃-900℃之间进行大约1小时。基于硅202中的高剂量氢注入203，退火进一步形成硅202的深入内部的弱化(in-depth weakened)层。由于硅102和应变硅锗201之间的键合力比深入内部的硅202的氢注入203弱化的区域所能承受的力大，所以硅202的牺牲部分(或者，如果氢注入203发生在硅锗201中，那么是硅锗201和硅202的牺牲部分)可以劈开，得到图3所示的结构。在一个实施方案中，留下的硅202(或者硅锗201)可以化学机械抛光以形成对后续加工步骤而言合适的硅202(或者硅锗201)表面。
硅和锗具有相同的晶格结构；但是，锗的晶格常数比锗的晶格常数大4.2％(硅的晶格常数是5.43埃，而锗的晶格常数是5.66埃)。硅锗合金Si1-xGex(x＝0.0-1.0)具有单调增加的晶格常数，当x从0.0增加到1.0时。在硅锗上沉积薄的硅层会由于下面的硅锗晶格结构强迫薄的硅沉积层的晶格，而在较小的硅晶格向较大的硅锗晶格对齐时产生具有拉伸应变的硅层。相似地，可以在硅层上生长具有压缩应变的薄硅锗层。但是，随着应变材料沉积层增厚，它们往往发生松弛回到其固有的晶格结构。
图4示出了图3的衬底100在高温长时间退火之后的横截面。在一个实施方案中，退火在大约800℃-1100℃之间进行大约1秒-3小时。在一个实施方案的退火中，温度是大约1000℃，时间是大约2小时。在高温长时间退火中，应变硅锗201中的锗扩散到硅102和硅202中。当锗扩散至在应变硅201、硅102和硅202中是大致恒定的浓度时，它形成松弛的硅锗401。由于不再受到相邻硅的压缩应变作用，所以松弛的硅锗401的晶格常数基于松弛的硅锗401中锗的浓度而增加。在一个实施方案中，松弛的硅锗401的锗浓度范围是大约5％-80％(即，大约5％-80％的硅晶格位点都被锗占据)。在一个实施方案中，松弛的硅锗401的锗浓度是大约15％。基于硅102、应变硅锗201、硅202或者其组合的退火前掺杂(或者，在一个实施方案中，独立的松弛的硅锗401掺杂工艺)，松弛的硅锗401可以用本领域公知的任何p型掺杂剂进行p掺杂。松弛的硅锗401实施方案的p型掺杂剂浓度水平可以大约位于未掺杂水平和6×1019/cm3之间。在一个实施方案中，松弛的硅锗401的p型掺杂剂浓度水平是大约1017/cm3。
图5示出了在松弛的硅锗401经过光刻图案化(lithographicpatterning)以形成松弛的硅锗翼片(fin)501之后图4的衬底100的横截面。松弛的硅锗翼片501可以通过本领域公知的任何方法进行图案化以使硅锗实现图案化。在一个实施方案中，松弛的硅锗翼片通过本领域公知的任何干硅蚀刻工艺进行图案化。在光刻图案化之后，一个实施方案的松弛的硅锗翼片501具有基本矩形的横截面，这是因为光刻图案化基本是各向异性的并且形成基本垂直的松弛的硅锗翼片501侧壁。在进一步的实施方案(未示出)中，松弛的的硅锗翼片501具有基本为梯形的横截面，其上表面和与掩埋的氧化物101相邻的其基底相比横跨的横向距离更小。对于基本为矩形和基本为梯形的实施方案两者而言，松弛的硅锗翼片501包括顶部和两个侧壁，所述顶部和侧壁的宽度和高度尺寸大约是晶体管栅极长度的25％-100％，并可以具有从基本上为高且薄的形状直至基本上为短且宽形状的任何形状。在又一实施方案(也没有示出)中，松弛的硅锗翼片501具有其它几何横截面，所述横截面可以包括另外的侧壁或者可以基本是半球状的。
图6示出了在沉积应变硅601之后的图5的衬底100的横截面。如上所述，松弛的硅锗翼片501的晶格常数比硅的晶格常数大。当在松弛的硅锗翼片501顶上形成薄硅层时，如果硅的厚度足够小，则硅晶格将和松弛的硅锗翼片501晶格对齐，以形成应变硅601。由于松弛的硅锗翼片501晶格常数比硅的晶格常数大，所以随后形成的应变硅601显示出拉伸应变，这是因为较小的硅晶格经拉伸以和松弛的硅锗翼片501晶格相适应。如上所述，拉伸应变增加了包含一个实施方案的非平面MOS晶体管的沟道区的应变硅601中的载流子迁移率。
应变硅601可以通过本领域公知的任何方法沉积以沉积晶体硅。在一个实施方案中，应变硅601采用选择性取向生长沉积，使得硅仅仅在松弛的硅锗翼片401的表面上生长，而不在松弛的硅锗翼片501图案化过程中暴露的掩埋氧化物101的表面上生长。例如，在一个实施方案中，实施方案的低压化学气相沉积工艺采用硅烷(SiH4)、二硅烷(Si2H4)、二氯代硅烷(SiH2Cl2)和三氯代硅烷(SiHCl3)作为硅源，采用HCL作为蚀刻气体用于选择性生长。在一个实施方案中，沉积室的压力是大约500毫托-500托，衬底100的温度是大约400℃-1100℃，总前体气体流速是大约10sccm-1000sccm。应该理解，沉积条件可以根据沉积室的尺寸而变。应该进一步理解，取向沉积基本上形成单晶应变硅601。
在一个实施方案中，应变硅601掺杂有p型掺杂剂。在一个实施方案中，应变硅601的p型掺杂剂浓度水平范围是从大约未掺杂到6×1019/cm3。应该理解，应变硅601可以通过本领域公知的任何掺杂方法掺杂。具体而言，在一个实施方案的低压化学沉积工艺中应变硅601可以在其沉积过程中通过结合掺杂剂前体进行原位掺杂。或者应变硅601可以通过外扩散或者注入来掺杂。
如上所述，一个实施方案的松弛的硅锗翼片501的横截面具有顶部和两个侧壁。需要注意的是，应变硅601应该沉积在松弛的硅锗翼片501的顶部和两个侧壁上，每个表面都具有基本均匀的厚度。一个实施方案中，在顶部和侧壁上的应变硅601具有大约在2纳米-10纳米之间的基本均匀的厚度。在一个实施方案中，应变硅601的厚度是大约4-5纳米。在一个实施方案中，应变硅601的厚度允许深度耗尽(deeply depleted)或者完全耗尽的沟道条件，这是本领域所公知的。
图7示出了在沉积了栅电介质701和栅极702之后图6的衬底100的横截面，以说明非平面三栅晶体管的横截面。在一个实施方案中，栅电介质701包含二氧化硅。在进一步的实施方案中，栅电介质701包含高介电常数材料，比如二氧化铪、硅酸铪、氧化镧、铝酸镧、氧化锆、硅酸锆、氧化钽、二氧化钛、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸铅钪(lead scandium tantanate)或者铌酸铅锌(lead zincniobate)。栅电介质701可以以本领域公知的任何方法沉积以沉积栅电介质701材料。
在一个实施方案中，栅电介质701的沉积是毯式沉积(blanketdeposition)。在沉积栅电介质701之后，沉积栅极702。在一个实施方案中，栅极702包含多晶硅、在高k栅电介质701界面处具有金属层的多晶硅、或者完全金属的栅极。在一个实施方案中，栅极702的沉积是毯式沉积。在其中栅电介质701和栅极702的沉积都是毯式沉积的实施方案中，两者的每一个都被蚀刻以暴露应变硅601区域，随后所述区域形成一个实施方案的三栅非平面晶体管的源极和漏极。值得注意的是，一个实施方案的栅极702和下面的栅电介质701延伸到松弛的硅锗翼片501(包括其上形成的应变硅601)的所有壁上(在一个实施方案中，顶部和两个侧壁)。
在替换性的实施方案(未示出)中，栅极702仅仅和松弛的硅锗翼片501的侧壁相邻，并不延伸到松弛的硅锗翼片501的顶部。应变硅601可以在松弛的硅锗翼片501的整个暴露表面(即，顶部和两个侧壁)上形成，或者可以仅仅在硅锗翼片501的两个侧壁上形成。同样地，栅电介质701可以在形成于松弛的硅锗翼片501上面的应变硅601的整个暴露表面(即，顶部和两个侧壁)上形成，或者可以仅仅形成在应变硅601的两个侧壁上。采用这种设置，一个实施方案的非平面晶体管类似于包括应变硅601沟道区的FinFET。
图8是图7的衬底100的透视图，包括掩埋的氧化物101、松弛的硅锗翼片501、应变硅601、栅电介质701和栅极702。在一个实施方案中，如上所述，栅电介质701和栅极702的毯式沉积已经被蚀刻以暴露松弛的硅锗翼片501。应该理解，一个松弛的硅锗翼片501可以针对许多栅极702运转，一个栅极702可以和许多松弛的硅锗翼片501一起操作，以形成非平面三栅MOS晶体管的阵列。
图9示出了图8的透视图，包括注入901以形成源极902和漏极903。形成MOS晶体管的源极和漏极是本领域公知的，注入901(例如，用于NMOS器件的n型掺杂剂注入)进一步降低了源极902和漏极903两者与随后制备的金属接点之间的接触电阻率，以改善一个实施方案的非平面三栅MOS晶体管的性能。
一个实施方案的所得结构是包括应变硅601沟道的非平面三栅MOS晶体管。如上所述，应变硅601晶格的拉伸应变提高应变硅601晶格中的电子和空穴迁移率，以制备具有改进的性能特征的NMOS器件。另外，在一个实施方案中，应变硅601的厚度使得可以具有深度耗尽或者完全耗尽的条件以减少当NMOS器件处于关闭状态(即，栅电压为0时的增强模式)时的漏电流。
本领域技术人员会认识到，当实施方案将非平面MOS晶体管结构和应变沟道材料组合时，具有改善晶体管性能的优点。

Claims (22)

1.一种非平面晶体管，包括：
在衬底上形成的并且和所述衬底在电学上隔离的硅锗本体；
在所述硅锗本体上形成的应变硅；
在所述应变硅上形成的栅电介质；
在所述栅电介质上形成的栅极；和
在所述应变硅中形成的源极和漏极。
2.权利要求1的非平面晶体管，所述硅锗本体包含浓度为大约5％-80％的锗。
3.权利要求2的非平面晶体管，所述硅锗本体包含浓度为大约15％的锗。
4.权利要求1的非平面晶体管，所述栅电介质包含选自如下组的材料：二氧化硅、二氧化铪、硅酸铪、氧化镧、铝酸镧、氧化锆、硅酸锆、氧化钽、二氧化钛、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸铅钪和铌酸铅锌。
5.权利要求1的非平面晶体管，所述栅极包含选自多晶硅、金属和它们的组合的材料。
6.权利要求1的非平面晶体管，其中所述硅锗本体具有基本上为矩形的横截面，所述应变硅在所述硅锗本体的顶部和两个侧壁上形成。
7.权利要求1的非平面晶体管，其中所述硅锗本体具有基本上为梯形的横截面，所述应变硅在所述硅锗本体的顶部和两个侧壁上形成。
8.权利要求1的非平面晶体管，其中所述应变硅的厚度为大约2纳米-10纳米。
9.权利要求8的非平面晶体管，其中所述应变硅的厚度为大约4纳米-5纳米。
10.一种三栅晶体管，包括：
在绝缘体上形成的硅锗翼片，所述硅锗翼片包括顶表面和两个侧壁表面；
在所述硅锗翼片的顶表面和两个侧壁表面上形成的应变硅膜；
在所述应变硅膜上形成的栅电介质；
在所述栅电介质上形成的栅极，其中所述栅极延伸到所述硅锗翼片的顶表面上；和
在所述应变硅膜中形成的源极和漏极。
11.权利要求10的三栅晶体管，所述硅锗翼片包含浓度为大约5％-80％的锗。
12.权利要求11的三栅晶体管，所述硅锗翼片包含浓度为大约15％的锗。
13.权利要求10的三栅晶体管，其中所述应变硅膜的厚度为大约2纳米-10纳米。
14.权利要求13的三栅晶体管，其中所述应变硅膜的厚度为大约4纳米-5纳米。
15.一种方法，包括：
在绝缘体衬底上的硅上形成硅锗；
对所述硅锗进行退火以松弛所述硅锗；
在所述松弛的硅锗中形成翼片，所述翼片包括顶表面和两个侧壁表面；和
在所述翼片的顶表面和两个侧壁表面上形成应变硅。
16.权利要求15的方法，对所述硅锗进行退火进一步包括使锗扩散到位于绝缘体衬底上的硅的硅中。
17.权利要求16的方法，进一步包括：
在应变硅膜上形成栅电介质，栅电介质材料选自二氧化硅、二氧化铪、硅酸铪、氧化镧、铝酸镧、氧化锆、硅酸锆、氧化钽、二氧化钛、钛酸钡锶、钛酸钡、钛酸锶、氧化钇、氧化铝、钽酸铅钪和铌酸铅锌。
18.权利要求17的方法，进一步包括：
在栅电介质上形成栅极，栅极材料选自多晶硅、金属和它们的组合。
19.权利要求18的方法，进一步包括：
掺杂所述应变硅以形成源极和漏极。
20.一种装置，包括：
包含应变硅沟道区的三栅晶体管。
21.权利要求20的装置，其中所述应变硅沟道区的厚度是大约2纳米-10纳米。
22.权利要求21的装置，其中所述应变硅沟道区的厚度为大约4纳米-5纳米。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102640269A (zh) * 2009-09-30 2012-08-15 苏沃塔公司 电子装置和系统及其制造和使用方法
CN103367432A (zh) * 2012-03-31 2013-10-23 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管及其制造方法
CN103413828A (zh) * 2013-07-18 2013-11-27 清华大学 多边形沟道层多栅结构隧穿晶体管及其形成方法
CN103515420A (zh) * 2012-06-26 2014-01-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN104835744A (zh) * 2014-02-11 2015-08-12 格罗方德半导体公司 具有松弛硅/锗鳍片的集成电路
CN107210225A (zh) * 2015-01-13 2017-09-26 国际商业机器公司 pFET区域中的应变释放
CN108010880A (zh) * 2016-10-31 2018-05-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN111509048A (zh) * 2020-04-28 2020-08-07 上海华力集成电路制造有限公司 N型鳍式晶体管及其制造方法

Families Citing this family (135)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
KR100625175B1 (ko) * 2004-05-25 2006-09-20 삼성전자주식회사 채널층을 갖는 반도체 장치 및 이를 제조하는 방법
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7470951B2 (en) * 2005-01-31 2008-12-30 Freescale Semiconductor, Inc. Hybrid-FET and its application as SRAM
FR2881877B1 (fr) * 2005-02-04 2007-08-31 Soitec Silicon On Insulator Transistor a effet de champ multi-grille a canal multi-couche
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7538351B2 (en) * 2005-03-23 2009-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an SOI structure with improved carrier mobility and ESD protection
FR2885733B1 (fr) * 2005-05-16 2008-03-07 St Microelectronics Crolles 2 Structure de transistor a trois grilles
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7960791B2 (en) * 2005-06-24 2011-06-14 International Business Machines Corporation Dense pitch bulk FinFET process by selective EPI and etch
US7400031B2 (en) * 2005-09-19 2008-07-15 International Business Machines Corporation Asymmetrically stressed CMOS FinFET
US7452768B2 (en) * 2005-10-25 2008-11-18 Freescale Semiconductor, Inc. Multiple device types including an inverted-T channel transistor and method therefor
US8513066B2 (en) * 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
US7615806B2 (en) 2005-10-31 2009-11-10 Freescale Semiconductor, Inc. Method for forming a semiconductor structure and structure thereof
US7341916B2 (en) * 2005-11-10 2008-03-11 Atmel Corporation Self-aligned nanometer-level transistor defined without lithography
KR100734304B1 (ko) * 2006-01-16 2007-07-02 삼성전자주식회사 트랜지스터의 제조방법
EP1833094B1 (en) * 2006-03-06 2011-02-02 STMicroelectronics (Crolles 2) SAS Formation of shallow SiGe conduction channel
JP2007299951A (ja) * 2006-04-28 2007-11-15 Toshiba Corp 半導体装置およびその製造方法
US7648853B2 (en) * 2006-07-11 2010-01-19 Asm America, Inc. Dual channel heterostructure
US7999251B2 (en) * 2006-09-11 2011-08-16 International Business Machines Corporation Nanowire MOSFET with doped epitaxial contacts for source and drain
US7452758B2 (en) * 2007-03-14 2008-11-18 International Business Machines Corporation Process for making FinFET device with body contact and buried oxide junction isolation
US7821061B2 (en) 2007-03-29 2010-10-26 Intel Corporation Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications
US7932542B2 (en) * 2007-09-24 2011-04-26 Infineon Technologies Ag Method of fabricating an integrated circuit with stress enhancement
CN100570823C (zh) * 2007-11-06 2009-12-16 清华大学 一种使用缩颈外延获得低位错密度外延薄膜的方法
US7629643B2 (en) * 2007-11-30 2009-12-08 Intel Corporation Independent n-tips for multi-gate transistors
KR100920047B1 (ko) * 2007-12-20 2009-10-07 주식회사 하이닉스반도체 수직형 트랜지스터 및 그의 형성방법
US8129749B2 (en) * 2008-03-28 2012-03-06 Intel Corporation Double quantum well structures for transistors
US8278687B2 (en) * 2008-03-28 2012-10-02 Intel Corporation Semiconductor heterostructures to reduce short channel effects
KR101505494B1 (ko) * 2008-04-30 2015-03-24 한양대학교 산학협력단 무 커패시터 메모리 소자
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US8053838B2 (en) * 2008-06-26 2011-11-08 International Business Machines Corporation Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets)
US7833891B2 (en) * 2008-07-23 2010-11-16 International Business Machines Corporation Semiconductor device manufacturing method using oxygen diffusion barrier layer between buried oxide layer and high K dielectric layer
US7884354B2 (en) * 2008-07-31 2011-02-08 Intel Corporation Germanium on insulator (GOI) semiconductor substrates
US7781283B2 (en) * 2008-08-15 2010-08-24 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US7979836B2 (en) * 2008-08-15 2011-07-12 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US8237195B2 (en) * 2008-09-29 2012-08-07 Fairchild Semiconductor Corporation Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate
US8184472B2 (en) * 2009-03-13 2012-05-22 International Business Machines Corporation Split-gate DRAM with lateral control-gate MuGFET
JP5645368B2 (ja) * 2009-04-14 2014-12-24 株式会社日立製作所 半導体装置およびその製造方法
KR101089659B1 (ko) 2009-06-03 2011-12-06 서울대학교산학협력단 돌출된 바디를 저장노드로 하는 메모리 셀 및 그 제조방법
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8021949B2 (en) * 2009-12-01 2011-09-20 International Business Machines Corporation Method and structure for forming finFETs with multiple doping regions on a same chip
US8440998B2 (en) * 2009-12-21 2013-05-14 Intel Corporation Increasing carrier injection velocity for integrated circuit devices
US8633470B2 (en) * 2009-12-23 2014-01-21 Intel Corporation Techniques and configurations to impart strain to integrated circuit devices
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
CN102468303B (zh) * 2010-11-10 2015-05-13 中国科学院微电子研究所 半导体存储单元、器件及其制备方法
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
TWI499006B (zh) * 2011-10-07 2015-09-01 Etron Technology Inc 動態記憶體結構
CN103137671B (zh) * 2011-12-02 2015-06-24 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管及其制作方法
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
KR101835655B1 (ko) 2012-03-06 2018-03-07 삼성전자주식회사 핀 전계 효과 트랜지스터 및 이의 제조 방법
US8872284B2 (en) * 2012-03-20 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with metal gate stressor
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
CN103515209B (zh) * 2012-06-19 2017-07-14 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9136383B2 (en) 2012-08-09 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US8847324B2 (en) * 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
US8957476B2 (en) 2012-12-20 2015-02-17 Intel Corporation Conversion of thin transistor elements from silicon to silicon germanium
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
CN103915483B (zh) * 2012-12-28 2019-06-14 瑞萨电子株式会社 具有被改造以减少漏电流的沟道芯部的场效应晶体管及制作方法
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US8951870B2 (en) 2013-03-14 2015-02-10 International Business Machines Corporation Forming strained and relaxed silicon and silicon germanium fins on the same wafer
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
GB2549911A (en) * 2013-06-26 2017-11-01 Intel Corp Conversion of thin transistor elements from silicon to silicon germanium
US8952420B1 (en) 2013-07-29 2015-02-10 Stmicroelectronics, Inc. Method to induce strain in 3-D microfabricated structures
US9496397B2 (en) 2013-08-20 2016-11-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFet device with channel epitaxial region
US8951850B1 (en) 2013-08-21 2015-02-10 International Business Machines Corporation FinFET formed over dielectric
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9099559B2 (en) * 2013-09-16 2015-08-04 Stmicroelectronics, Inc. Method to induce strain in finFET channels from an adjacent region
JP6235325B2 (ja) * 2013-12-10 2017-11-22 株式会社東芝 電界効果トランジスタ及びその製造方法、半導体デバイス及びその製造方法
WO2015094164A1 (en) * 2013-12-16 2015-06-25 Intel Corporation Dual strained cladding layers for semiconductor devices
US20150255555A1 (en) * 2014-03-05 2015-09-10 Globalfoundries Inc. Methods of forming a non-planar ultra-thin body device
US9443963B2 (en) 2014-04-07 2016-09-13 International Business Machines Corporation SiGe FinFET with improved junction doping control
US9985030B2 (en) 2014-04-07 2018-05-29 International Business Machines Corporation FinFET semiconductor device having integrated SiGe fin
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
KR101628197B1 (ko) 2014-08-22 2016-06-09 삼성전자주식회사 반도체 소자의 제조 방법
KR102255174B1 (ko) * 2014-10-10 2021-05-24 삼성전자주식회사 활성 영역을 갖는 반도체 소자 및 그 형성 방법
WO2016060337A1 (ko) * 2014-10-13 2016-04-21 한국과학기술원 전계 효과 트랜지스터의 제조 방법
US9614057B2 (en) * 2014-12-30 2017-04-04 International Business Machines Corporation Enriched, high mobility strained fin having bottom dielectric isolation
KR102310080B1 (ko) * 2015-03-02 2021-10-12 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9954107B2 (en) 2015-05-05 2018-04-24 International Business Machines Corporation Strained FinFET source drain isolation
US9607901B2 (en) * 2015-05-06 2017-03-28 Stmicroelectronics, Inc. Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FINFET technology
FR3036847A1 (fr) * 2015-05-27 2016-12-02 St Microelectronics Crolles 2 Sas Procede de realisation de transistors mos a largeur de canal augmentee, a partir d'un substrat de type soi, en particulier fdsoi, et circuit integre correspondant
US10833175B2 (en) * 2015-06-04 2020-11-10 International Business Machines Corporation Formation of dislocation-free SiGe finFET using porous silicon
US9680018B2 (en) * 2015-09-21 2017-06-13 International Business Machines Corporation Method of forming high-germanium content silicon germanium alloy fins on insulator
US9601385B1 (en) * 2016-01-27 2017-03-21 International Business Machines Corporation Method of making a dual strained channel semiconductor device
US9748404B1 (en) * 2016-02-29 2017-08-29 International Business Machines Corporation Method for fabricating a semiconductor device including gate-to-bulk substrate isolation
US9871139B2 (en) * 2016-05-23 2018-01-16 Samsung Electronics Co., Ltd. Sacrificial epitaxial gate stressors
WO2018182749A1 (en) 2017-04-01 2018-10-04 Intel Corporation Germanium-rich channel transistors including one or more dopant diffusion barrier elements
WO2020150482A1 (en) * 2019-01-16 2020-07-23 The Regents Of The University Of California Wafer bonding for embedding active regions with relaxed nanofeatures

Family Cites Families (109)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
KR930003790B1 (ko) 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
JP3202223B2 (ja) 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
JP2572003B2 (ja) 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3460863B2 (ja) 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
US5658806A (en) 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
JP3376211B2 (ja) * 1996-05-29 2003-02-10 株式会社東芝 半導体装置、半導体基板の製造方法及び半導体装置の製造方法
US5817560A (en) 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5963817A (en) * 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US6351040B1 (en) 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6252284B1 (en) 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
JP3846706B2 (ja) 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
US20020011612A1 (en) 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6716684B1 (en) 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
AU2001267880A1 (en) 2000-11-22 2002-06-03 Hitachi Ltd. Semiconductor device and method for fabricating the same
JP2002198368A (ja) 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
JP3488914B2 (ja) * 2001-01-19 2004-01-19 名古屋大学長 半導体装置製造方法
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6630388B2 (en) 2001-03-13 2003-10-07 National Institute Of Advanced Industrial Science And Technology Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
JP2002298051A (ja) 2001-03-30 2002-10-11 Mizuho Bank Ltd ポイント交換サービス・システム
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6960806B2 (en) * 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6689650B2 (en) 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
JP2003158250A (ja) * 2001-10-30 2003-05-30 Sharp Corp ＳｉＧｅ／ＳＯＩのＣＭＯＳおよびその製造方法
US20030085194A1 (en) 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
US7385262B2 (en) 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
KR100442089B1 (ko) 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) * 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6635909B2 (en) * 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
JP2004079887A (ja) * 2002-08-21 2004-03-11 Renesas Technology Corp 半導体装置
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
US6800910B2 (en) * 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
JP4546021B2 (ja) * 2002-10-02 2010-09-15 ルネサスエレクトロニクス株式会社 絶縁ゲート型電界効果型トランジスタ及び半導体装置
US6706571B1 (en) 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6611029B1 (en) 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6855990B2 (en) * 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6709982B1 (en) 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6686231B1 (en) 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
JP4418760B2 (ja) 2002-12-20 2010-02-24 インターナショナル・ビジネス・マシーンズ・コーポレーション フィン型ｆｅｔおよびｃｍｏｓデバイスのための一体化アンチヒューズ構造
US6803631B2 (en) * 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6762483B1 (en) * 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
WO2004073044A2 (en) 2003-02-13 2004-08-26 Massachusetts Institute Of Technology Finfet device and method to make same
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6828628B2 (en) 2003-03-05 2004-12-07 Agere Systems, Inc. Diffused MOS devices with strained silicon portions and methods for forming same
US6716690B1 (en) 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
JP4563652B2 (ja) 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
TWI231994B (en) * 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
JP3835759B2 (ja) * 2003-04-08 2006-10-18 株式会社日立製作所 車両外施設・車両間通信装置及び車両外施設・車両間通信システム並びに車両外施設・車両間通信装置を用いた通信方法
US6867433B2 (en) * 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
JP4105044B2 (ja) * 2003-06-13 2008-06-18 株式会社東芝 電界効果トランジスタ
US7812340B2 (en) * 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US6921982B2 (en) 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
KR100487566B1 (ko) * 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
EP1519420A2 (en) * 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6955969B2 (en) * 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance
US7183137B2 (en) 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7388258B2 (en) 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7385247B2 (en) * 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) * 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US6881635B1 (en) * 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US8450806B2 (en) * 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US7023018B2 (en) * 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US20050230763A1 (en) * 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
US8669145B2 (en) * 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7348284B2 (en) * 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
WO2006062869A1 (en) * 2004-12-07 2006-06-15 Thunderbird Technologies, Inc. Strained silicon, gate engineered fermi-fets

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102640269A (zh) * 2009-09-30 2012-08-15 苏沃塔公司 电子装置和系统及其制造和使用方法
CN102640269B (zh) * 2009-09-30 2015-08-12 苏沃塔公司 电子装置和系统及其制造和使用方法
CN103367432A (zh) * 2012-03-31 2013-10-23 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管及其制造方法
CN103367432B (zh) * 2012-03-31 2016-02-03 中芯国际集成电路制造(上海)有限公司 多栅极场效应晶体管及其制造方法
CN103515420A (zh) * 2012-06-26 2014-01-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN103515420B (zh) * 2012-06-26 2016-06-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN103413828A (zh) * 2013-07-18 2013-11-27 清华大学 多边形沟道层多栅结构隧穿晶体管及其形成方法
CN104835744A (zh) * 2014-02-11 2015-08-12 格罗方德半导体公司 具有松弛硅/锗鳍片的集成电路
CN104835744B (zh) * 2014-02-11 2018-01-12 格罗方德半导体公司 具有松弛硅/锗鳍片的集成电路
CN107210225A (zh) * 2015-01-13 2017-09-26 国际商业机器公司 pFET区域中的应变释放
CN108010880A (zh) * 2016-10-31 2018-05-08 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN111509048A (zh) * 2020-04-28 2020-08-07 上海华力集成电路制造有限公司 N型鳍式晶体管及其制造方法

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US7193279B2 (en) 2007-03-20
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US20060157794A1 (en) 2006-07-20
DE112006000229T5 (de) 2007-11-08
JP5408880B2 (ja) 2014-02-05
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US20060157687A1 (en) 2006-07-20

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