CN101145688A

CN101145688A - Electrostatic discharge protection structures with reduced latch-up risks

Info

Publication number: CN101145688A
Application number: CNA2007101494422A
Authority: CN
Inventors: 本杰明·范坎普
Original assignee: Sofics Bvba; Sarnoff Corp
Current assignee: Sofics Bvba; Sarnoff Corp
Priority date: 2006-05-23
Filing date: 2007-05-23
Publication date: 2008-03-19
Also published as: JP2007318146A

Abstract

The present invention provides an ESD protection circuitry in a semiconductor integrated circuit (IC) having protected circuitry to prevent false triggering of the ESD clamp. The circuitry includes an SCR as an ESD clamp having an anode adapted for coupling to a first voltage source, and a cathode adapted for coupling to a second voltage source. The circuitry also includes at least one noise current buffer (NCB) coupled between at least one of a first trigger tap of the SCR and the first voltage source such that the first trigger tap of the SCR is coupled to a power supply.

Description

Reduce the ESD-protection structure of latch-up risks

The cross reference of related application

The application requires the rights and interests of No. the 60/808th, 041, the U.S. Provisional Application submitted on May 23rd, 2006, herein in conjunction with its full content as a reference.

Technical field

The present invention relates generally to Electrostatic Discharge protective circuit field, relate in particular to the improvement of the false triggering that in the protective circuit of integrated circuit (IC), prevents silicon controlled rectifier (SCR) circuit.

Background technology

In the prior art,, use the voltage overshoot analogue noise in order to prevent the false triggering of ESD clamp.For voltage overshoot, use noise voltage buffer (NVB) as shown in Figure 1.Fig. 1 illustrates the schematic block diagram of the prior art of the esd protection circuit 100 of representing integrated circuit (IC).Esd protection circuit 100 comprises the ESD clamp, is connected to the SCR102 of the node 1104 of the pad of representing IC.The IC pad of node 1104 can be input pad, o pads or power pad.Node 2106 can be ground or also is i/o pads.The triggering tap G2 of SCR102 is connected to the node 3108 that can be input pad, o pads or power pad.In this example of Fig. 1, node 1104 representative input pads, on behalf of ground and node 3108, node 2 represent power supply.Noise voltage buffer (NVB) 110 is connected between the triggering tap G2 and node 3108 of SCR102.Shunt resistance R1112 is connected between SCR102 and the node 2106 alternatively.

In normal running, give node 3108 power supplies, yet at node 1104, voltage is lower than power supply, that is, there is not enough voltage to come electric current between conductive anode and the grounded cathode.Therefore, SCR102 is cut off.In order to make the SCR102 conducting, between the G2 of node 1 and SCR102, must have 0.7 volt at least.Because the input voltage at node 1104 places is lower than power supply, that is, and node 3108, so SCR102 can not trigger during the normal running.During ESD, the power supply at node 3108 places is 0 volt substantially, yet the voltage at node 1104 places is high, that is, at least 0.7 volt or higher will have voltage so, thereby cause SCR102 conducting or triggering in the G2 positive contact.The ESD electric current will flow to node 2106 through SCR102 from node 1104.

Under certain conditions, the input voltage at node 1104 places may become and be higher than power supply in the normal running, that is, and and node 3108.For example, the voltage at node 3108 places is that the voltage at 1.8 volts and node 1102 places is 2 volts or higher, and it can trigger the SCR102 conducting during normal running.Usually, the voltage that inputs or outputs node 104 places is restricted to and is lower than power supply, but voltage overshoot (noise, spiking) can cause these overvoltage.Therefore, in this case, SCR102 is not because ESD is triggered, and because import pad, that is, the high pressure at node 1104 places is triggered.The false triggering of Here it is SCR102, this is the application of not expecting in normal running.Therefore, NVB110 will reduce the voltage that produces between anode and the G2 by the series connection dividing potential drop.For example, 0.7 volt of 0.3 volt of will be divided in the G2 positive contact at node 1 place, on NVB110 0.3 volt, thereby the voltage in the restriction G2 positive contact.Therefore, NVB110 prevents that G2 from triggering SCR102 during normal running, thereby prevents that the voltage overshoot noise from can trigger SCR.

Although once attempt reducing the false triggering of SCR in the past, in the operation of normal power source line power supply, still there is the unnecessarily danger of trigger equipment by different circuit engineerings.

Description of drawings

Fig. 1 has described the diagram of block diagram of the existing techniques in realizing of esd protection circuit.

The diagram of the block diagram of the esd protection circuit that Fig. 2 has described is according to an embodiment of the invention, have the noise current buffer.

Fig. 3 has described in accordance with another embodiment of the present invention, has combined the diagram of block diagram of esd protection circuit of Fig. 2 of noise current buffer and noise voltage buffer.

Fig. 4 A has described the diagram of the block diagram of Fig. 2 according to still another embodiment of the invention, that combine noise current buffer and leakage buffers.

Fig. 4 B has described the diagram according to the block diagram of Fig. 2 alternative embodiment of the present invention, that combine noise current buffer and leakage buffers.

Fig. 4 C has described the diagram of the exemplary realization of noise current buffer according to a preferred embodiment of the invention, Fig. 4 A and leakage buffers.

Fig. 4 D has described the diagram of another exemplary realization of noise current buffer according to a preferred embodiment of the invention, Fig. 4 A and leakage buffers.

Fig. 5 A has described the diagram according to the block diagram of Fig. 2 alternative embodiment of the present invention, that combine noise current buffer and noise current surplus enhancer (noise current margin increaser).

Fig. 5 B has described the diagram of the exemplary realization of noise current buffer according to a preferred embodiment of the invention, Fig. 5 A and noise current surplus enhancer and leakage buffers.

Embodiment

In one embodiment of the invention, in being arranged, the semiconductor integrated circuit of protective circuit (IC) provides the Electrostatic Discharge protective circuit.Esd protection circuit comprises first voltage source of the protected circuit node of IC, and has the anode that is suitable for being connected to first voltage source and be suitable for being connected to the silicon controlled rectifier (SCR) of the negative electrode of second voltage source.Circuit also comprises at least one first at least one the noise current buffer (NCB) that triggers between the tap and first voltage source that is connected SCR, and wherein at least one of SCR first triggers tap and be connected to the tertiary voltage source.

The present invention simulated to prevent that SCR is owing to the not controlled current flow in the input of ESD clamp triggers between error-free running period.If in the ESD clamp, injected multiple current then it can cause pinning (latch-up).When enough electric currents flowed into the anode G2 joint of SCR102, SCR102 can trigger or conducting, and this is unfavorable to normal running.As shown in Figure 2, the false triggering problem of SCR102 solves by increase noise current buffer (NCB) 202 in esd protection circuit 200 during the normal running.Notice the triggering node placement in parallel of esd protection between the anode G2 joint of NCB202 and SCR102.Therefore, electric current is assigned in two alternate paths.

During normal running, the voltage of giving node 3108 power supplies and node 1104 places is between ground and power supply.The electric current that node 1104 places are injected will mainly flow through noise current buffer (NCB) 202, and have only very little one part of current will flow through anode G2 joint.Can not trigger SCR102 to such an extent as to this part electric current is too little.The major part of electric current can flow to node 3108.

During the ESD that himself is the electric current injector, electric current will flow through anode G2 joint and NCB202, therefore need more electric current to come conducting SCR102 (just understanding conducting SCR102 owing to have only the electric current that flows into anode G2 joint).The anode G2 joint of SCR102 is designed to the electric current of the some/level of handling during triggering.In case the level of electric current is enough high, SCR102 can conducting.During normal running, current value range is between 0mA and 100-200mA.Yet during ESD, current value can be higher, and scope is at 0A and 2-3A.Therefore, NCB202 is provided the current value of a certain critical level.Critical range is preferably from 0.1A to 0.3A.Be lower than this current value, SCR102 will not trigger, if but injection current become and be higher than this value, SCR just can trigger.

Fig. 3 has described the diagram of block diagram of the esd protection circuit 200 of Fig. 2 according to another embodiment of the present invention, that noise voltage buffer (NVB) 110 is arranged.Use the benefit of these two kinds of technology to be to carry out the ESD clamp safely to voltage overshoot/noise and to current over pulse/noise during the normal running.The operation of this circuit is equal to above-mentioned operation with reference to Fig. 1 and 2 description.

Because NCB202 may introduce high leakage current (leakage of not expecting) between node 3108 and node 1104, can preferably leakage buffers (LB) 204 be added the esd protection circuit of Fig. 2.Leakage buffers during the normal running (LB) 204 will stop the electric current between node 1104 and the node 3108 to flow.The needs of LB204 are depended on the realization of noise current buffer NCB202, that is, depend on during the normal running whether conducting of NCB202.As shown in an embodiment among Fig. 4 A, LB204 can trigger the node G2 placement of connecting with ESD, or as shown in another embodiment among Fig. 4 B, LB204 can trigger node G2 placement in parallel with ESD.

Trigger voltage among Fig. 4 A preferably includes 0.7 volt of G2 positive contact and adds in order to the voltage on the LB204 of conduction current.The benefits of among Fig. 4 B leakage buffers (LB) 204 parallel connections being placed are that the trigger voltage during the ESD does not comprise the voltage on the LB204.Therefore this will be the clamp device of better protection node 1104 also to the lower trigger voltage of clamp.Because LB204 does not connect with triggering node G2, so the trigger voltage among Fig. 4 B is 0.7 volt of the G2 positive contact, thereby trigger voltage is very low.Be used for the extra protection of voltage overshoot/noise if desired, although not shown, NVB110 can be connected between the triggering node G2 and node 3108 of esd protection circuit of Fig. 4 A and Fig. 4 B.

With reference to Fig. 4 C, the exemplary realization of noise current buffer (NCB) 202 according to a preferred embodiment of the invention, Fig. 4 A and leakage buffers (LB) 204 is shown.In this embodiment, NCB202 comprises resistance 402, and LB204 comprises diode 404.Notice that present noise immunity is 0.7V/RNCB.This value is to trigger the minimum current that SCR102 needs.If inject maximum current during the normal running, 100mA for example, the resistance that resistance 402 needs can be calculated with formula.This resistance provides the current value of a certain critical level for NCB202.Equally, when resistance during the normal running 402 conducts, diode 404 (effect is equivalent to leakage buffers 204) will stop the electric current mobile (that is leakage current) between node 1104 and the node 3108.

In addition, Fig. 4 D has described the diagram of another exemplary realization of noise current buffer (NCB) 202 according to a preferred embodiment of the invention, Fig. 4 A and leakage buffers (LB) 204.In this embodiment, LB204 comprises the diode 404 that is similar to Fig. 4 C, yet NCB202 comprises active element NMOS406.Shown in Fig. 4 C, the grid that the source electrode of NMOS406 is connected to the anode of SCR102 and NMOS406 is connected to its drain electrode, and its drain electrode further is connected to the G2 positive contact.Because the voltage at node 3108 places is less than the voltage at node 1104 places during the ESD, so the grid voltage of NMOS is little, thereby NMOS406 ends.When NMOS406 by the time, it be a high impedance, that is, a large amount of electric currents will flow through NMOS406 and and then flow into anode G2 joint, therefore easy conducting SCR102.

During normal running, the voltage at node 3108 places is higher than the voltage at node 1104 places, so the grid voltage height of NMOS406, its conducting NMOS406.When the NMOS406 conducting, it is Low ESR (ohm), that is, electric current in a small amount will flow through it and also flow into anode G2 joint.Therefore this undercurrent in a small amount stops SCR102 conducting during normal running to trigger SCR102.During normal running, the NMOS406 conducting, so electric current will flow to node 1104 from node 3108.This leakage is not expected, therefore needs LB204 to stop this leakage.Stop leakage with diode 404 in this case.During the normal running, diode is reverse, and therefore having blocked electric current flows to node 1104 from node 3108.

Although in the above-mentioned example of Fig. 4 C and Fig. 4 D, NCB202 is described to resistance and NMOS respectively, and LB204 is illustrated as diode, but should be noted that, usually they can be by any active element, as NMOS, PMOS, bipolar transistor, diode, or passive component, form as resistance, metal, inductance, electric capacity.Therefore, scope of the present invention is not limited to the use as the particular element of NCB and LB.

Because the ESD clamp is SCR102 among the embodiment as implied above, is lower than 0.7V (25 ℃) to avoid the triggering of clamp so NCB202 must operate at.Yet,, require 0.7V and Geng Gao at least in order to trigger SCR102.Therefore, if NCB202 is operated in during normal running above 0.7V, for example inciting somebody to action so shown in Fig. 5 A, another element of noise current surplus enhancer (NCMI) 502 adds esd protection circuit.Noise current surplus enhancer (NCMI) 502 is added into to improve the voltage design space of NCB202.NCMI502 placement in parallel with NCB202.If NCB202 is a resistance, for example be big resistance, trigger voltage can be promoted by NCMI502 so.Voltage on the NCB202 will be 0.7 volt of voltage that adds on the NCMI502.Therefore, need the voltage of more multiple current injection to trigger SCR102 now.By increasing this method of NCMI502, for example be the NCB202 of resistance, preferably having higher value and pin immunity to interference will be identical (with the identical electric current in the afore-mentioned).When same current was injected, the voltage on the NCB202 can be higher, but clamp, and SCR102 can not trigger, and this is because extra voltage can be added in NCMI502 goes up but not be added on the anode G2 joint., Fig. 5 A do not show that LB204 can preferably in parallel with NCMI502 or the placement of connecting although.Similarly, the NVB110 placement of can desirably connecting with NCMI502.

With reference to Fig. 5 B, illustrate the noise current buffer of Fig. 5 A according to a preferred embodiment of the invention and the exemplary realization that noise current surplus enhancer adds LB204.In this embodiment, NCB202 comprises resistance 402, and LB204 comprises diode 404, and NCMI502 also comprises diode 504.Notice that present noise immunity (maximum current) is 1.4V/RNCB.Compare with the built-in voltage (0.7V) of diode 404 in the circuit of the situation figure below 4C that does not have NCMI502, this value is doubled.This uses particularly useful to high temperature, this is because to higher temperature, the diode built-in voltage can descend (to 100 ℃ of decline 0.4V), so the voltage design space descends.

Although in the example that Fig. 5 B provides, NCMI502 and LB204 are illustrated as diode, and importantly, they can be by forming as any active element of NMOS, PMOS, bipolar transistor, diode or as the passive component of resistance, metal, inductance, electric capacity usually.Therefore, scope of the present invention is not limited to the use as the particular element of NCMI and LB.

Although specifically illustrate and described the various embodiment in conjunction with the present invention instruction here, those skilled in the art still can easily imagine many still in conjunction with these instructions but do not break away from the embodiment of other variation of spiritual scope of the present invention.

Claims

1. Electrostatic Discharge protective circuit in having the semiconductor integrated circuit of protected circuit (IC), this esd protection circuit comprises:

First voltage source of the protected circuit node of this IC;

Silicon controlled rectifier (SCR) has the negative electrode that is suitable for being connected to the anode of this first voltage source and is suitable for being connected to second voltage source; And

Be connected at least one first at least one noise circuit buffer (NCB) that triggers between tap and this first voltage source of this SCR, with described SCR described at least one first trigger tap and be connected to the tertiary voltage source.

2. esd protection circuit as claimed in claim 1, wherein said NCB is used for preventing the triggering of this SCR during normal running.

3. esd protection circuit as claimed in claim 1, wherein said NCB is a resistance.

4. esd protection circuit as claimed in claim 1, wherein said NCB is a MOS transistor.

5. esd protection circuit as claimed in claim 1, wherein said tertiary voltage source is a power supply.

6. esd protection circuit as claimed in claim 1, wherein said second voltage source is ground.

7. esd protection circuit as claimed in claim 1 also comprises: be connected the leakage buffers (LB) between this NCB and this tertiary voltage source.

8. esd protection circuit as claimed in claim 7, wherein said LB are used for preventing during the normal running that the electric current between this first voltage source and this tertiary voltage source from flowing.

9. esd protection circuit as claimed in claim 7, wherein said LB are connected in series between this at least one the first triggering tap and this tertiary voltage source of this SCR.

10. esd protection circuit as claimed in claim 7, described at least one first triggering tap of wherein said LB and described SCR and this first voltage source are connected in first of described NCB and this SCR in parallel and trigger between the tap.

11. esd protection circuit as claimed in claim 7, wherein said LB is a diode.

12. as the esd protection circuit of claim 11, wherein said diode oppositely is connected with this NCB with this tertiary voltage source.

13. esd protection circuit as claimed in claim 1 also comprises: with described SCR described at least one first trigger the noise current surplus enhancer (NCMI) that tap and this tertiary voltage source are connected in series.

14. as the esd protection circuit of claim 13, wherein said NCMI is used to improve the voltage design space of this NCB.

15. as the esd protection circuit of claim 13, wherein said NCB and NCMI are connected in parallel.

16. as the esd protection circuit of claim 13, wherein said NCMI is a diode.

17. esd protection circuit as claimed in claim 1 also comprises: described at least one the first noise voltage buffer (NVB) that triggers between tap and this tertiary voltage source that is connected described SCR.