CN101189730A - 具有增强迁移率的应变沟道的非平面体晶体管及制造方法 - Google Patents

具有增强迁移率的应变沟道的非平面体晶体管及制造方法 Download PDF

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CN101189730A
CN101189730A CNA200580009823XA CN200580009823A CN101189730A CN 101189730 A CN101189730 A CN 101189730A CN A200580009823X A CNA200580009823X A CN A200580009823XA CN 200580009823 A CN200580009823 A CN 200580009823A CN 101189730 A CN101189730 A CN 101189730A
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N·林德尔特
S·M·切亚
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Abstract

一种具有应变增强迁移率的三栅极体晶体管及其制造方法。本发明是一种具有应变增强迁移率的非平面晶体管及其制造方法。所述晶体管具有在半导体基片上形成的半导体主体，其中半导体主体具有侧向相对的侧壁上的顶面。在半导体主体的顶面和侧壁上形成半导体覆盖层。在半导体主体顶面上的半导体覆盖层上形成栅极绝缘层，并且在半导体主体的侧壁上的覆盖层上形成栅极绝缘层。在栅极绝缘层上及其周围形成具有一对侧向相对的侧壁的栅极电极。在栅极电极的相对的两侧，在半导体主体内形成一对源极/漏极区域。

Description

具有增强迁移率的应变沟道的非平面体晶体管及制造方法
发明背景
1.发明领域
本发明涉及集成电路制造领域，更具体地说，涉及应变增强迁移率的非平面体晶体管的构成及其制造方法。
2.先有技术讨论
现代集成电路，诸如微处理器，是由数亿个耦合在一起的晶体管构成的。为了改善集成电路的性能和能力，已经提出了一些新的晶体管结构。为了改善器件的性能，有人提出了非平面晶体管，诸如三栅极晶体管。在图1A和1B中，图解说明三栅极晶体管100。图1A是三栅极晶体管100的俯视/侧视图的例图，而图1B是穿过三栅极晶体管100的栅极截取的剖面图的例图。三栅极晶体管100包括硅体102，硅体102具有一对侧向相对的侧壁103和顶面104。硅体102形成在包括氧化层106的绝缘基片上，氧化层106本身形成在单晶硅基片108上。栅极绝缘层110形成在硅体102的顶面104上和侧壁103上。栅极120形成在栅极绝缘层110上并包围硅体102。一对源极/漏极区域130形成在硅体102内沿着栅极120的侧向相对的侧壁。晶体管130可以说是三栅极晶体管，因为它本质上具有3个栅极(G1，G2，G3)，3个栅极(G1，G2，G3)本质上形成3个晶体管。三栅极晶体管100在硅体102的一侧103上具有第一栅极/晶体管，在硅体102的顶面104上具有第二栅极/晶体管和在硅体102的第二侧103上具有第三栅极/晶体管。每一个晶体管都提供与硅体102的侧面成正比的电流。三栅极晶体管具有吸引力，因为它们的单位面积的电流大，这提高了器件的性能。
附图的简短说明
图1A表示标准三栅极晶体管的俯视图；
图1B表示标准三栅极晶体管的剖面图；
图2是按照本发明的实施例具有应变诱生迁移率的三栅极体晶体管的例图；
图3A-3I图解说明按照本发明实施例形成具有应变增强迁移率的三栅极体晶体管的方法；
图4A-4C图解说明按照本发明实施例形成具有应变增强迁移率的三栅极体晶体管的方法；以及
图5图解说明硅块、应变硅锗半导体主体和应变硅覆盖层的晶格。
发明的详细说明
本发明的实施例是具有应变增强迁移率的非平面体晶体管及其制造方法。在以下描述中，提出了许多具体细节以便对本发明提供透彻的理解。为了避免不必要地使本发明模糊不清，在其他实例中，对众所周知的半导体处理和制造技术不再提出具体的细节。
本发明的实施例是具有应变增强迁移率的非平面体晶体管及其制造方法。本发明的实施例包括半导体主体，它使在半导体主体上形成或包围它的覆盖层处于应变之下。处于应变下的覆盖层增大器件中载流子的迁移率，这增大了器件的电流，从而可以用来改善电路速度。
图2中图解说明具有应变增强迁移率的非平面或三栅极体晶体管200的示例。晶体管200形成在体半导体基片202上。在本发明的实施例中，基片202是单晶硅基片。在半导体基片202中形成的是一对彼此隔开的隔离区204，诸如浅沟槽隔离(STI)区，所述隔离区限定它们之间的基片的有源区206。但是，基片202不必是硅单晶基片而可以是其它类型的基片，诸如(但不限于)锗(Ge)、硅锗(SixGey)、砷化镓(GaAs)，InSb，GaP和GaSb。对于n型器件，有源区206一般掺杂到1×1016至1×1019原子/cm3之间的p型导电级，而对于p型器件，则掺杂至1×1016与1×1019原子/cm3之间的n型导电级。在本发明的其他实施例中，有源区206可以是未掺杂的半导体、诸如本征或未掺杂的硅单晶基片。
晶体管200具有在体基片202的有源基片区206上形成的半导体主体208。半导体主体208具有顶面209和一对侧向相对的侧壁211。顶面209和在半导体基片206上形成的底部表面相隔一个定义体高度的距离。半导体主体208的侧向相对的侧壁211彼此隔开定义所述体宽度的距离。半导体主体208是单晶半导体薄膜。在本发明的实施例中，半导体主体208是由不同于用于形成体基片202的半导体的半导体材料形成。在本发明的实施例中，半导体主体208是由具有不同于体半导体基片202的晶格常数或尺寸的单晶半导体形成的，使得半导体主体208被置于应变之下。在本发明的实施例中，体半导体基片是单晶硅基片，而半导体主体208是单晶的硅-锗合金。在本发明的实施例中，硅锗合金包括5-40％之间的锗，而理想的是，大约15-25％之间的锗。
在本发明的实施例中，体半导体基片202是单晶硅基片，而半导体主体208是硅碳合金。
在本发明的实施例中，这样形成体半导体208，使得其厚度小于半导体主体208的外表面将导致晶格弛豫的数量。在本发明的实施例中，半导体主体208形成得其厚度在100-2000
Figure A20058000982300101
之间，更具体地说，在200-1000
Figure A20058000982300102
之间。在本发明的实施例中，半导体主体208的厚度和高度大约相同。
在本发明的实施例中，半导体主体208的宽度是体208高度一半至体208高度两倍之间。在本发明的实施例中，对于n型半导体器件，半导体主体208掺杂为浓度在1×1016至1×1019原子/cm3之间的p型导电性，而对于p半导体器件型，掺杂为浓度在1×1016至1×1019原子/cm3之间的n型导电性。在本发明的实施例中，半导体主体208是本征半导体，诸如未掺杂的或本征硅薄膜。
晶体管200包括在半导体主体208的侧壁211上以及在半导体主体208的顶面209上形成的半导体覆盖层210。半导体覆盖层210是单晶半导体薄膜。在本发明的实施例中，半导体覆盖层210是由具有不同于半导体主体208的晶格常数的半导体材料形成的，使得在覆盖层中形成应变。在本发明的实施例中，覆盖层具有拉伸应变。拉伸应变被认为改善了电子的迁移率。在本发明的实施例中，覆盖层具有压缩应变。压缩应变被认为改善了空穴的迁移率。在本发明的实施例中，电流在覆盖层210中在垂直于应变的方向上流动。在本发明的实施例中，半导体主体208的侧壁211上的覆盖层210中的应变大于半导体主体208的顶面209上的覆盖层210中的应变。
在本发明的实施例中，半导体覆盖层210是单晶硅薄膜。在本发明的实施例中，覆盖层210是在硅-锗合金体208上形成的单晶硅薄膜。在硅-锗合金半导体主体208上形成的单晶硅薄膜将使单晶硅薄膜具有拉应力。在本发明的实施例中，覆盖层210是在硅碳合金半导体主体208上形成的单晶硅薄膜。在硅碳合金半导体主体208上形成的单晶硅覆盖层210将使单晶硅薄膜210具有压应力。
在本发明的实施例中，这样形成半导体覆盖层210，使得其厚度小于使单晶薄膜的晶格弛豫的数量。在本发明的实施例中，这样形成半导体覆盖层210，使得其厚度在50-300
Figure A20058000982300111
之间。在本发明的实施例中，半导体主体208侧壁211上的覆盖层的厚度与半导体主体208的顶面209上的覆盖层210的厚度相同，如在图2图解说明的。在本发明的实施例中，这样形成半导体覆盖层210，使得半导体主体208顶面上的厚度大于侧壁211上的厚度，例如，在图4C中所表示的。
晶体管200包括栅极绝缘层212。在形成于半导体主体208的侧壁211上的覆盖层210上形成栅极绝缘层212，并在形成于半导体主体208的顶面209上的半导体覆盖层210上形成栅极绝缘层212。栅极绝缘层210可以是任何众所周知的栅极绝缘层。在本发明的实施例中，栅极绝缘层是二氧化硅(SiO2)、氮氧化硅(SiOxNy)或氮化硅(Si3N4)绝缘层。在本发明的实施例中，栅极绝缘层212是氮氧化硅薄膜，其厚度在5-20
Figure A20058000982300121
之间。在本发明的实施例中，栅极绝缘层212是高K栅极绝缘层，诸如金属氧化物电介质，诸如(但不限于)五氧化钽(Ta2O5)、氧化钛(TiO2)、氧化铪(HfO)和氧化锆(ZrO)。但是，栅极绝缘层212可以是其它类型的高K电介质，诸如(但不限于)PZT和BST。
晶体管200包括栅极214。在栅极绝缘层212上并围绕它形成栅极214，如图2所示。在形成于半导体主体208的侧壁211上的覆盖层210上形成的栅极绝缘层212上及其附近形成栅极214，并且在形成于半导体主体208的顶面209上的覆盖层210上形成的栅极绝缘层212上形成栅极214，并且在形成于栅极电极208的侧壁211上的覆盖层210上形成的栅极绝缘层212上或其附近形成栅极214，如图2所示。栅极214具有一对侧向相对的侧壁216，所述一对侧向相对的侧壁216隔开定义晶体管200的栅极长度(Lg)的距离。在本发明的实施例中，栅极214的侧向相对的侧壁216在垂直于半导体主体208的侧向相对的侧壁211的方向延伸。栅极214可以由任何适当的栅极材料形成。在本发明的实施例中，栅极214包括掺杂至浓度在1×1019至1×1020原子/cm3之间的多晶硅薄膜。对于n型器件，栅极214可以掺杂为n型导电性，而对于p型器件，掺杂为p型导电性。在本发明的实施例中，栅极可以是金属栅极。在本发明的实施例中，栅极214由金属薄膜形成，所述金属薄膜具有适合于(tailored for)n型器件的逸出功，诸如3.9电子伏至4.2电子伏之间的逸出功。在本发明的实施例中，栅极214由金属薄膜形成，所述金属薄膜具有适合于(tailored for)p型器件的逸出功，诸如4.9电子伏至5.2电子伏之间的逸出功。在本发明的实施例中，栅极214由具有4.6至4.8电子伏之间的中间能阶(midgap)逸出功的材料形成。中间能阶逸出功对当半导体主体208和覆盖层210是本征半导体薄膜时的应用是理想的。下面将指出，栅极214不必是单一材料的，可以是薄膜组合堆叠，诸如(但不限于)多晶硅/金属电极或金属多晶硅电极。
晶体管200具有一对在半导体主体208上以及在栅极214的侧向相对的侧壁216的相对的两侧上的覆盖层上形成的源极/漏极区域，如图2所示。当形成n型器件时，源极/漏极区域218掺杂为n型导电性，而当形成p型器件时，掺杂为p型导电性。在本发明的实施例中，源极/漏极区域具有1×1019至1×1021原子/cm3之间的掺杂浓度。源极/漏极区域218可以由均匀的浓度形成，或者可以包括不同浓度的或不同掺杂分布的子区域，诸如触点(tip)区域(例如，源极/漏极扩展)。在本发明的实施例中，当晶体管200是对称的晶体管时，源极和漏极区域将具有相同的掺杂浓度分布。在本发明的实施例中，晶体管200是不对称晶体管，源极区域和漏极区域可以改变，以便获得特定的电气特性。
半导体主体208和覆盖层210的位于源极/漏极区域216之间并且在栅极214之下的所述部分形成晶体管的沟道区域。所述沟道区域也可以定义为半导体主体208和覆盖层210的被栅极214包围的区域。源极/漏极区域一般通过例如扩散略微扩展到栅极下面，以便形成略微小于栅极长度(Lg)的沟道区域。当晶体管300”导通”时，在器件的沟道区域中形成反型层，所述反型层形成导电沟道，使电流能够在源极/漏极区域340之间流动。在半导体主体208的侧壁211上的覆盖层表面上以及在半导体主体208的顶面209上的覆盖层的表面上形成反型层或导电沟道。
通过提供在3个侧面上包围半导体主体208和覆盖层210的栅极绝缘层212和栅极214，所述非平面晶体管具有以下特征：所述非平面晶体管具有3个沟道和3个栅极，其中一个栅极(G1)延伸在半导体主体208的一个侧面211上的源极/漏极区域之间，第二栅极(G2)延伸在半导体主体208的顶面209上的源极/漏极区域之间，而第三栅极(G3)延伸在半导体主体208的侧壁211上的源极/漏极区域之间。晶体管200的栅极的″宽度″(Gw)是3个沟道区域的和。就是说，晶体管200的栅极宽度等于半导体主体208的高度加上侧壁211的顶面上覆盖层的厚度、加上半导体主体208的宽度、加上半导体主体的两侧211中的每一侧上覆盖层的厚度、加上半导体主体208的顶面209上覆盖层210的厚度。可以利用由单个栅极包围的多个半导体主体208和覆盖层获得″宽度″较大的晶体管，诸如在图3I中图解说明的。
尽管在图2中图解说明了三栅极晶体管200，但是本发明同样地可以应用于其它非平面晶体管。例如，本发明可以应用于″finfet″或双栅极晶体管或仅仅在半导体主体的相对的两侧上形成两个栅极。另外，本发明可应用于″omega″栅极或环绕栅极器件，其中栅极环绕半导体主体以及在半导体主体的一部分的下面。可以通过包括在半导体主体208上形成的覆盖层210来改善″finfet″器件和″omega″器件的性能，并以此增强器件内载流子的迁移率。下面将指出，非平面器件是一种这样的器件，当”导通”时，在垂直于基片平面的方向上形式导电沟道或导电沟道的一部分。非平面晶体管也可以是一种这样的器件，其中既在水平方向又在垂直方向形成导电沟道区域。
图3A-3I图解说明按照本发明实施例的具有应变增强迁移率的非平面体晶体管的形成方法。首先，如图3A所示，提供半导体基片300。在本发明的实施例中，半导体基片300是单晶硅基片。基片300不必是硅基片，而可以是其它类型的基片，诸如硅锗基片、锗基片、硅锗合金、砷化镓、InSb和GaP。在本发明的实施例中，半导体基片300是本征(亦即，未掺杂的)硅基片。在本发明的其他实施例中，半导体基片300掺杂至浓度在1×1016至1×1019原子/cm3之间的p型导电性或n型导电性。接着，在基片300上形成具有掩模部分302的掩模，所述掩模部分302用于形成各隔离区，如图3A所示。在本发明的实施例中，所述掩模是抗氧化掩模。在本发明的实施例中，掩模部分302包括薄的衬垫氧化层304和较厚的氮化硅或抗氧化层306。掩模部分302在基片300限定要在其中形成晶体管体的有源区308。掩模部分302可以通过淀积衬垫氧化层，然后在基片300上面形成衬垫氮化硅层而形成。接着，使用众所周知的光刻法技术，对要在其中形成掩模部分302的位置上面的光刻胶掩模层进行遮蔽、曝光和显影。然后与所形成的光刻胶掩模对准，蚀刻氮化物薄膜306和衬垫氧化层304，以便形成掩模部分302，如图3A所示。
在本发明的实施例中，掩模部分302具有宽度(W1)，宽度(W1)是最小宽度或最小特征尺寸(亦即，关键尺寸(CD))，可以在制造晶体管时利用光刻法来形成宽度(W1)。另外，在本发明的实施例中，各掩模部分302彼此隔开距离D1，距离D1是在制造过程中可以利用光刻法限定的最小距离。就是说，掩模部分302具有可以是可靠的并能利用制造晶体管用的光刻法处理达到的最小尺寸并彼此隔开最小尺寸(亦即，关键尺寸)。这样，将掩模部分302定义为具有能够利用制造晶体管用的光刻工艺过程实现的最小尺寸和最大密度。
在本发明的实施例中，掩模部分302具有厚度(T1)，所述厚度(T1)等于或大于随后形成的半导体主体所要求的厚度或高度。
接着，如图3B所示，以与掩模部分302的外边缘对齐的方式蚀刻半导体300的各曝露部分，以便形成沟槽开口310。将所述沟槽开口蚀刻到足以将相邻的晶体管彼此隔离的深度。
接着，如图3C所示，用绝缘层312填充沟槽，以便在基片300中形成浅沟槽隔离(STI)区域312。在本发明的实施例中，所述绝缘层是通过首先在沟槽310的侧壁底部生长薄的衬垫氧化物而形成的。接着，例如，通过利用高密度等离子体(HDP)化学气相淀积处理，在衬垫氧化物上面覆盖淀积氧化物绝缘层，来填充沟槽312。还将在掩模部分302的顶部上形成填充绝缘层。然后可以通过例如化学机械抛光从掩模部分302的顶部除去填充绝缘层。继续所述化学机械抛光处理直到掩模部分302的顶面露出，使浅槽隔离区312的顶面基本上与掩模部分302的顶面同平面为止，如图3C所示。
尽管浅槽隔离区用于本发明是理想的，但是也可以利用其它众所周知的隔离区和技术，诸如硅的局部氧化(LOCOS)或凹槽LOCOS。
接着，如图3D所示，从基片300除去掩模部分302，以便形成半导体主体开口314。首先，利用蚀刻剂除去氮化硅部分306，所述蚀刻剂把抗氧化部分或氮化硅部分306蚀刻掉，而基本上不蚀刻隔离区312。除去氮化硅部分306之后，除去衬垫氧化物部分304。例如，可以利用包括氟氢酸(HF)的湿蚀刻剂除去衬垫氧化物部分304。除去掩模部分302形成具有基本上垂直的侧壁的半导体主体开口或沟槽314。所述垂直侧壁使半导体主体能够在沟槽内生长，并限于其中，以便能够形成带有几乎垂直的侧壁的半导体主体。
接着，如图3E所示，在开口314中形成半导体主体薄膜316，如图3E所示。在本发明的实施例中，半导体主体薄膜316是外延半导体薄膜。在本发明的实施例中，当需要应变增强半导体器件时，由单晶半导体薄膜形成半导体薄膜，所述单晶半导体薄膜具有与在其上生长该单晶半导体薄膜的底层半导体基片的不同的晶格常数或不同的晶格尺寸，使得所述半导体薄膜处于应变下。在本发明的实施例中，单晶硅薄膜316具有比底层半导体基片300大的晶格常数或晶格尺寸。在本发明的实施例中，单晶半导体薄膜316具有比底层半导体基片300小的晶格尺寸或常数。
在本发明的实施例中，半导体薄膜316是在硅单晶基片300上选择性地生长的外延硅锗合金薄膜。可以利用包括二氯硅烷(DCS)、H2、锗烷(GeH4)和HCI的淀积气体选择性地在外延反应器中生长硅锗合金。在本发明的实施例中，硅锗合金包括5-40％之间的锗，而理想的是15-25％之间的锗。在本发明的实施例中，外延半导体薄膜316是在硅基片300上形成的单晶硅碳合金。把单晶半导体薄膜316淀积至半导体主体的厚度所要求的厚度。在本发明的实施例中，把单晶半导体薄膜316生长或淀积至小于隔离区312顶面的高度的厚度。这样，隔离区312限定沟槽内的半导体薄膜316，使得形成带有几乎垂直侧壁的半导体薄膜。作为另一方案，可以在基片300上面覆盖淀积包括沟槽314内和隔离区312顶部上的半导体薄膜316，然后对其进行深抛光(polish back)，以便从隔离区顶部除去半导体薄膜316，只剩下在沟槽314内的半导体薄膜316，如图3E所示。
在本发明的实施例中，半导体薄膜316是未掺杂的或本征半导体薄膜。在本发明的实施例中，制造p型器件时，把半导体薄膜316掺杂至浓度在1×1016至1×1019原子/cm3之间的n型导电性。在本发明的实施例中，制造n型器件时，把半导体薄膜316掺杂至浓度在1×1016至1×1019原子/cm3之间的p型导电性。可以在″原位″处理中的淀积过程中通过在淀积处理气体混合物中包括掺杂剂气体来对半导体薄膜316进行掺杂。作为另一方案，可以随后通过例如离子注入或热扩散来对半导体薄膜316进行掺杂，以便形成掺杂半导体薄膜316。
接着，深蚀刻隔离区312或使之凹进，以便暴露半导体薄膜316的侧壁320，并以此形成半导体主体318，如图3F所示。半导体主体318具有几乎垂直的侧壁320，因为在淀积过程中半导体薄膜316侧向被隔离区312限制。利用不明显蚀刻半导体薄膜316的蚀刻剂深蚀刻隔离区312。当半导体薄膜316是硅或硅合金时，可以利用包括HF的湿蚀刻剂使隔离区312凹进。在本发明的实施例中，深蚀刻隔离区至这样一个水平，使得它们基本上与在半导体基片300上形成的有源区308的顶面同平面，如图3F所示。
接着，如图3G所示，在半导体主体318的顶面319和侧壁320上形成半导体覆盖层322。半导体覆盖层322是单晶半导体薄膜。在本发明的实施例中，半导体覆盖层322是由具有不同于半导体主体318的晶格常数或尺寸的材料形成的。在本发明的实施例中，半导体覆盖层322是单晶硅薄膜。在本发明的实施例中，半导体覆盖层322是在硅锗合金体318上形成的单晶硅薄膜。在本发明的实施例中，半导体覆盖层322是在硅碳合金半导体主体318上形成的单晶硅薄膜。可以利用包括DCS、HCI和H2的处理气体选择性地在外延淀积反应器中淀积单晶硅覆盖层322。在本发明的实施例中，这样形成半导体覆盖层322，使得其厚度小于在半导体覆盖层322内导致显著弛豫的数量。在本发明的实施例中，这样形成半导体覆盖层322，使得其厚度在晶体管”导通”时足以在覆盖层内形成整个反型层。在本发明的实施例中，这样形成半导体覆盖层322，使得其厚度在50-300
Figure A20058000982300181
之间。在本发明的实施例中，半导体覆盖层322是未掺杂的或本征半导体薄膜。在本发明的实施例中，在形成p型器件时把半导体覆盖层322掺杂成1×1016至1×1019原子/cm3之间的n型导电性，而当形成n型器件时，掺杂至1×1016至1×1019原子/cm3之间的p型导电性。在本发明的实施例中，半导体覆盖层322在原位淀积处理中掺杂。作为另一方案，可以通过其它众所周知的技术，诸如通过离子注入或固态源扩散来对覆盖层322进行掺杂。
接着，如图3H所示，在形成于半导体主体318的侧壁320上的覆盖层322上形成栅极绝缘薄膜324，并且在形成于半导体主体318的顶面319上覆盖层322上形成栅极绝缘薄膜324，如图3H所示。在本发明的实施例中，栅极绝缘层324是生长栅极绝缘层，诸如(但不限于)二氧化硅层、氮氧化硅层或它们的组合。可以利用众所周知的干/湿氧化处理在半导体覆盖层上生长氧化硅或氮氧化硅层。当生长栅极绝缘层324时，将仅仅在包含诸如覆盖层322等区域的半导体上而不在隔离区312上形成栅极绝缘层324。作为另一方案，栅极绝缘层324可以是淀积绝缘层。在本发明的实施例中，栅极绝缘层324是高K栅极绝缘层，诸如金属氧化物绝缘层，诸如(但不限于)氧化铪、氧化锆、氧化钽和氧化钛。可以通过众所周知的技术(诸如化学气相淀积或溅射淀积)淀积高K氧化物绝缘层。当淀积栅极绝缘层324时，还将在隔离区312上形成栅极绝缘层324。
接着，如图3H所示，在基片300上面覆盖淀积栅极材料326，使得栅极材料326淀积在栅极绝缘层324上并围绕栅极绝缘层324。就是说，在形成于半导体主体318的顶面上的覆盖层322上形成的栅极绝缘层324上淀积所述栅极材料，并且在形成于半导体主体318的侧壁320上的覆盖层322上或其附近形成所述栅极材料。在本发明的实施例中，栅极材料326是多晶硅。在本发明的实施例中，栅极材料326是金属薄膜。在本发明的实施例中，栅极材料326是具有适合于n型器件的逸出功的金属薄膜，而在本发明的实施例中，栅极材料是具有适合于p型器件的逸出功的金属薄膜。这样形成栅极材料326，使得其厚度足以完全覆盖或包围半导体主体318、覆盖层322和栅极绝缘层324，如图3H所示。
接着，如图3I所示，通过众所周知的技术使栅极材料326和栅极绝缘层324具有图案，以便形成栅极电极330和栅极绝缘层328。可以利用众所周知光刻法和蚀刻技术使栅极材料326和栅极绝缘层324具有图案。栅极电极330具有一对侧向相对的侧壁332，它们定义所述器件的栅极长度。在本发明的实施例中，侧向相对的侧壁332在垂直于半导体主体318的方向上延伸。尽管图中示出用于形成栅极电极330的腐蚀法，但是其它众所周知的技术，诸如置换栅极处理都可以用来形成栅极电极330。
接着，还如图3I所示，在栅极电极330的相对的两侧，在覆盖层332和半导体主体318中形成一对源极/漏极区域340。形成n型器件时，可以把源极/漏极区域形成为具有1×1020至1×1021原子/cm3之间浓度的n型导电性。在本发明的实施例中，形成p型器件时，可以把源极/漏极区域形成为具有1×1020至1×1021原子/cm3之间浓度的p型导电性。任何众所周知的技术，诸如离子注入或热扩散，都可以用来形成源极/漏极区域。使用离子注入时，栅极电极可以用来把晶体管的沟道区域与离子注入处理隔开，从而使源极/漏极区域340与栅极电极330自对准。另外，必要时源极/漏极区域可以包括子区域，诸如源极/漏极扩展和源极/漏极触点区域。包括垫片形成的众所周知的工艺过程可以用来形成所述子区域。另外，必要时可以在源极/漏极区域340上和在栅极电极330的顶部上形成硅化物，以便进一步减小电接触电阻。这便完成了具有应变增强迁移率的非平面体晶体管的制造。
众所周知的″后端″技术可以用来形成金属触点、金属化层和夹层介质，以便使不同的晶体管互联在一起，变成功能集成电路，诸如微处理器。
本发明宝贵的方面是覆盖层增大了晶体管的栅极宽度。这样，可以用最小特征尺寸和间隔来形成半导体主体，然后可以在按最小尺寸限定的半导体主体上并围绕它形成覆盖层，以便增大器件的栅极宽度。这增大了器件的单位面积的电流，改善器件的性能。在按最小尺寸限定和隔开的特征上形成覆盖层把按最小尺寸彼此隔开的所述主体之间的距离减小到小于所述关键尺寸或者小于利用用来形成所述器件的光刻工艺过程可实现的尺寸。这样，覆盖层的形成使每一个半导体主体能够实现较大的栅极宽度，同时仍旧利用所述最小关键尺寸(CD)和间隔来限定所述主体。利用覆盖层来增大栅极宽度即使在不要求或要求应力增强迁移率的用途上也是宝贵的。本发明的实施例本身包括这样的用途，例如，其中在以最小尺寸彼此隔开的硅主体上形成硅覆盖层，以便增大所制造的晶体管的栅极宽度。另外，使用覆盖层来增大单位面积的栅极宽度在非体器件中，诸如在绝缘的基片(诸如在绝缘体基外延硅(SOI)基片)上形成的三栅极或非平面器件中也是有用的。
在本发明各实施例中，半导体薄膜的堆叠(亦即，体半导体300、半导体主体318和覆盖层322)是设计来在覆盖层322中产生高应变的，这使载流子迁移率激烈增大。图5图解说明块硅单晶硅基片、硅锗合金半导体主体320和硅覆盖层322如何可以在硅覆盖层322中产生高的拉应力。当在单晶基片300(图3E)上生长外延硅锗合金薄膜316时，硅锗薄膜318的平行于硅单晶基片300的表面的平面502的晶格常数与体硅基片300的硅晶格匹配。由于硅锗外延薄膜316的四边形畸变的缘故，硅锗合金316的垂直于硅基片表面的平面504的晶格常数大于与硅基片300平行的平面502。一旦使隔离区312凹进(图3F)以便形成硅锗体318，顶部319上的硅锗晶格将膨胀，而两侧上的晶格常数将由于自由表面的存在而收缩。一般，硅锗合金318的侧壁320上的晶格常数将大于硅锗合金的顶面319上的晶格常数，这将大于硅单晶基片上硅锗合金的晶格常数。当在应变硅锗合金(图3G)上生长硅覆盖层322时，硅锗合金318将把它的延长的垂直晶胞尺寸504强制加在硅覆盖层322已经较小的晶胞尺寸上，在SiGe主体318的侧壁上产生正交的应变硅覆盖层322。因而，在硅锗合金的侧壁322上形成的硅覆盖层将呈现相当大的拉伸应变和在硅锗合金的顶面319上较低的但是显著的拉伸应变。在硅覆盖层322产生的应变是在垂直于流入器件的电流的方向上的。
图4A-4C图解说明形成具有应变增强迁移率的非平面体晶体管的方法，其中这样形成覆盖层，使得在半导体主体的顶面上比在侧壁上厚。如在图4A图解说明的，在隔离区312之间生长半导体主体薄膜316，如参照图3E所描述的。但是，在所述实施例中，在使隔离区312凹陷之前在半导体主体316上生长覆盖层的第一部分410。在本发明的实施例中，形成比半导体主体318所需的厚的氮化硅层306，以便提供附加的空间，使得能够在沟槽310内生长半导体覆盖层的第一部分410。这样，可以把覆盖层410的第一部分限制在隔离区312内。形成覆盖层的第一部分410之后，使隔离区312凹进，如上面所描述的，以便形成具有在顶面上形成的覆盖层410的半导体主体318，如图4B所示。接着，如图4C所示，在半导体主体318的侧壁320上并且在形成于半导体主体320的顶面319上的覆盖层的第一部分410上生长所述覆盖层的第二部分412。在本发明的实施例中，这样形成半导体覆盖层410，使得其厚度基本上等于覆盖层412的第二部分的厚度。这样，当形成基本上正方形的半导体主体318时，半导体主体318加上覆盖层将仍旧提供一个基本上正方形的覆盖体。接着，如在图3H和31图解说明的，可以继续进行处理，以便完成具有应变增强迁移率的非平面体晶体管的制造。

Claims (42)

1.一种半导体器件包括：
半导体基片上的半导体主体，所述半导体主体具有顶面和侧向相对的侧壁；
半导体覆盖层，它形成在所述半导体主体的所述顶面上和所述侧壁上；
栅极绝缘层，它形成在所述半导体主体的所述顶面和所述侧壁上的所述半导体覆盖层上；
栅极电极，它具有在所述栅极绝缘层上并围绕所述栅极绝缘层而形成的一对侧向相对的侧壁；以及
在所述栅极电极的相对的两侧上，在所述半导体主体内形成的一对源极/漏极区域。
2.如权利要求1所述的半导体器件，其中所述半导体覆盖层具有拉应力。
3.如权利要求2所述的半导体器件，其中所述半导体覆盖层在所述半导体主体的所述侧壁上具有比在所述半导体主体的所述顶面上大的拉应力。
4.如权利要求2所述的半导体器件，其中所述源极/漏极区域具有n型导电性。
5.如权利要求1所述的半导体器件，其中所述半导体基片是硅基片，其中所述半导体主体是硅锗合金，并且其中所述半导体覆盖层是硅薄膜。
6.如权利要求1所述的半导体器件，其中所述半导体覆盖层具有压应力。
7.如权利要求6所述的半导体器件，其中所述半导体覆盖层在所述半导体主体的所述侧面上具有比在所述顶面上大的压应力。
8.如权利要求6所述的半导体器件，其中所述半导体基片是单晶硅基片，其中所述半导体主体包括硅碳合金，并且其中所述半导体覆盖层是硅薄膜。
9.如权利要求1所述的半导体器件，其中所述半导体基片是硅基片，其中所述半导体主体是硅体，并且其中所述半导体覆盖层是硅覆盖层。
10.一种半导体器件包括；
硅锗体，它形成在硅单晶基片上，所述硅锗体具有顶面和一对侧向相对的侧壁；
硅薄膜，它形成在所述硅锗体的所述顶面和所述侧壁上；
栅极绝缘层，它形成在所述半导体主体的所述顶面上的所述硅薄膜上和所述半导体主体的所述侧壁上的所述硅薄膜上；
栅极电极，它具有在所述栅极绝缘层上并围绕所述栅极绝缘层而形成的一对侧向相对的侧壁；以及
在所述栅极电极的相对的两侧上，在所述半导体主体内形成的一对源极/漏极区域。
11.如权利要求10所述的半导体器件，其中这样形成所述硅薄膜，使得所述硅薄膜在所述半导体主体的顶面上比在所述半导体主体侧壁上厚。
12.如权利要求10所述的半导体器件，其中所述硅薄膜具有
Figure A2005800098230003C1
之间的厚度。
13.如权利要求10所述的半导体器件，其中所述硅锗合金包括5-40％之间的锗。
14.如权利要求13所述的半导体器件，其中所述硅锗合金包括大约15-25％的锗。
15.如权利要求10所述的半导体器件，其中所述源极/漏极区域具有n型导电性。
16.一种半导体器件包括：
硅碳合金体，它形成在硅单晶基片上，所述硅碳合金体具有顶面和一对侧向相对的侧壁；
硅薄膜，它形成在所述硅碳合金体的所述顶面和所述侧壁上；
栅极绝缘层，它形成在所述硅碳合金体的所述顶面的所述硅薄膜上和所述硅碳合金体的所述侧壁上的所述硅薄膜上；
栅极电极，它具有在所述栅极绝缘层上并且围绕所述栅极绝缘层而形成的一对侧向相对的侧壁；以及
在所述栅极电极的相对的两侧，在所述半导体主体内形成的一对源极/漏极区域。
17.如权利要求16所述的半导体器件，其中将所述硅薄膜形成到之间的厚度。
18.如权利要求17所述的半导体器件，其中所述硅薄膜具有
Figure A2005800098230004C2
之间的厚度。
19.如权利要求16所述的半导体器件，其中所述源极/漏极区域具有p型导电性。
20.一种形成半导体器件的方法包括：
在半导体基片中形成一对隔离区，所述一对隔离区在所述半导体基片中在所述一对隔离区之间限定有源基片区，所述隔离区延伸在所述基片上面；
在所述半导体基片的所述有源区上，在所述一对隔离区之间形成半导体薄膜；
对所述隔离区进行深蚀刻，以便由所述半导体薄膜形成半导体主体，其中所述半导体主体具有顶面和一对侧向相对的侧壁；
在所述半导体主体的所述顶面和所述侧壁上形成半导体覆盖层；
在形成于所述半导体主体的所述顶面的所述侧壁上的所述覆盖层上面形成栅极绝缘层；
形成栅极电极，所述栅极电极具有在所述栅极绝缘层上并围绕所述栅极绝缘层的一对侧向相对的侧壁；以及
在所述栅极电极的相对的两侧，在所述半导体主体内形成一对源极/漏极区域。
21.如权利要求20所述的方法，其中所述半导体薄膜是选择性地从所述半导体基片的所述有源区生长的。
22.如权利要求20所述的方法，其中所述覆盖层是选择性地从所述半导体主体生长的。
23.如权利要求20所述的方法，其中利用湿蚀刻剂对所述隔离区进行深蚀刻。
24.如权利要求20所述的方法，其中所述半导体覆盖层具有拉应力。
25.如权利要求24所述的方法，其中所述半导体覆盖层在所述半导体主体的所述侧壁上比在所述半导体主体的所述顶面上具有较大的拉应力。
26.如权利要求24所述的方法，其中所述源极/漏极区域具有n型导电性。
27.如权利要求20所述的方法，其中所述半导体基片是硅基片，其中所述半导体主体是硅锗合金，并且其中所述半导体覆盖层是硅。
28.如权利要求20所述的方法，其中所述半导体覆盖层具有压应力。
29.如权利要求28所述的方法，其中所述半导体覆盖层在所述半导体主体的所述侧壁上比在所述半导体主体的顶面上具有较大的压应力。
30.如权利要求28所述的方法，其中所述半导体基片是单晶硅基片，其中所述半导体主体包括硅碳合金，并且其中所述半导体覆盖层是外延硅。
31.如权利要求28所述的方法，其中所述源极/漏极区域具有p型导电性。
32.一种形成半导体器件的方法包括：
在半导体基片中形成一对彼此隔开的隔离区，所述彼此隔开的隔离区在所述基片中限定有源基片区，其中所述隔离区在所述有源基片区上面延伸；
在所述隔离区之间在所述基片的所述有源区上形成半导体薄膜；
在所述隔离区之间在所述半导体薄膜的所述顶面上形成第一覆盖层；
对所述隔离区进行深蚀刻，以便形成具有带有所述第一覆盖层的顶面和一对侧向相对的侧壁的半导体主体；
在所述半导体主体的所述顶面上的所述第一覆盖层上以及在所述半导体主体的所述侧壁上形成第二覆盖层；
在所述半导体主体的所述第一覆盖层上的所述第二覆盖层上以及在所述半导体主体的所述侧壁上的所述第二覆盖层上形成栅极绝缘层；
在所述栅极绝缘层上并围绕所述栅极绝缘层形成具有一对侧向相对的侧壁的栅极电极；以及
在所述栅极电极的相对的两侧，在所述半导体主体内形成一对源极/漏极区域。
33.如权利要求32所述的方法，其中所述第一和第二覆盖层是外延硅，并且其中所述半导体主体是硅锗合金，并且其中所述半导体基片是硅单晶基片。
34.如权利要求32所述的方法，其中所述第一和第二覆盖层是外延硅，其中所述半导体主体是硅碳合金，并且其中所述半导体基片是硅单晶基片。
35.如权利要求32所述的方法，其中所述第一和第二半导体覆盖层具有拉应力。
36.如权利要求32所述的方法，其中所述第一和第二半导体覆盖层具有压应力。
37.如权利要求32所述的方法，其中所述半导体薄膜具有不同于所述半导体基片的晶格结构，使得所述半导体薄膜具有在其中形成的应力。
38.一种形成半导体器件的方法包括：
在基片上形成第一半导体主体和第二半导体主体，所述第一和所述第二半导体主体各自具有顶面和一对侧向相对的侧壁，所述第一半导体主体和所述第二半导体主体相隔一段距离；
在所述第一和所述第二半导体主体的所述侧壁和所述顶面上形成半导体覆盖层；
在所述第一和所述第二半导体主体的所述顶面和所述侧壁上形成栅极绝缘层；以及
在所述第一和第二半导体主体的所述顶面上的所述栅极绝缘层上以及在所述第一和第二半导体主体的所述侧壁上的所述栅极绝缘层旁边形成栅极电极。
39.如权利要求38所述的方法，其中利用光刻工艺过程限定所述半导体主体，并且其中隔开所述第一和第二主体的所述距离是所述光刻工艺过程可以达到的最小尺寸。
40.如权利要求39所述的方法，其中所述第一和第二半导体主体具有等于所述光刻工艺过程可以限定的最小尺寸的宽度。
41.如权利要求38所述的方法，其中所述半导体主体是外延硅薄膜并且其中所述半导体覆盖层是外延硅薄膜。
42.如权利要求38所述的方法，其中所述半导体主体是外延硅锗合金薄膜并且其中所述半导体覆盖层是外延硅薄膜。
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KR100845175B1 (ko) 2008-07-10
US7154118B2 (en) 2006-12-26
TWI269358B (en) 2006-12-21
CN101189730B (zh) 2011-04-20
US7781771B2 (en) 2010-08-24
US20080142841A1 (en) 2008-06-19
WO2005098963A1 (en) 2005-10-20
US20050218438A1 (en) 2005-10-06
US7326634B2 (en) 2008-02-05
KR20060130704A (ko) 2006-12-19
DE112005000704B4 (de) 2012-08-30
US20050224800A1 (en) 2005-10-13
DE112005000704T5 (de) 2007-09-06

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