CN101218651B - Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells - Google Patents

Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells Download PDF

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CN101218651B
CN101218651B CN2006800105187A CN200680010518A CN101218651B CN 101218651 B CN101218651 B CN 101218651B CN 2006800105187 A CN2006800105187 A CN 2006800105187A CN 200680010518 A CN200680010518 A CN 200680010518A CN 101218651 B CN101218651 B CN 101218651B
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volatile memory
memory device
subgroup
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programming
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CN101218651A (en
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格里特·简·赫民克
龟井辉彦
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Delphi International Operations Luxembourg SARL
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SanDisk Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A set of non-volatile storing elements are divided into subsets for executing soft program in order to soft-program the slower soft programming element more completely. The entire set of elements is soft-programmed until the soft programming is verified to be executed (or until a first subset of elements is verified as soft-programmed). When the set is verified as soft-programmed the first subset of elements is restrained for further soft programming, at the same time the second subset of elements are executed with additional soft programming. The second subset can comprises the slower soft programming element. The second subset can following go through the soft programming verification, meanwhile the first subset is eliminated from the verification. The soft programming and verification aiming at the second subset can be continued until the soft programming is verified to be executed. The different step widths can be used depending on which subset is soft-programmed and verified to increase the magnitude of the soft programming signal.

Description

Nonvolatile memory system and soft program method
Right of priority
The application's case advocate application on March 31st, 2005 being entitled as of the people such as Hemink " NON-VOLATILEMEMORY ERASE OPERATIONS WITH OVER-ERASE PROTECTION " the 60/667th, the right of priority of No. 043 U.S. Provisional Patent Application case, the mode that described application case is quoted in full is incorporated herein.
The cross reference of related application
Following application case is that mode cross reference and that quote in full is incorporated herein:
The U.S. patent application case of the people such as Hemink of application on Dec 6th, 2005 the 11/296th, No. 055 (attorney docket SAND-01066US0) being entitled as " ERASING NON-VOLATILE MEMORYUSING INDIVIDUAL VERIFICATION AND ADDITIONAL ERASING OF SUBSETS OFMEMORY CELLS ";
The 11/296th, No. 028 (attorney docket SAND-01066US1) U.S. patent application case that is entitled as " SYSTEMS FOR ERASINGNON-VOLATILE MEMORY USING INDIVIDUAL VERIFICATION AND ADDITIONALERASING OF SUBSETS OF MEMORY CELLS " of the people such as Hemink of application on Dec 6th, 2005;
The U.S. patent application case of the people such as Hemink of application on Dec 6th, 2005 the 11/296th, No. 071 (attorney docket SAND-01 066US3) being entitled as " SYSTEMS FOR SOFT PROGRAMMINGNONVOLATILE MEMORY UTILIZING INDIVIDUAL VERIFICATION ANDADDITIONAL SOFT PROGRAMMING OF SUBSETS OF MEMORY CELLS ";
The U.S. patent application case of the Masaaki Higashitani of application on Dec 6th, 2005 the 11/295th, No. 755 (attorney docket SAND-01054US0) being entitled as " ERASING NON-VOLATILEMEMORY UTILIZING CHANGING WORD LINE CONDITIONS TO COMPENSATE FORSLOWER ERASING MEMORY CELLS "; And
The U.S. patent application case of the Masaaki Higashitani of application on Dec 6th, 2005 the 11/296th, No. 032 (attorney docket SAND-01054US2) being entitled as " SYSTEMS FOR ERASINGNON-VOLATILE MEMORY UTILIZING CHANGING WORD LINE CONDITIONS TOOMPENSATE FOR SLOWER ERASING MEMORY CELLS ".
Technical field
The present invention relates generally to the semiconductor technology for the erasable nonvolatile memory device.
Background technology
Semiconductor memory system has become and has been used for more and more at large various electronic installations.For instance, nonvolatile semiconductor memory is used for cellular phone, digital camera, personal digital assistant, mobile computing device, non-moving calculation element and other device.EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) (comprising quick flashing EEPROM) and EPROM (EPROM) belong to the most general nonvolatile semiconductor memory.
An example of flash memory system uses and is clipped in two enable nand gates of selecting between grid, and it comprises a plurality of transistors of arranged in series.The transistor of series connection and selection grid are called the NAND string.Fig. 1 is the top view of showing a NAND string.Fig. 2 is its equivalent electrical circuit.The NAND that describes in Fig. 1 and 2 string comprises four transistors 100,102,104 and 106, its series connection and be clipped in first and select between grid 120 and the second selection grid 122.Select grid 120 that NAND is series-connected to bit line 126.Select grid 122 that NAND is series-connected to source electrode line 128.By controlling selection grid 120 via selecting line SGD to apply appropriate voltage to control grid 120CG.By controlling selection grid 122 via selecting line SGS to apply appropriate voltage to control grid 122CG.Each in transistor 100,102,104 and 106 all comprises controls grid and floating grid, thereby forms the grid element of memory cell.For instance, transistor 100 has the grid 100CG of control and floating grid 100FG.Transistor 102 comprises controls grid 102CG and floating grid 102FG.Transistor 104 comprises controls grid 104CG and floating grid 104FG.Transistor 106 comprises controls grid 106CG and floating grid 106FG.Control grid 100CG and be connected to word line WL3, control grid 102CG and be connected to word line WL2, control grid 104CG and be connected to word line WL1, and control grid 106CG is connected to word line WL0.
Although it should be noted that Fig. 1 and 2 shows four memory cells in the NAND string, only provides four transistorized uses as an example.NAND goes here and there to have and is less than four memory cells or four above memory cells.For instance, some NAND strings will comprise 8 memory cells, 16 memory cells, 32 memory cells etc.The discussion of this paper is not limited to any certain number destination memory location in the NAND string.
The typical structure that is used for the flash memory system of use enable nand gate will comprise some NAND strings.For instance, Fig. 3 shows three NAND strings 202,204 and 206 of the memory array with more NAND strings.Each in the NAND string of Fig. 3 all comprises two and selects transistor or grid and four memory cells.For instance, NAND string 202 comprises selects transistor 220 and 230, and memory cell 222,224,226 and 228.NAND string 204 comprises selects transistor 240 and 250, and memory cell 242,244,246 and 248.Each was ganged up one and selects grid (for example, selecting grid 230 and selection grid 250) to be connected to source electrode line.Select line SGS to be used for controlling source side and select grid.Each NAND ganged up by the selection grid 220 of selecting line SGD to control, 240 etc. and was connected to corresponding bit line.In other embodiments, select line not necessarily to need to share.Word line WL3 is connected to the control grid for memory cell 222 and memory cell 242.Word line WL2 is connected to the control grid for memory cell 224 and memory cell 244.Word line WL1 is connected to the control grid for memory cell 226 and memory cell 246.Word line WL0 is connected to the control grid for memory cell 228 and memory cell 248.As seen, bit line and corresponding NAND string comprise the row of memory cell array.Word line (WL3, WL2, WL1 and WL0) comprises the row of array.Each word line connects the control grid of each memory cell in row.For instance, word line WL2 is connected to for memory cell 224,244 and 252 control grid.
Each memory cell can be stored data (analog or digital).When storage one-bit digital data, the scope of the possible threshold voltage of memory cell is divided into two scopes, and it is appointed as logical data " 1 " and " 0 ".In an example of NAND type flash memory, threshold voltage is negative after memory cell is wiped free of, and is defined as logical one.Threshold voltage after programming operation is for just and be defined as logical zero.When threshold voltage for negative and by applying 0 volt when attempting reading to controlling grid, memory cell will connect to indicate positive stored logic 1.For just and by applying 0 volt when attempting read operation to controlling grid, memory cell will be disconnected, it indicates stored logic 0 when threshold voltage.Memory cell also can be stored multistage information, for example the numerical data of multidigit.In the situation that the storage multi-stage data, the scope of possible threshold voltage is divided into the number of data level.For instance, if store the information of four levels, will there be so four threshold voltage ranges, be appointed as data value " 11 ", " 10 ", " 01 " and " 00 ".In an example of nand type memory, the threshold voltage after erase operation is for bearing and be defined as " 11 ".Three different positive threshold voltages are used for state " 10 ", " 01 " and " 00 ".
The related example of NAND type flash memory and operation thereof provides in following United States Patent (USP)/patent application case: the 5th, 570, No. 315 United States Patent (USP)s; The 5th, 774, No. 397 United States Patent (USP)s; The 6th, 046, No. 935 United States Patent (USP)s; The 6th, 456, No. 528 United States Patent (USP)s; And the 09/893rd, No. 277 (publication number US2003/0002348) U.S. patent application case, described patent all is incorporated herein by reference.
When flash memory cells is programmed, program voltage is applied to controls grid (selected word line) and bit line ground connection.From the electronic injection of p trap in floating grid.When electronics gathered in floating grid, the threshold voltage that floating grid can become electronegative and unit rose.The threshold voltage of floating grid charging and unit can be indicated the particular state corresponding to the data of storage.
In order to wipe the memory cell of NAND type flash memory, electronics is transferred to well region and substrate from the floating grid of each memory cell.Usually, (for example ,～16V-20V) erasing pulse is applied to well region and attracts well region with the electronics that will leave from the floating grid of each memory cell with one or more high voltages.Thereby the word line ground connection of each memory cell or be provided with 0V and attract electronics to produce noble potential in the tunnel oxide district.If do not wipe each memory cell of NAND string after applying the erasing voltage pulse, the large I of pulse increases and is applied to the NAND string again so, until each memory cell is wiped free of.The amount that erasing voltage increases between pulse is commonly referred to the step sizes of erasing voltage.
Use the typical erase operation of prior art can cause in the NAND string difference between memory cell to wipe speed.Comparable other memory cell of some memory cells is faster or more slowly arrive to be used for the target threshold voltage of erase status.This can cause comparatively fast wiping the over-erasure of memory cell, because it will continue to stand through applying fully to wipe the erasing voltage than the slower memory unit of NAND string.Therefore, differently wipe the shorter cycle life that speed can cause memory cell or NAND string.Typical erase operation also can cause the diverse threshold voltage between the memory cell of NAND string.That is to say, when comparing with other memory cell of described string or device, one or more memory cells of NAND string can have different threshold voltages after applying one or more erasing voltage pulses.For overcoming this effect, regulated with the technology that is commonly referred to soft programming and wiped the threshold voltage of one or more memory cells afterwards.Soft programming comprises to one or more memory cells and applies relatively low program voltage, and it is lower than the voltage that is used for actual program.Soft programming usually comprises and applies a series of pulses that program voltage increases as the step sizes between applying with program voltage pulse at every turn.The threshold voltage of soft programming rising memory cell is in order to make all through wiping threshold voltage distribution narrow and/or the rising of memory cell.Yet soft programming can increase programming and erasing time.
In addition, traditional soft programming can stand some impact in the same affect of diverse character between different memory cells.May wipe slowly the same memory unit also may soft programming slow.Other unit of these comparable NAND strings in slower soft programming unit has lower erase threshold voltage when soft programming finishes.
Summary of the invention
Technology described herein belongs to in the mode that more consistent erase threshold voltage is provided, non-volatile memory device being wiped and/or the technology of soft programming.According to an embodiment, a kind of system is provided, it considers to wipe with the individual characteristic of soft programming one or more memory cells of operating period, to wipe behavior and soft programming behavior.
One group of non-volatile memory device (for example, the NAND string) can be divided into subgroup and wipe, in order to avoid over-erasure comparatively fast to wipe memory element.Whole described set of pieces is through wiping, until the first subgroup of described set of pieces is verified as through wiping.Described the first subgroup can comprise very fast erased element.Verify that described the first subgroup comprises eliminating the second subgroup from checking.Be verified as after wiping in described the first subgroup, its suppressed wiping, described the second subgroup is through further wiping simultaneously.When described the second subgroup is verified as when wiping, described set of pieces is verified as through wiping.Verify described set of pieces through wipe can comprise get rid of described the first subgroup from checking or verify together described the first and second subgroups both.Depend on which subgroup just being wiped free of and verifying and use different step sizes, in order to more effectively and exactly wipe described set of pieces.
One group of non-volatile memory device can be divided into subgroup and carry out soft programming, in order to more completely slower soft programming element is carried out soft programming.Whole described set of pieces is through soft programming, until be verified as through soft programming (or until the first subgroup element be verified as through soft programming, till getting rid of the second subgroup simultaneously from checking).Be verified as after soft programming at described group, the first suppressed further soft programming of subgroup element is implemented extra soft programming to the second subgroup element simultaneously.The second subgroup can comprise slower soft programming element.The second subgroup can then experience soft program verification, gets rid of simultaneously the first subgroup from checking.Soft programming and checking for the second subgroup are sustainable, until it is verified as through soft programming.Depend on which subgroup just by soft programming and checking, can use different step sizes to increase the size of soft programming signal.In one embodiment, according to the soft programming of carrying out after the wiping of technology described herein according to technology described herein.
In one embodiment, provide a kind of method of erasable nonvolatile memory, it comprises enables wiping of one group of non-volatile memory device.Enabling the first and second subgroups of described group of non-volatile memory device wipes.Then apply one or more erasing voltage pulses to described group, enable simultaneously the non-volatile memory device of described the first and second subgroups and wipe.Apply pulse until described the first subgroup is verified as through wiping.Be verified as after wiping in described the first subgroup, suppress described the first subgroup and further wipe, again enable described the second subgroup simultaneously and wipe.Then apply one or more extra erasing voltage pulses to described group, suppress simultaneously described the first subgroup and enable described the second subgroup.Apply additional pulse until described the second subgroup is verified as through wiping.
In one embodiment, provide a kind of Nonvolatile memory system, the management circuit that it comprises one group of non-volatile memory device and communicates by letter with described group of non-volatile memory device.Described group of non-volatile memory device that comprises the first subgroup and the second subgroup.Described management circuit is wiped described group with a kind of technology, and described technology comprises: apply erasing voltage to described group, each non-volatile memory device of enabling simultaneously in described group is wiped; Whether verify described the first subgroup through wiping, get rid of simultaneously the second subgroup from checking; And repeat to apply and verify, until the first subgroup is verified as through wiping.For after wiping, management circuit suppresses wiping of described the first subgroup, and enables wiping of described the second subgroup in described the first subgroup of checking.Management circuit then applies erasing voltage to described group, and enable simultaneously described the second subgroup and wipe and suppress described the first subgroup and wipe, and by verifying that whether the second subgroup is through wiping to verify that whether described group of non-volatile memory device be through wiping.
In one embodiment, provide a kind of method of soft programming nonvolatile memory, it comprises to one group of non-volatile memory device and applies one or more soft programming pulses, until described group is verified as through soft programming.Described group of checking be after soft programming, suppress the first subgroup of described group of non-volatile memory device and carry out soft programming, and the second subgroup to described group of non-volatile memory device applies one or more extra soft programming pulses, suppresses simultaneously the soft programming of described the first subgroup.In one embodiment, carry out soft programming after as above wiping.
According to another embodiment, provide a kind of Nonvolatile memory system, the management circuit that it comprises one group of non-volatile memory device and communicates by letter with described group of non-volatile memory device.Described group comprises the non-volatile memory device of the first subgroup and the non-volatile memory device of the second subgroup.Management circuit applies soft-program voltage and verifies whether described group carried out soft programming through soft programming to described group of non-volatile memory device by each non-volatile memory device in described group.Management circuit repeats to apply and verify, until described group of non-volatile memory device is verified as through soft programming.Verifying described group after soft programming, management circuit applies soft-program voltage to each non-volatile memory device in the non-volatile memory device of the first subgroup, and whether the non-volatile memory device of verifying the first subgroup simultaneously from checking gets rid of second subgroup through soft programming.
From obtaining further feature of the present invention, aspect and purpose to checking of specification, drawings and the claims.
Description of drawings
Fig. 1 is the top view of NAND string.
Fig. 2 is the equivalent circuit diagram of the NAND string described of Fig. 1.
Fig. 3 is the circuit diagram of describing three NAND strings.
Fig. 4 is the block scheme of an embodiment that can implement the Nonvolatile memory system of various aspects of the present invention.
Fig. 5 illustrates the exemplary organization of memory array.
Fig. 6 describes to be applied to exemplary program through selecting the word line/verifying voltage signal according to embodiment.
Fig. 7 is for the exemplary flow chart of carrying out programming operation.
Fig. 8 describes the exemplary threshold distributions of group of memory cells.
Fig. 9 describes to store the exemplary threshold distributions of the group of memory cells of two bits.
Figure 10 is the table of describing according to the exemplary bias condition that is used for the execution erase operation of prior art.
Figure 11 is the curve map that is depicted in the voltage of the various piece of NAND string during desirable erase operation.
Figure 12 is the cross-sectional view of NAND string, and it describes each capacitive couplings voltage in described NAND string.
Figure 13 is the curve map that is depicted in each voltage of the end memory cell of NAND string during erase operation.
Figure 14 A and Figure 14 B are depicted in the end of completing NAND string after erase operation and exemplary indivedual threshold voltages of internal memory unit distribute.
Figure 15 is the process flow diagram that is used for wiping one group of non-volatile memory device according to an embodiment.
Figure 16 is the table that is used for wiping and verifying the bias condition of wiping of one group of non-volatile memory device of describing according to an embodiment.
Figure 17 A-17C describes to distribute according to the end memory cell of the NAND during erase operation of embodiment string and the internal memory unit threshold voltage at each some place.
Figure 18 A-18B is the curve map of describing according to the erasing voltage signal of an embodiment.
Figure 19 is the process flow diagram according to the step 456 that is used for execution Figure 15 of an embodiment.
Figure 20 describes according to the end memory cell of the string of NAND after soft programming of prior art and the exemplary threshold voltage distributions of internal memory unit.
Figure 21 is the process flow diagram that is used for one group of non-volatile memory device of soft programming according to an embodiment.
Figure 22 is the table that is used for soft programming and the bias condition of the soft programming of verifying one group of non-volatile memory device of describing according to an embodiment.
Figure 23 describes according to the end memory cell of the string of NAND after soft programming of an embodiment and the exemplary threshold voltage distributions of internal memory unit.
Embodiment
Fig. 4 is the block scheme of an embodiment of flash memory that can be used for implementing one or more embodiment of content of the present invention.Can use other system and embodiment.Memory cell array 302 is controlled by arrange control circuit 304, line control circuit 306, c source electrode control circuit 310 and p trap control circuit 308.Arrange control circuit 304 is connected to the bit line of memory cell array 302, to be used for reading the data that are stored in memory cell, for the state of memory cell during definite programming operation, and programme and wipe with promotion or inhibition for the potential level of controlling bit line.Line control circuit 306 be connected to the word line with select in the word line one, apply the program voltage of the bit line potential levels combination of reading voltage, apply and being controlled by arrange control circuit 304 and apply erasing voltage.C source electrode control circuit 310 is operatively connected to the common source line (being designated as " C source electrode " in Fig. 6) of memory cell.P trap control circuit 308 is controlled p trap voltage.
The data that are stored in memory cell can be read and be outputed to exterior I/O line via data input/output (i/o) buffer 312 by arrange control circuit 304.The programming data that is stored in memory cell is input to data input/output (i/o) buffer 312 via exterior I/O line, and is delivered to arrange control circuit 304.Exterior I/O line is connected to controller 318.
The order data that is used for the control flash memory device is input to controller 318.Order data notice flash memory request is which kind of operation.Input command is delivered to the state machine 316 as the part of control circuit 315.State machine 316 is controlled arrange control circuit 304, line control circuit 306, c source electrode control 310, p trap control circuit 308 and data input/output (i/o) buffer 312.State machine 316 is the status data of exportable flash memory also, for example ready/busy or by/failure.
Controller 318 is connected to or can be connected with the host computer system such as personal computer, digital camera or personal digital assistant etc.Itself and initially for example data are stored into memory array 302 or from the main-machine communication of the order of memory array 302 reading out datas, and provide or receive described data.Controller 318 is converted to described order can be by as command circuit 314 deciphers of the part of control circuit 315 and the command signal of execution.Command circuit 314 is communicated by letter with state machine 316.Controller 318 contains memory buffer usually, is used for user data write store array or reads from memory array.
An exemplary embodimentsan example memory system comprises an integrated circuit that comprises controller 318, and one or more integrated circuit (IC) chip, its each control, I/O and state machine circuit that all contains memory array and be associated.Exist the memory array of system and controller circuitry are integrated in trend on one or more integrated circuit (IC) chip together.Accumulator system can embed the part as host computer system, maybe can be included in the storage card (or other encapsulation) that inserts removedly in host computer system.Described card can comprise whole accumulator system (for example, comprising controller) or only comprise the memory array (its middle controller or control function are embedded in main frame) with associated peripheral circuits.Therefore, controller can be embedded in main frame or be included in removable accumulator system.
Referring to Fig. 5, the demonstrative structure of memory cell array 302 is described.As an example, the NAND quick flashing EEPROM that is split into 1024 blocks is described.Can wipe simultaneously the data that are stored in each block.In one embodiment, block is the least unit of the unit wiped simultaneously.In each block, in this example, there are 8512 row.Each block is divided into many pages of the unit that can be programming usually.Other data unit that is used for programming also may and be expected.In one embodiment, individual page can be divided into a plurality of sections and the described section unit that can contain as the minimal number of the write-once of basic programming operation.One or more data pages are stored in row of memory cells usually.
In each block of the example of Fig. 5, there are 8512 row, it is divided into even column and odd column.Bit line is divided into even bitlines (BLe) and odd bit lines (BLo).In strange/even bit line structure, along common word line and the memory cell that is connected to odd bit lines at a time programming, and along common word line and the memory cell that is connected to even bitlines at another time programming.Fig. 5 shows four memory cells, and it is connected in series to form the NAND string.Although show four unit for being included in each NAND string, can use greater or less than four (for example, 16,32 or other number) memory cells.A terminal of NAND string selects transistor or grid (be connected to and select grid drain electrode line SGD) to be connected to corresponding bit line via first, and another terminal selects transistor (be connected to and select gate source polar curve SGS) to be connected to the c source electrode via second.
In other embodiments, bit line is not divided into the odd and even number bit line.This class formation is commonly referred to full bit line structure.In full bit line structure, read with programming operation during select simultaneously whole bit lines of block.Programme simultaneously along common word line and the memory cell that is connected to any bit line.
An embodiment read with programming operation during, select simultaneously 4256 memory cells.The memory cell of selecting has identical word line (for example, WL2-i) and the bit line (for example, even bitlines) of identical type.Therefore, can programme the simultaneously data of 532 bytes.The data formation logical page (LPAGE) of these 532 bytes that read simultaneously or programme.Therefore, in this example, a block can be stored at least 8 pages.When each memory cell stores two bits (for example, multi-level unit), 16 pages of a block stores.Other big or small block and page also can be used for embodiment.In addition, the structure that is different from the structure of Figure 4 and 5 also can be used for implementing embodiment.
Read with verification operation in, the selection grid of the block selected is elevated to one or more selects voltages and with the unselected word line of the block selected (for example, WL0, WL1 and WL3) be elevated to and read by voltage (for example, 4.5 volts) so that the transistor conduct operates by grid.The selection word line of the block of selecting (for example, WL2) be connected to reference voltage, its level is used for each and reads and verification operation through specifying, so as to determine the threshold voltage of the memory cell paid close attention to be higher than or lower than this level.For instance, in the read operation of a bit memory cell, with the word line WL2 ground connection of selecting, so that whether detection threshold voltage is higher than 0V.In the verification operation of a bit memory cell, the word line WL2 that selects is connected to for example 0.8V, whether reached 0.8V in order to carry out middle verification threshold voltage in programming.Source electrode and p trap are in zero volt during reading and verifying.The bit line (BLe) of selecting is pre-charged to for example level of 0.7V.If threshold voltage is higher than reading or verify level, the potential level of the bit line (BLe) of paying close attention to so is because the non-conducting memory cell that is associated is kept high level.On the other hand, if threshold voltage is lower than reading or verify level, the potential level of the bit line (BLe) of paying close attention to so is because the conduction memory cell is reduced to low level, for example less than 0.5V.The state of memory cell is by the sensor amplifier detection that is connected to bit line and reads the bit-line voltage of gained.Be the programming or the difference of wiping between memory cell depends on whether net negative charge is stored in floating grid.For instance, if negative charge is stored in floating grid, threshold voltage becomes higher and transistor can be in enhanced mode of operation so.
When program memory cells in an example, drain electrode and p trap receive 0 volt, receive a series of programming pulses with increase value and control grid.In one embodiment, in described series the value scope of pulse at 12 volts to 24 volts.In other embodiments, in described series, the scope of pulse can be different, for instance, have the beginning level higher than 12 volts.During the programming of memory cell, implement verification operation in the cycle between programming pulse.That is to say, read the program level of each unit in the cell group of multiple programming between each programming pulse, whether met or exceeded to determine it checking level that it just is being programmed into.A kind of mode of verification of programming is in specific comparison point test conduction.For example in the NAND unit, by for all follow-up programming pulses, bit-line voltage being elevated to VDD (for example, 2.5 volts) to stop being used for being verified as the programming process of the unit of abundant programming from 0, lock those unit.In some cases, with the number (for example, 20 pulses) of Limited Pulses, and if given memory cell fully do not programmed by last pulse, suppose so mistake.In some embodiments, wiped memory cell (with block or other unit) before programming.
Fig. 6 describes the program voltage signal according to an embodiment.This signal has the pulse that one group of band increases value.The value of pulse increases predetermined step sizes with each pulse.In an embodiment who comprises the memory cell of storing long numeric data, exemplary step sizes is 0.2 volt (or 0.4 volt).Between each of programming pulse is the checking pulse.The signal of Fig. 6 supposition four status register unit, so it comprises three checking pulses.For instance, be three continuous checking pulses between programming pulse 330 and 332.The first checking pulse 334 is depicted as and is in zero volt verifying voltage level.The second checking pulse 336 is followed the first checking pulse with the second verifying voltage level.The 3rd checking pulse 338 is followed the second checking pulse 336 with the 3rd verifying voltage level.Can store the multistate memory unit of data and may carry out verification operations at seven comparison point places in eight states.Therefore, apply successively seven checking pulses to carry out seven verification operations with seven checking level between two continuous programming pulses.Based on seven verification operations, system can determine the state of memory cell.A kind of method of the time burden for reducing checking is to use more effective proof procedure, for example disclose in following application case: the 10/314th, No. 055 U.S. patent application case that is entitled as " Smart Verify for Multi-StateMemories " of application on Dec 5th, 2002; The of being entitled as of on October 27th, 2005 application " Methodfor Programming of Multi-State Non-Volatile Memory Using Smart Verify " _ _ _ _ _ _ _ _ _ _ number (attorney docket SAND-1051US1) U.S. patent application case; And being entitled as of on October 27th, 2005 application " Apparatus for Programming of Multi-State Non-Volatile Memory Using Smart Verify " the _ _ _ _ _ _ _ _ _ _ U.S. patent application case of number (attorney docket SAND-105IUS0), the mode that described application case is all quoted in full is incorporated herein.
Carry out above-described reading and verification operation according to technology well known in the prior art.Therefore, the those skilled in the art can change the many details in institute's details of construction.
Fig. 7 is the process flow diagram of describing for an embodiment of the method that nonvolatile memory is programmed.Wipe the memory cell of will programme in step 340.Step 340 can comprise the more memory cell of memory cell (for example, with block or other unit) of wiping than with programming.In step 342, carry out soft programming so that the distribution narrow of the erase threshold voltage through wiping memory cell.Some memory cells may be in the erase status darker than necessary erase status due to erase process.Soft programming can apply little programming pulse makes it more near the erase verification level with mobile threshold voltage through wiping memory cell.In the step 350 of Fig. 7, " data loading " order is sent and is input in command circuit 314 by controller 318, allows data to be input to data input/output (i/o) buffer 312.The input data are considered to order and are latched by state machine 316 via the order latch signal (undeclared) that is input to command circuit 314.In step 352, the address date of specific page address is input to line control unit or demoder 306 from controller or main frame.The input data are considered to page address and are latched via state machine 316 under the address latch signal impact that is input to command circuit 314.In step 354, will be input to for the programming data page through the addressing page data input/output (i/o) buffer 312 to be used for programming.For instance, can input in one embodiment the data of 532 bytes.Described data are latched in the suitable register for the bit line of selecting.In certain embodiments, data also are latched in the second register for the bit line of selecting to be used for verification operation.In step 356, data input/output (i/o) buffer 312 is sent and be input to " programming " order by controller.Order is latched by state machine 316 via the order latch signal that is input to command circuit 314.
By " programming " command triggers, use is applied to data programing that the step-by-step impulse of Fig. 6 of suitable word line will latch in step 354 to controlled by state machine 316 in the selection memory unit.In step 358, be applied to programming pulse voltage level Vpgm through selecting the word line be initialized as the beginning pulse (for example, 12V) and the programmable counter PC initialization that will be kept by state machine 316 in 0.In step 360, a Vpgm pulse is put on through selecting the word line.If logical zero is stored in the particular data latch, the indication corresponding memory cell of should programming is so with corresponding bit line ground connection.On the other hand, if logical one is stored in the particular lock storage, the indication corresponding memory cell should remain on its current data state, so corresponding bit line is connected to VDD to suppress programming.
In step 362, checking is through the state of selection memory unit.If the target threshold voltage that detects through selected cell has arrived proper level, the data that are stored in so in the corresponding data latch are changed into logical one.Do not arrive proper level if threshold voltage detected, the data that are stored in so in the corresponding data latch do not change.In this way, need not to programme and have the bit line that is stored in the logical one in its corresponding data latch.When all data latch stores logical ones, state machine knows that all programme through selected cell.In step 364, check that whether all data latches all in stored logic " 1 ".If so, programming process is completed and success so, because all arrive its dbjective state through programming and checking through the selection memory unit.Report in step 366 " by " state.
If determine not to be that all data latches is all at stored logic " I in step 364 5", programming process continues so.In step 368, contrast program limit value scrutiny program counter PC.An example of program limit value is 20, yet, can use other value in various embodiments.If programmable counter PC is not less than 20, determine in step 369 whether the number of the position that not success is programmed is equal to or less than predetermined number so.If the number of the position of success programming is not equal to or less than predetermined number, so programming process is labeled as by and passes through state in step 371 report.Can use error proofread and correct the position that not success is programmed during reading process.Yet, if the number of the position of success programming is not greater than predetermined number, so programming process is labeled as failure and reports status of fail in step 370.If programmable counter PC less than 20, makes the Vpgm level increase step sizes and increase progressively programmable counter PC in step 372 so.In step 372, process is circulated back to step 360 to apply next Vpgm pulse.
The process flow diagram of Fig. 7 is described and can be passed through programmed method for the single that binary storage is used.In can passing through programmed method for the secondary that for example multistage storage is used, can use a plurality of programmings or verification step in the single repetition of process flow diagram.Can for programming operation each time by execution in step 358-372.In passing through for the first time, can apply one or more programming pulses and verify whether its result is in suitable intermediateness with determining unit.In passing through for the second time, can apply one or more programming pulses and verify whether its result is in suitable end-state with determining unit.
When the programming process of success finished, the threshold voltage of memory cell should be used in one or more of the threshold voltage of program memory cells distribute or in the distribution for the threshold voltage through wiping memory cell.Fig. 8 explanation is used for the threshold voltage distribution of memory cell array when the data of each memory cell stores position.Fig. 8 show to be used for through wiping memory cell threshold voltage first distribute 380 and be used for distributing 382 through second of the threshold voltage of program memory cells.In one embodiment, first distributes threshold voltage levels in 380 for negative and corresponding to logical one, and second distribute threshold voltage levels in 382 for just and corresponding to logical zero.
Fig. 9 explanation is used for the exemplary threshold voltage distributions of memory cell array when each memory cell is stored two bits in four physical states.384 expressions that distribute are in the distribution through the threshold voltage of the unit of erase status (storage " 11 "), and it has negative threshold voltage levels.386 expressions that distribute are in the distribution of threshold voltage of the unit of the first programming state (storage " 10 ").388 expressions that distribute are in the distribution of threshold voltage of the unit of the second programming state (storage " 00 ").390 expressions that distribute are in the distribution of threshold voltage of the unit of the 3rd programming state (storage " 01 ").In this example, be stored in each in two positions in the single memory unit from different logical page (LPAGE)s.That is to say, be stored in the different logical page address of each carrying of two positions in each memory cell.The position that shows in square is corresponding to lower page.The position that shows in circle is corresponding to upper page.In one embodiment, use gray code sequence logic state to be assigned to the continuous physical state of memory cell, if make the threshold voltage of floating grid be displaced to mistakenly in nearest adjacent threshold voltage state scope, so only a position is with influenced.For improved reliability is provided, preferably make individual distributions compact (distribution narrow), because distribution more closely can make and read surplus (adjacent states threshold value distribute between distance) and broaden.
Certainly, if storer is with four above physical states operations, so at the threshold voltage distribution number that in voltage threshold window, existence is equaled state number that defines of memory cell.In addition, although specify specific bit patterns to each distribution or physical state, can specify different bit patterns.
Usually, the unit of positive multiple programming is the alternate cells along the word line.For instance, Fig. 3 explanation three memory cells 224,244 and 252 in the unit of the much bigger number of a word line WL2.Comprise one group of alternate cells storage of unit 224 and 252 from the position of logical page (LPAGE) 0 and 1 (" verso "), and comprise another group alternate cells storage of unit 244 from the position of logical page (LPAGE) 2 and 3 (" recto ").
In one embodiment, by the p trap being elevated to erasing voltage (for example, 20 volts) and with the word line ground connection through selecting block or it is applied 0 volt, source electrode and bit line float simultaneously, wipe memory cell.Figure 10 describes for the exemplary bias condition of carrying out erase operation.Due to capacitive couplings, unselected word line (for example, those word lines in unselected, the block that will not wipe), bit line, selection line and c source electrode also are elevated to high positive potential (for example, 20V).Therefore highfield is applied to the tunnel oxide of the memory cell through selecting block, and during to substrate, wipes the data through the selection memory unit when the electron emission of floating grid.Wipe and refer to by electronics being migrated out the threshold voltage that its floating grid reduces memory cell.When the electronics of abundance is transferred to the p well region from floating grid, become negative through the threshold voltage of selected cell.In case threshold voltage arrives predetermined abundant low value, just memory cell can be considered as through wiping and thinking that erase process is completed or success.Therefore, wipe the threshold voltage that memory cell refers to reduce memory cell, and do not hint that it wipes fully or successfully.Can carry out in another unit of one or more blocks of whole memory array, array or unit and wipe.Erasing voltage signal V EraseUsually apply as a series of erasing voltage pulses, wherein implement the erase verification operation between each pulse.If the unit of the unit of just wiping is not verified as through wiping, another erasing voltage pulse can be applied to the p well region so after the erasing voltage pulse applies.In certain embodiments, the peak value of erasing voltage increases (for example, increasing progressively with 1V) from 16V to 20V for each succeeding impulse.
Figure 11 be depicted in single erasing voltage pulse for typical erase operation and apply during the curve map (for example, under the bias condition of Figure 10) of NAND string each several part place voltage.The example explanation ideal situation of Figure 11, it has ignored capacitive charge coupling between grid as discussed below.Curve 410 describes to receive erasing voltage signal V EraseThe voltage of p well region.The erasing voltage pulse causes p trap straight line to rise to 20V and then turns back to 0V.Curve 414 and 412 is described control gate pole tension and the floating grid voltage of the memory cell of described string.Before applying the erasing voltage pulse, floating grid voltage depends on the programming state of memory cell, and is usually less than 0V.In Figure 11, for the value of the floating grid voltage supposition-1V before the first erasing voltage pulse.Control gate pole tension 414 remains in 0V in whole erase operation, and floating grid voltage 412 rises pro rata with p trap voltage.Floating grid in the tunnel dielectric district capacitive couplings to the p trap.In many NAND string embodiments, the capacitive couplings ratio between the floating grid of memory cell and p well region is about 40-50%.Therefore, floating grid voltage 412 is to rise to the approximately voltage of 9V with the ratio of approximately 0.5: 1 of p trap voltage (when coupling ratio as 50% time).The current potential (current potential between the floating grid of unit and p well region) of wiping of gained provides in the curve map of following Figure 11.Wipe current potential and equal p trap voltage (V Erase=20V) with floating grid voltage (VF G=poor between 9V).For the situation of describing in Figure 11, erasing voltage equals approximately 11V when the first erasing voltage pulse begins.It should be noted that wiping current potential transfers to p trap with electronics from floating grid at the erasing voltage impulse duration of reality and change.Thus, when the p trap turns back to 0V after the erasing voltage pulse, floating grid voltage will from apply before the erasing voltage pulse different.Usually, floating grid voltage will be for just, corresponding to negative (through wiping) threshold voltage of memory cell after the first erasing voltage pulse.
Actual voltage level in the NAND string will be different from the voltage level of describing with respect to the ideal situation of Figure 11.Due between adjacent floating grid and select capacitive charge coupling between grid and adjacent floating grid, NAND goes here and there different memory unit may experience the different current potentials of wiping identical wiping under bias condition.
Figure 12 provides the cross-sectional view of the NAND string that comprises 8 memory cells.Although present embodiment with respect to Figure 12 and unit 8 enable nand gate, the invention is not restricted to this, and can use according to the many enable nand gates that comprise still less or 8 above memory cells (for example, 4,12,16 or more).As describing in Figure 12, the memory cell of NAND string is formed in p well region 540.Each memory cell (502,504,506,508,510,512,514 and 516) comprises the stacked gate architectures that forms by controlling grid (502c, 504c, 506c, 508c, 510c, 512c, 514c and 516c) and floating grid (502f, 504f, 506f, 510f, 512f, 514f and 516f).Floating grid is formed on the surface of the p trap on oxide or the compound film of other dielectric top.Control grid on floating grid, wherein oxide or other isolation dielectric layer separate control grid and floating grid.The control grid of memory cell is connected to or forms word line WL0, WL1, WL2, WL3, WL4, WL5, WL6 and WL7.N+ diffusion region 542 shares between adjacent cells, and described unit is one another in series and connects to form the NAND string by this.Each source electrode and drain electrode in these formation unit, N+ diffusion region.N+ diffusion region 526 is connected to the bit line for NAND string, and the common source line that N+ diffusion region 528 is connected to for a plurality of NAND strings.Select grid 520 to be formed by the structure identical with memory cell with 522, yet gate regions is electrically connected to.
Due to capacitive couplings, when during erase operation, high erasing voltage being put on the p trap, float and select grid 522 and 520 to be elevated to than high normal potential.The erasing voltage that is applied to p trap or its certain part is coupled to from well region each that select grid.Approximately the p trap voltage of 90-100% can expect that being coupled to each selects grid in many enable nand gates.Therefore, if the erasing voltage pulse of 20V puts on the p trap, each is selected voltage on grid will rise about 18V-20V and arrives the voltage of 18V-20V so.In Figure 12, the coupling from p trap 540 to selection grid 522 and 520 is by arrow 530 explanations.Although degree is less, each in the memory cell of described string also experiences similar coupling effect.The p trap of memory cell and the coupling between floating grid are about 40-50% usually.Each floating grid also is coupled to its corresponding grid of controlling, and wherein coupling is about 50-60%.On less degree, each floating gate coupling is to adjacent floating grid and control grid.All different couplings are added together and reach altogether 100%.Suppose 50% coupling from the p trap to floating grid, the floating grid voltage of each memory cell is applying the approximately 10V that raises under the pulse of 20V erasing voltage.This coupling effect is by arrow 532 explanations.The voltage that is coupled to the floating grid of each memory cell is realized the V produce on tunnel oxidation layer EraseCurrent potential.For instance, for having-memory cell of the floating grid voltage of 1V, the p trap is being applied the current potential of wiping that produces about 11V (20V-9V) under the pulse of 20V erasing voltage before wiping.
Each memory cell of described string will experience from neighbor memory cell and/or more transistorized capacitive charge couplings.This coupling can affect the current potential of the floating grid of unit, and therefore affects the current potential of wiping of unit.The last memory cell (for example, the memory cell in Figure 12 502 and 516) of NAND string---is connected to first and last word line (end word line) of NAND string and is adjacent to those memory cells of the selection grid of NAND string---that the capacitive charge that will experience from adjacent selection grid is coupled.In Figure 12, this capacitive couplings is by from the selection grid 520 of memory cell 520 to the arrow 534 of floating grid 502f and describe to the arrow 538 of floating grid 516f from the selection grid 522 of memory cell 516.The voltage that is coupled to memory cell 502 and 516 will select the voltage at grid place to reduce pro rata the upper electric field that exists in tunnel dielectric district (for example, tunnel oxide) of those unit with representativeness.
Occured by arrow 538 and 534 being coupling on both direction of expression, because during erase operation, select grid to be in equally quick condition.Thus, memory cell 516 and 502 floating grid voltage will have some impacts to selecting the voltage on grid 522 and 520.Yet, much smaller to the coupling of selecting grid to the coupling ratio of selecting grid from the p trap from floating grid, and therefore almost completely determine to select grid voltage by p trap voltage.
In many NAND embodiments, the capacitive couplings from the selection grid of the end memory cell of NAND string to floating grid can be contemplated to approximately 2% to 5% the order of magnitude.If the erasing voltages of 20 volts are applied to the p well region, so in the situation that the 90%p trap to the coupling of selecting grid, each selects the voltage of the grid approximately 18V that will rise.Subsequently due to from selecting grid to the coupling of the 2-5% of adjacent floating grid, the approximately 0.4-1V that will rise of the voltage on adjacent floating grid (for example, 516f and 502f).Gained voltage on the tunnel oxide of the end memory cell of described string will littlely than the voltage of ideal situation shown in Figure 11 approximately 0.4 arrive 1V.It should be noted that capacitive couplings mentioned above can be depending on memory cell and select the spacing between physical size, memory cell and the selection grid of grid and for example tunnel dielectric, control and the floating grid that use in this class component of structure between dielectric and select the dielectric character of the dielectric material between grid and memory cell and change largely.For example in some cases, coupling mentioned above can be greater than or less than 2-5% scope mentioned above.
Coupling between adjacent floating grid, another factor is the coupling between floating grid and adjacent word line or control grid.This coupling also can be the order of magnitude of 2-5%, but can be depending on the size and dimension of memory cell and smaller or greater.In some cases, especially select physical distance between grid and neighbor memory cell be similar between two internal memory unit apart from the time, from selecting in grid will be in the similar scope of coupling with from adjacent control grid (word line) and floating grid to the coupling of adjacent floating grid.Yet during erase operation, differently setovered owing to selecting grid to compare with floating grid with the control grid, therefore the floating grid voltage of end memory cell will be higher than the floating grid voltage of internal memory unit, and the current potential of wiping that therefore is used for the end memory cell will be lower, as described below.
Figure 13 is depicted under the bias condition of Figure 10 during the single erasing voltage pulse that is used for erase operation applies, p trap voltage 420, floating grid voltage 422 and the control gate pole tension 424 of the typical end memory cell of NAND string.P trap voltage 420 rises to the peak value of 20V and then turns back to 0V from 0V.Control gate pole tension 424 remains on 0V, is supplied with 0V because be connected to the word line of each memory cell.As all unit, the floating grid of end memory cell on the order of magnitude of about 40-50% capacitive couplings to the p well region.When p well region voltage was increased to 20V, this capacitive couplings impelled floating grid voltage at 50% when coupling of supposition approximately 10V that rises.The end memory cell has a part of voltage that is in the adjacent selection grid place of its coupling in addition.Therefore, voltage on these floating grids will be not only with increase pro rata with its capacitively coupled p trap voltage, but also owing to increasing from the 2-5% coupling of selecting grid.In Figure 13, supposing from the coupling of selecting grid increases extra 1V to floating grid voltage.Therefore, with the maximal value of the 9V of the ideal situation of describing in Figure 11 in pairs than, floating grid voltage 422 rises to the maximal value of 10V when the beginning of erasing voltage pulse.The current potential of wiping in the tunnel dielectric district of end memory cell provides in the curve map of following Figure 13.The current potential of wiping when the erasing voltage pulse begins is about 10V, or wipes the little approximately 1V of current potential than the 11V of ideal situation.
The memory cell that is not adjacent to the selection grid of NAND string (that is, all memory cells except the end memory cell of NAND string) can be described as the internal memory unit of described string in this article.In Figure 12, the internal memory unit of NAND string is memory cell 504,506,508,510,512 and 514.To reduce its capacitive couplings from adjacent floating grid of wiping current potential (hereinafter discussing) although internal memory unit will experience, its degree is less than the degree of end memory cell.Therefore, internal memory unit will be substantially as the previous ideal situation of describing and showing, and (assuming unit is in programming state, and wherein floating grid voltage is approximately-1V) before the erasing voltage pulse to have the current potential of wiping of about 11V.Owing to comparing with internal memory unit, current potential on the tunnel oxide of end memory cell is lower, so (will have the less electronics from its floating grid transfer) will be wiped and can equally with internal memory unit do not wiped darkly to the end memory cell more lentamente after applying one or more erasing voltage pulses.
During higher than predetermined level (lower than the threshold voltage of predetermined level), the memory cell of NAND string is verified as through wiping when the electric charge on floating grid.Due to the extra coupling to the floating grid of end memory cell, the T.T. of erase operation increases, in order to fully wipe these end memory cells.Internal memory unit can be applied to the erasing voltage pulse of number N and fully wipe afterwards, and the end memory cell of NAND string may not can be fully wiped, until apply N+1 or the above erasing voltage pulse of N+1.
Figure 12 is by the extra capacitor coupling effect between the floating grid of the individual memory cell of arrow 536 explanation NAND strings.For instance, the coupling between the upper adjacent floating grid of WL0 and WL1 can be the order of magnitude of 2-5%, but can be depending on the size and dimension of memory cell and smaller or greater.Thus, the voltage that exists on the floating grid of memory cell 516 will affect the voltage of the floating grid of memory cell 514, vice versaad.Similarly coupling will be present between the floating grid of the memory cell 514 that is connected to WL2 and 512, by that analogy.This is coupling on both direction and exists, and is as indicated in the double end on arrow 536.These coupling effects will be seen between all memory cells of the string of the NAND under various level, but coupling influence will be less than the impact on the end memory cell, because the bias voltage on adjacent control grid and floating grid is different from the bias condition of selecting on grid.At erasing voltage pulse duration of existence, the voltage of each floating grid is significantly less than the voltage of selecting grid place's existence.Therefore, the voltage that brings out in each floating grid due to the coupling between the floating grid of individual memory cell will be less than owing to being coupled to the contiguous voltage of selecting grid and bringing out in the floating grid of memory cell endways.Yet each memory cell of NAND string can be expected the corresponding different behavior of wiping that has the slightly different net charge that exists at its floating grid place and bring due to this coupling.
Figure 14 A be illustrated in data after the write store array four states or level Four storage arrangement wipe (E) and the distribution of programming (A, B, C) threshold V T.Figure 14 B is depicted in erase operation and has completed same four status register devices afterwards.Describe separately the threshold voltage distribution for the memory cell of internal word line and end word line.The threshold voltage that 430 displayings that distribute are used for the internal word line distributes, and the internal word line is than deeper being wiped by the 432 end word lines of describing that distribute.In some nand memory device embodiments, owing to being coupled from the capacitive charge of selecting grid, internal memory unit will be wiped than the dark approximately 0.5-1V of end memory cell.Inner and the memory cell of end word line are all compared substantially and are deeper wiped required.For guarantee after the circulation of many write/erases can one erasing voltage pulsed erase all or most of memory cell, the first erasing voltage pulse through selecting the size generally will be greater than the required size in all unit of wiping new equipment (not experiencing many write/erases circulates) in a pulse.Therefore, fresh memory device can have threshold voltage distribution as shown in Figure 14B after the experience erase operation.
When in NAND tandem or higher height (for example, in other unit of block or string) when carrying out the erase verification of many memory cells, between memory cell, diverse erasing time or behavior can cause excessively compressing and some memory cell of over-erasure.For instance, fully wipe the internal memory unit of the end memory cell while possibility over-erasure NAND string of described string in trial.As described previously, internal memory unit will be wiped quickly than end memory cell.If the place carries out checking in the NAND tandem, the NAND string will continue in the pulse of p trap place's reception erasing voltage, until wipe each memory cell of described string so.Therefore, even internal memory unit can fully be wiped after the erasing voltage pulse than end memory cell lesser number, but internal memory unit will receive extra erasing voltage pulse, until each memory cell of described string is verified as through wiping.
Place the pressure larger than necessary pressure on internal memory unit due to over-erasure.The over-erasure internal memory unit of bringing due to slower erasing time of end memory cell can reduce the serviceable life of internal memory unit and whole Nonvolatile memory system.As understanding in this technology, apply larger current potential and compress oxide material on transistorized tunnel oxide.On tunnel oxide sufficiently high current potential apply and many times than the damage that can finally cause oxide skin(coating) that applies of electronegative potential.
Due to can carry out operation bidirectional change wipe after the threshold voltage of memory cell, so between memory cell, the diverse behavior of wiping also can cause the erase operation time to increase.When wiping flash memory cells, to be all have negative threshold voltage in the predetermined negative threshold voltage ranges through erase unit to target.Yet as described, erase process may cause some unit to have negative threshold voltage lower than preset range.Have the memory cell of too low threshold voltage may be subsequently can not correct programming, maybe may cause other unit can not correct programming (probability that for example, occurs by increasing program disturb).Therefore, the device of over-erasure will usually experience so-called soft programming.The memory cell that has significantly lower than the threshold voltage of the value in preset range will receive a small amount of programming, make threshold voltage be elevated to and be in preset range.Soft programming process require to be carried out extra operation and because the erasing time that increases is reduced memory performance, because soft programming is commonly referred to be the part of erase operation.
According to an embodiment, the word line of the storage stack unit just wiped is divided into the subgroup of individual authentication, make extra erasing pulse to be provided to have the selection word line of wiping more slowly memory cell.In this way, comparatively fast wiping the word line can over-erasure, and the memory cell of all the word lines in group will have the threshold voltage distribution of identical (or identical substantially) erase operation after.
Figure 15 is the process flow diagram of describing according to the method for wiping the storage stack unit of an embodiment.Be understood by those skilled in the art that, can operation on a plurality of NAND strings concurrently according to the method for Figure 15, for example to wipe the block of memory cell.In addition, according to described embodiment, also can operate in other unit of unit.In one embodiment, can carry out wiping according to the process flow diagram of Figure 15 for the erase step 340 of Fig. 7.In one embodiment, receive from main frame at controller 318 wipe or the request of the storage stack unit of programming after carry out wiping according to Figure 15.
Make bit line, source electrode line, drain selection gate line and the drain electrode of NAND string select gate line to float in step 440.In step 442, zero volt (or ground connection) is put on each word line of NAND string.Step 440 and 442 realizes comprising the wiping of whole group of memory cell of NAND string or a plurality of NAND strings in parallel.In step 444, with erasing voltage pulse V ErasePut on the p well region of NAND string.In step 446, checking is connected to the memory cell of internal word line for erase status.The memory cell that is connected to end word line is got rid of from checking, made and only verify internal memory unit.Apply by terminad word line the voltage that is enough to connect memory cell (no matter whether it is wiped free of) and come to get rid of end word line from checking.This voltage can be greater than the erase verification voltage E that is applied to the internal word line veri fy。Can use many voltage levels in step 446.For instance, can use enough greatly the voltage that is programmed into the memory cell of high state with connection, but will be only enough in most embodiment greater than the voltage of erase verification voltage slightly.Key factor is, is verifying the internal word line simultaneously, and the memory cell that is connected to end word line is what conduct.
In step 448, determine whether each NAND string is successfully verified as in step 446 to have wiped its internal memory unit.In one embodiment, only conspiring to create merit at each NAND is verified as and thinks that step 448 and internal memory unit wipe successfully when wiping its internal memory unit.In another embodiment, if only the NAND of predetermined number conspires to create merit and is verified as and wipes its internal memory unit, think that so step 448 and internal memory unit wipe successfully.By go here and there to determine that internal memory unit wipes successfully based on the NAND of predetermined number string rather than each NAND, proof procedure can stop (step 450) before reaching maximum erase cycles number.This can be avoided due to one or be difficult on a small quantity wipe or defective NAND string and over-erasure NAND string.
If there is no the NAND string of good authentication all or predetermined number in step 448, method is branched off into step 450 so, wherein checks and verifies counter VC for wiping limits value.The checking counter is used for the number of the repetition of restriction erase cycles.An example wiping restriction is 8, yet can use other value.If the checking counter is less than wiping limits value, VC increases progressively 1 so, and the value V of erasing voltage pulse EraseStepping increases the first step sizes or increment value Δ VERAI.In one embodiment, Δ VERAI is about 0.5V to 1V.
Be chosen in one embodiment the first erasing voltage pulse that step 444 applies for having a value, make before writing erase cycles and afterwards, the unit that is connected to the internal word line is just wiped after applying the first pulse and can over-erasure.In this way, can wipe internal memory unit in a pulse, make for the most of the time, will verify the internal word line after just once the repeating of step 440 to 446.Therefore, Δ VERAI can be relatively little value, in order to just wipe internal memory unit (for example, many write erase cycles after) in those situations that needs further repeat.To discuss more details about the various step sizes that can use according to embodiment referring to Figure 18 A and 18B.
If the checking counter is not less than 8, method proceeds to step 452 so, will not verify that wherein number and the predetermined number of NAND string compares.If not verified number is less than or equal to predetermined number, method proceeds to step 458 so.If the number of not verified string is not less than predetermined number, so in step 454 for the operationral report status of fail.Step 452 is optional.For instance, thinking and to omit step 448 in the embodiment of step 448 success based on being less than whole NAND string.
Step 448 or 452 be after (yes) branch, the memory cell of internal word line has been verified as through wiping.In addition, all memory cells that are connected to all word lines of the group of just wiping increase (electric charge remove with electronics and increase) because step 440 to 446 makes its floating grid electric charge.Yet the end memory cell is not verified as yet and is in erase status.As described previously, these end memory cells are more slowly wiped than internal memory unit.Therefore, after confirming that memory cell has now been wiped faster, notice can be pointed to the end memory cell so that therefore extra wiping to be provided.In this way, the inside of storage stack unit and end memory cell will be erased to approximately identical level after erase operation is completed.
In step 458, will verify that counter VC is reset to zero.In addition, erasing voltage V EraseStepping increases by second and increases progressively size delta VERA 2Δ VERA can be greater than Δ VERAI.In one embodiment, Δ VERA2 can be approximately 1V to 2V.Δ V ER A2Preferably through selecting so that after applying single erasing voltage pulse with the level that increases, will and all wipe afterwards the end memory cell before the write/erase circulation.In step 460, again make bit line, source electrode line, drain selection gate line and drain electrode select gate line to float.In step 462, suppress the internal word line and further wipe and enable end word line for further wiping.Can suppress wiping internal memory unit by the internal word line that floats at follow-up erasing voltage impulse duration.Can apply 0V by terminad word line and enable the end memory cell to wipe.After this condition is set, will be in the first erasing voltage pulse that increases level and put on described group of memory cell.In step 466, for erase status checking end word line, get rid of simultaneously the internal word line from checking.Again, as in step 446, this can apply erase verification voltage by terminad word line, and the voltage that simultaneously applies the memory cell that is enough to connect the internal word line (no matter its state how) to the internal word line is completed.This voltage that puts on the internal word line will be greater than the erase verification voltage that puts on end word line.Yet it should be noted that in certain embodiments, can be for erase status at the whole NAND string of step 466 checking.Internal memory unit has been verified as through wiping, and therefore it should conduct under erase verification voltage applies.Therefore, can be at each memory cell of the described string of step 466 checking in this alternate embodiment.Yet, may preferably apply larger voltage to internal memory unit, so that just to still not verified end word line enforcement checking.
In step 468, determine whether each NAND string is successfully verified as to have wiped its end memory cell.Be similar to step 448, when all or only the NAND of predetermined number conspire to create merit when checking and can be made in determining of step 468 success.If the NAND of all or predetermined number conspires to create the merit checking, pass through state in step 470 report so.If all or predetermined number do not have good authentication, check and verify counter in step 472 for wiping limits value so.If the checking counter is less than restriction, method proceeds to step 474 so, verifies that wherein counter increases progressively 1 and erasing voltage V EraseStepping increases by the 3rd incremental steps size delta VE RA 3
In one embodiment, Δ VERA 3Be the value identical with Δ VERI.In other embodiments, Δ VERA3 is greater than Δ VERAI, because the end memory cell is wiped slow and can be had benefited from larger increment value and wipe to accelerate it. Step 458 and 474 result are that after verifying the internal word line, the erasing voltage pulse increases relatively large at first applying erasing voltage for the terminad memory cell.If need repeatedly to repeat in order to wipe the end memory cell fully, it will increase in a small amount in step 474 so subsequently.Again, hereinafter will discuss more details and the replacement scheme that is used for increment value.If the checking counter is not less than 8, will not verify that in step 476 number and the predetermined number of NAND string compare so.Be similar to step 452, step 476 is optional.If the number of checking string is not less than predetermined number, pass through state in step 470 report so.Yet, if the number of not verifying the NAND string is greater than predetermined number, so in step 454 report status of fail.
Figure 16 is the table of showing the bias condition of the various child-operations of carrying out as the part of the erase operation of Figure 15.Row 480 statements are for the bias condition of the memory cell of wiping all word lines of word line group of just wiping.Row 480 steps 440 to 444 corresponding to Figure 15.In these steps, all memory cells of each word line increase by the electric charge that makes its floating grid from its floating grid metastatic electron.Bit line selects gate line the same unsteady with source electrode line as source electrode and drain electrode.Each word line is provided with 0V and wipes in order to enable it.The p trap receives described erasing voltage, and by means of by applying 0V to the word line and applying V to the p trap EraseAnd the current potential that produces comes the floating grid metastatic electron from each memory cell of described group.
Row 482 statements are used for only verifying for erase status the bias condition of internal word line.Row 482 steps 446 corresponding to Figure 15.Bit line floats, and source electrode line is in V DDDrain electrode selects grid and drain selection gate line to be provided with being enough to connect two kinds of positive voltage V that select grid SGV SG is usually greater than V DDFor instance, V in one embodiment SGCan be approximately 4-4.5V.The internal word line possesses for the erase verification voltage that operates (for example, 0V).Word line WL 0With word line WL nPossesses voltage V Use1V Use1Can be voltage range as discussed previously, but usually through selecting in order to guarantee to be connected in word line WL 0With word line WL nThe conduction of memory cell.For instance, V useI can be greater than any one voltage in the potential voltage of program memory cells.Yet it is enough only using as a rule slightly the value greater than erase verification voltage because after applying the first erasing voltage pulse even the end memory cell also wipe to a certain extent.By using V useI is as being applied to word line WL 0With word line WL nVoltage, in step 446, the end memory cell is got rid of in word line verification operation internally.In order to verify whether internal memory unit wipes, the bias condition of row 482 is applied to NAND string and readout bit line voltage.If internal memory unit is wiped fully deeply, it will be in on-state and conducting path from the source electrode line to the bit line will be provided so.To go here and there inducing current and bit-line voltage by NAND will increase.After schedule time amount, read or check bit-line voltage by sensor amplifier.If bit-line voltage has reached predetermined level, internal memory unit is verified as through wiping so.Therefore if internal memory unit is not wiped fully deeply, it will can not be in on-state and will can not conduct any electric current and maybe will conduct the electric current of minute quantity so.Thus, bit-line voltage will can not be increased to predetermined level.When readout bit line voltage after schedule time amount, it will can not reach predetermined level and internal memory unit and will can not be verified as through wiping.
Row 484 statements are used for only wiping the bias condition of the memory cell of the end word line that is connected to described group of just wiping.Row 484 steps 460 to 464 corresponding to Figure 15.As wiping all word lines, bit line, source electrode line, drain selection gate line and drain electrode select gate line all to float.In addition, the p trap will be provided with erasing voltage V EraseFor further wiping of the memory cell that suppresses internal word line (being verified as through wiping), the internal word line floats, and end word line possesses 0V.In this way, the internal word line will be coupled to the p trap and not produce in the tunnel dielectric district of connected memory cell and wipe current potential.Yet by terminad word line supply 0V, those memory cells will be activated to wipe.Therefore, when being applied to the p trap, the erasing voltage pulse only wipes the memory cell of end word line.
Row 486 statements are used for only verifying the bias condition of the erase status of end word line.Row 486 steps 466 corresponding to Figure 15.As the internal word line verification operation of same column 482, bit line floats, and source electrode line is in V DDP trap ground connection and drain electrode select grid and drain selection grid by voltage V SGConnect.In order to verify end word line eliminating internal word line from checking simultaneously, with erase verification voltage E Veri fY (for example, 0V) is applied to word line WL 0And WL n, simultaneously with V Use1Be provided to the internal word line.V CSeiTo guarantee the conduction of the memory cell of internal word line, and make and to test the only erase status of end word line.If the end memory cell is fully wiped, it will apply E so veri fConnect under y voltage.Bit-line voltage will be increased to or surpass indicates the predetermined level of end memory cell through wiping.If the end memory cell is not fully wiped, it will remain open or apply E so Ve π fAt least can fully not connect under y voltage.Bit-line voltage will can not be increased to the predetermined level that indication end memory cell is wiped not yet.As previously discussed, can verify alternatively whole NAND string, because before verified internal memory unit in step 446.Therefore, erase verification voltage can be applied to the internal word line and be used for the checking of end word line, because it can conduction under erase verification voltage.Yet that possibility is useful is supply V Use1To guarantee conduction, in order to only test the erase status of end memory cell.
The improvement erase threshold voltage of Figure 17 A describes to wipe according to embodiment to Figure 17 C storage stack unit distributes.Figure 17 A is illustrated in data the wiping and programmed threshold voltage distribution of level Four nand memory device after the write store array.Figure 17 B is illustrated in single erasing voltage pulse and applies the erase threshold voltage distribution of completing the memory cell that installs afterwards.For instance, Figure 17 B can be corresponding to the time of completing the step 444 of Figure 15 according to the bias condition (row 480) of Figure 16.Usually, and as shown in Figure 17 B, after applying the first erasing voltage pulse, only the memory cell of internal word line (distributing shown in 430) will fully be wiped.The memory cell of end word line (distributing shown in 432) makes negative charge remove from its floating grid, but not enough, makes it be in the actual erase state.This is that the different word lines that bring due to the selection grid of end word line and coupling between floating grid diverse wiped behavior.Figure 17 C is illustrated in the erase threshold distribution of subgroup of memory cell after the end word line that only extra erasing pulse is applied to described group of just wiping.For instance, the time after Figure 17 C can complete corresponding to the step 464 of Figure 15.This can be after being applied to end word line with an extra erasing pulse, or after the repeatedly repetition by step 460-474 applies a plurality of erasing pulses.Owing to using the method for describing in Figure 15 and 16, the internal word line makes connected memory cell be erased to similar threshold voltage with end word line.Therefore, prevented due to the over-erasure of wiping more slowly the next bosom word line of end word line strap.The checking of the different subgroups by dividing memory cell has compensated the diverse behavior of wiping, makes all memory cells finish in approximately identical threshold voltage distributes.
Can carry out by different way in other embodiments the division of word line in the NAND string.For instance, two least significant end word line (for example, WL of NAND string 0, WL 1, WL n-1And WL n) can be combined in together as end word line, and remaining word line (WL 2-WL n-2) combine as the internal word line.In this embodiment, the step 446 of Figure 15 will comprise authenticator line WL 2-WL n-2, and step 462 and 466 will be carried out further to wipe and authenticator line WL 0, WL 1, WL n-1And WL nIn another embodiment, six or six above word lines can be combined in together as end word line.Also can implement other combination.
Figure 18 A and 18B describe can be according to the erasing voltage signal of various embodiment uses.Figure 18 A shows the first erasing voltage pulse, and it is for having value V EraseiPulse.The first pulse can be the first pulse of the groups of memory cells of step 444 place that is applied to Figure 15 just wiping.This pulse is used for wiping all memory cells of described group.In certain embodiments, the first value of erasing pulse can be approximately 15V to 20V.In one embodiment, preferably with before write/erase circulation and afterwards, the unit on the internal word line will be wiped (and not can over-erasure) just after applying single erasing voltage pulse mode is selected the value of the first erasing pulse.Yet after write/erase circulation, or due to the diverse parameter of the storage arrangements of indivedual structures, all internal memory unit may not be wiped free of after the first pulse.In other embodiments, the first erasing voltage pulse can be through selecting so that only before the write/erase circulation or only in a limited number of write/erase cycle period, internal memory unit will be wiped after applying the first pulse.After the write/erase circulation of expansion, may need more pulse.Over-erasure when this technology can reduce write/erase circulation beginning, its cost are more erasing voltage pulses after the write/erase circulation of expansion.
As shown in Figure 18 A, be successfully verified as at the internal word line and apply the second pulse pulse before wiping 2The erasing voltage signal is from pulse 1To pulse 2Increase step size, delta V ERAI.Increase Δ VERAI corresponding to the step 456 of Figure 15.Δ VE in one embodiment RAI can be approximately 0.5V to 1V.After applying the second erasing voltage pulse, all internal word lines are successfully verified.This can be corresponding to the step 448 of Figure 15.After all internal word line empirical tests, only continue to wipe for the end memory cell.These memory cells are wiped more slowly, therefore for the 3rd erasing voltage pulse pulse 3Apply, the erasing voltage signal increases by the second larger incremental steps size delta V ERA 2This can be corresponding to the step 458 of Figure 15.Preferred Δ VERA in one embodiment 2Through selecting so that apply the first erasing voltage pulse (for example, pulse at terminad memory cell only 3) afterwards, before write/erase circulation and all will wipe afterwards all end memory cells.In one embodiment, Δ VERA 2Be approximately 2 volts.Pulse 3Apply step 464 corresponding to Figure 15.Increase by the 3rd step size, delta VE with afterpulse RA 3This is corresponding to the step 474 of Figure 15.Δ V ERA 3Can equal Δ V in one embodiment ERAI, or in other embodiments can be greater or lesser.
Figure 18 B describes the alternate embodiment of spendable erasing voltage signal when carrying out the method for Figure 15.In this embodiment, the first erasing voltage pulse choice is greater than the second pulse.The first erasing voltage pulse pulse 15Through selecting to cause larger variation (for example, approximately 6V).This erasing voltage pulse is still selected so that after applying individual pulse through ideal, before the write/erase circulation of a certain number and will wipe internal memory unit afterwards.Yet recognize, may wipe all internal memory unit with an above pulse in some cases.In other embodiments, the first erasing voltage pulse can be through selecting so that only before the write/erase circulation or only in a limited number of write/erase cycle period, internal memory unit will be wiped after applying the first erasing voltage pulse.After the write/erase circulation of expansion, may need more pulse.In the embodiment of Figure 18 B, being verified as in all internal memory unit needed the second and the 3rd pulse before wiping.The second erasing voltage pulse pulse 2Compare pulse 1Little step size, delta V ERA4.Successively decreasing also corresponding to the step 456 of Figure 15 of erasing voltage signal.Yet, be not to increase progressively the erasing voltage pulse, its size reduces Δ VERA 4This guarantees that internal memory unit can over-erasure after applying the second erasing voltage pulse.Make the second pulse less, to cause less skew in the threshold voltage of memory cell.If need the 3rd erasing voltage pulse, as pulse 3Shown in, so then can make it increase step size, delta VE RAI continues to shift from the floating grid of those memory cells to guarantee electronics.
After applying the 3rd erasing voltage pulse, internal memory unit is verified as through wiping.The remainder of Figure 18 B is identical with Figure 18 A.Through applying the first erasing voltage pulse pulse with lucky adjusting end memory cell 4Increase value Δ V from last erasing voltage impulse magnitude ERA 2-.This is corresponding to the step 458 of Figure 15.In the embodiment of Figure 18 B, need extra erasing voltage pulse to wipe the end memory cell.So the 5th erasing voltage pulse pulse 5Added value Δ VE RA3Surpass the 4th erasing voltage pulse value.In one embodiment, applying the first erasing voltage pulse pulse 1Afterwards, the second erasing voltage pulse pulse 2Can have and pulse 1Identical size rather than size reduce.In this embodiment, subsequently in order to wipe the required any erasing voltage pulse of internal memory unit all with added value Δ VERAI, as shown.
Figure 19 is the process flow diagram according to the method for an embodiment of describing for the step 456 of carrying out Figure 15.In Figure 19, the erasing voltage pulse by Figure 18 B comes execution in step 456 as shown.In the step 450 of Figure 15, at first determine that in step 490 whether checking counter VC equals zero, and indicates so far only erasing voltage pulse to be applied to groups of memory cells.If the checking counter equals zero, indicating this is change for the first time to the erasing voltage impulse magnitude, and then method proceeds to step 492, and wherein the stepping of erasing voltage impulse magnitude reduces to be worth Δ V ERA4This will cause applying during next repeats and be similar to pulse 2Pulse.If yet the checking counter is not equal to zero, indicate this be to the erasing voltage signal for the second time or more times change, then method proceeds to step 494, wherein the stepping of erasing voltage signal increases Δ VERAI, causes being similar to the pulse of Figure 18 B 3Pulse.From step 492 and 494, method again proceeds to the step 440 of Figure 15.
Capacitive couplings also can cause diverse behavior between the memory cell of so-called soft programming operating period NAND string.Usually implement the soft programming operation by apply simultaneously the soft programming pulse to all the word lines through selecting block.Carry out soft programming after wiping the storage stack unit.Carry out soft programming so that the narrowed width of the erase threshold distribution of described group of memory cell, and the erase threshold distribution standardization of individual memory cell in also making described group.The soft programming pulse (for example, as shown in Figure 6), arrives programming state to avoid the unit lower than the conventional programming pulse on amplitude.What expect as the soft programming result is that the unit has narrower erase threshold voltage distribution.Therefore, do not expect that threshold voltage shift is in the programming state scope.
After applying each soft programming pulse, implementation of class is similar to the verification operation of typical erase verification operation shown in Figure 10.During the checking of soft programming operation, test the conduction of going here and there by NAND by each memory cell that receives erase verification voltage at its grid.In case the NAND of a certain number in selecting block string has arrived non-conduction condition (at least one unit of the described string of indication has reached the erase verification level) in erase verification operating period, soft programming finishes so.The result of soft programming is the upwards skew and more near the erase verification level of the distribution of wiping memory cell in described string.By using soft programming, even the initial over-erasure of memory cell, upward displacement is to the level near the erase verification level but erase threshold voltage distributes also.
Due to from selecting grid to the capacitive couplings of the memory cell of the end word line of NAND string, the soft programming behavior of the memory cell of described string is different.Select the capacitive couplings between grid and end memory cell slack-off in soft programming operating period chien shih these unit.Therefore, can expect that the memory cell of end word line will be in the erase status darker than the erase status of internal word line after soft programming.
Figure 20 is illustrated in the erase threshold voltage distribution of the memory cell of NAND string afterwards of experience soft programming.Distribution 430 is depicted in the experience soft programming erase threshold distribution of internal word linear memory unit afterwards.Soft programming has made this erase threshold voltage distributions shift and more near the erase verification level.The checking that is used for soft programming owing to applying under erase verification voltage as non-conduction when the NAND of predetermined number string is verified as successfully soft programming with cell group, and therefore the unit of a certain number will make its threshold voltage shift surpass the erase verification level.Has the actual verification scheme that will depend on employing higher than the actual number of the threshold voltage of erase verification level.For instance, if scheme when single string becomes non-conduction with soft program verification for completing, the only unit in group can be higher than the checking level so.In other scheme, the thousands of unit in group can make its threshold voltage shift just surpass the erase verification level.The threshold voltage of end memory cell is described in distribution 432.Due to the slower soft programming time of end memory cell, its threshold voltage is along with not being offset near the erase verification level.
According to an embodiment, the word line of storage stack unit is divided into subgroup again, make the mode of indivedual subgroup needs that can be suitable for the word line implement soft programming.Method is similar to the erase verification method of describing in Figure 15.All word lines of positive soft programming in described group all experience certain initial soft programming.After described group of memory cell of checking or the successful soft programming of its subgroup, can only carry out extra soft programming for end word line, in order to it is shifted out its darker erase status also more near the erase verification level.
Figure 21 describes to be used in one embodiment the method for soft programming.For instance, the method for Figure 21 can be used for a plurality of NAND strings of the block of memory cell are carried out soft programming.In one embodiment, can carry out soft programming according to Figure 21 for the soft-program step 342 of Fig. 7.In step 602, with soft-program voltage signal V SP GM is set as its initial value and soft programming counter SPC is set as zero.In step 604 with source electrode line, bit line and drain selection gate line ground connection.In addition, with V SGBe applied to drain electrode and select gate line.Can just will drain before applying the soft programming pulse and select the gate line lower voltage to arrive approximately 2.5V, suppress (step 617) to allow when needed boosting to carry out soft programming.Not so in other cases.Soft programming suppresses still (step 617) can occur on a certain degree by the raceway groove that will be elevated to VDD.In step 606, the first soft programming pulse is applied to all word lines of the group of described positive soft programming.In step 608, use the erase verification voltage level to verify the memory cell of all word lines for erase status.In one embodiment, step 608 can comprise the memory cell of only verifying the internal word line, guarantees simultaneously the conduction of end memory cell.Yet, in any case the memory cell of end word line all will conduct applying under erase verification voltage as a rule because it is than the memory cell of internal word line soft programming more slowly.
In step 610, in the block with positive soft programming, number and the predetermined number of non-conduction NAND string compare.If the number of non-conduction string is not more than predetermined number, in step 612, soft programming counter SPC and predetermined limits value (for example 20) are compared so.If the soft programming counter is not less than 20, operate in step 614 report status of fail for soft programming so.If the soft programming counter is less than 20, method proceeds to step 616 so, wherein soft programming counter SPC increase progressively 1 and the stepping of soft-program voltage signal increase predetermined value.In step 617, the NAND of non-conduction during the checking of step 608 (successful soft programming) goes here and there suppressed further soft programming.Can be by apply for example V to respective bit line DDHigh voltage suppress soft programming in specific NAND string.By the rising bit-line voltage, the channel region through suppressing the NAND string will boost to high voltage in next soft programming cycle period.Voltage difference between the floating grid of memory cell and the channel region through suppressing the NAND string is with too low and can not impel the further soft programming of unit.Method then proceeds to step 604 to apply extra soft programming pulse to described group of memory cell.
If the number of non-conduction string is greater than predetermined number, the instruction memory unit successfully experiences soft programming, resets soft programming counter SPC in step 618 so.In one embodiment, step 618 can further comprise increases the soft-program voltage signal.In one embodiment, the increase at step 618 place can with step 616 in identical or be another value.For example in one embodiment, in step 616, soft-program voltage signal incremental steps size delta V Spgm1In step 618, but its incremental steps size delta V Spgm2, it can be greater than Δ V SpgmiCan use in one embodiment the soft-program voltage signal of the erasing voltage signal that is similar to Figure 18 A.
In step 620, with source electrode line, bit line and drain selection gate line ground connection and with V SGBe applied to drain side and select gate line.In step 622, suppress the soft programming of internal word line.Can 0V suppresses the soft programming of internal word line to the less positive voltage of the order of magnitude of 3V by apply approximately to the internal word line.In one embodiment, the voltage that is applied to the internal word line large and for about 5V to the order of magnitude of 10V.For instance, the described voltage voltage that can be usually the channel region through applying to promote string passes through voltage (V with what suppress programming or soft programming PaSs).For the NAND string (being verified as through soft programming) of suppressed further soft programming in further the repeating of step 618-634, high voltage is fully boosted to avoid further soft programming with the channel region of sufficient to guarantee through suppressing the NAND string.In step 624, the soft programming pulse only is applied to the end word line of the group of just wiping, in order to further the end memory cell is carried out soft programming.In step 626, for erase status checking end memory cell word line, guarantee simultaneously the conduction of internal word line and do not consider its state (getting rid of the internal word line from checking).The erase verification voltage level can be applied to end word line, and with voltage V Use1(conduction of sufficient to guarantee internal word line) is applied to the internal word line.In this way, only carry out checking for end word line, get rid of simultaneously the internal word line from checking.
In step 628, number and the predetermined number of the non-conduction string determined in step 626 compared.If the number of non-conduction string is greater than predetermined number, the unit of indication end word line is upward displacement and close to the erase verification level, method proceeds to step 630 so now, and wherein state is passed through in report.If the number of non-conduction string is not more than predetermined number, so soft programming counter and predetermined limits value are compared.If the soft programming counter is greater than predetermined limits value, so for operating in step 614 report status of fail.If yet the soft programming counter increases progressively 1 and make the stepping that makes progress of soft-program voltage signal in step 634 with the soft programming counter so less than predetermined limits value.In step 635, the NAND of non-conduction during the checking of step 626 (successful soft programming) goes here and there suppressed further soft programming.Method then proceeds to step 620 to carry out the further soft programming of end memory cell.
In one embodiment, step 634 makes the soft-program voltage signal increase progressively the size identical with step 616, and in other embodiments, uses other value.For instance, if use the soft-program voltage signal of the erasing voltage signal that is similar to Figure 18 B, step 634 can comprise so increases size delta V Spgm3(be similar to Δ VE RA3), step 618 can comprise increases size delta V Spgm2(be similar to Δ VE RA 2), and step 616 can comprise increase size delta V SpgmI (being similar to Δ VERAI).In this embodiment, step 616 reduces size delta V during can further being included in the first repetition Spgm4(be similar to Δ VE RA4) and for follow-up repeat to increase size delta Vs Pgm1
Can carry out by different way the division for word line in the NAND string of soft programming in different embodiment.For instance, two least significant end word lines (for example, WL0, WL1, WL of NAND string n-1And WL n) can be combined in together as end word line, and remaining word line (WL2-WL n-2) combine as the internal word line.In this embodiment, the step 622 of Figure 21 will comprise and suppress word line WL2-WLn-2, and with execution in step 624 and 626 with further to word line WL0, WL1, WL n-IAnd WL nCarry out soft programming and checking.In another embodiment, six or six above word lines can be combined in together as end word line.Also can implement other combination.
Figure 22 states the bias condition of the various operations of the process flow diagram of describing for Figure 21.Row 640 are stated the bias condition of the soft programming operation of all memory cells of just wiping group.Row 640 steps 604 to 606 corresponding to Figure 21.Bit line, source electrode line and p trap are in 0V to carry out soft programming.V DDBe shown as for bit-line voltage band bracket, with indication V DD is applied to those NAND strings of suppressed soft programming.Source side selects gate line to be in 0V, and drain side selects gate line to be in V SGWith soft programming pulse V spg mBe applied to each word line of described group, so that the threshold voltage of connected each memory cell that raises.
Row 642 statement is used for verifying the bias condition of soft programming of all memory cells of described group.Row 642 steps 608 corresponding to Figure 21.These bias conditions are identical with those bias conditions wiped that are used for all memory cells of checking storage stack unit.Bit line floats and the p trap is in 0V, and with VD DBe provided to source electrode line.Select grid by V for two SGConnect.Erase verification voltage is applied to each word line to determine the whether non-conduction and therefore have the memory cell that at least one has reached the erase verification level of described string.
Row 644 statements are used for only end word line being carried out the bias condition of soft programming.Row 644 steps 620 to 624 corresponding to Figure 21.By with VS GBe fed to drain side and select gate line to connect drain side selection grid, and select gate line to disconnect source side selection grid by 0V being fed to source side.Provide low positive voltage V to the internal word line Use1(for example, 0V is to 5V).By to the less positive voltage of internal word line supply, connected memory cell can be suppressed in and apply further programming under the soft programming pulse.End word line receives soft programming pulse V SP GM is in order to experience further soft programming.When being verified as through the suppressed further soft programming of the NAND of soft programming string, be applied to the value V of internal word line usEi (for example, can be relatively high voltage V pa ss = 5 V - 10 V ) rather than less positive voltage.Because V DDRelatively high voltage also is applied to the bit line of the string through suppressing, so will cause the channel region through suppressing the NAND string to boost to high voltage in next soft programming cycle period.Floating grid and the voltage difference between the channel region through suppressing the NAND string of this maintenance memory cell are low fully, make the further soft programming of unit can not occur.
Row 646 statements are used for the only soft program verification bias condition of end word line.Row 646 can be corresponding to the step 626 of Figure 21.Bit line floats, and source electrode line is in VDD.The p trap is in zero volt.By with V SOBeing fed to drain electrode selects gate line and drain selection gate line to connect the selection grid.With V USEi is applied to the internal word line.As above discuss the V that uses during soft programming Use1Value (row 644) in some cases can be greater than 0V to 3V.The V that is used for checking useThe value of i is that 0V is to the order of magnitude of 3V.It only need to be in conducted state to guarantee the unit that in the internal word line, soft programming has been completed higher than erase verification voltage.In this way, can independently determine and verify the state of memory cell on end word line.Therefore, the value of the Vuse1 that uses during soft programming (for example, 5V is to 10V) can be different from the value (for example, 0V is to 3V) of using during soft program verification.Erase verification voltage or 0V are applied to end word line.In this way, get rid of the internal word line from soft program verification, end word line experience checking simultaneously.
Figure 23 is depicted in experience according to the threshold voltage distribution of storage stack unit after the soft programming of the embodiment of Figure 21 and 22.As shown in figure 23, inner and erase threshold distribution end word line has all moved up near the erase verification level.Internal word line threshold voltage distribution 430 upwards is offset near the erase verification level, as usually occuring.End word line distributes 432 because extra soft programming (step 618-635) moves up near the erase verification level.
Above-mentioned example is to provide for NAND type flash memory.Yet principle of the present invention is applicable to utilize the nonvolatile memory of other type of cascaded structure, comprises those storeies that the new technology of just developing is used in current existing those storeies and expection.
Presented foregoing detailed description of the present invention for explanation and description purpose.Do not wish that it is precise forms detailed or that limit the invention to disclose.In view of above teaching, many modifications and variations are possible.Described embodiment is through selecting in order to explain best principle of the present invention and application in practice thereof, makes by this others skilled in the art and utilize best the present invention with various modifications with the various embodiment forms that are suitable for desired application-specific.Wish that scope of the present invention is defined by appending claims.

Claims (33)

1. the system of a soft programming nonvolatile memory, it comprises:
Be used for each non-volatile memory device of one group of non-volatile memory device is programmed, until described group is verified as the device that reaches target level;
Be used for being verified as at described group the device that stops after reaching described target level the programming of each non-volatile memory device of the first subgroup of described one group of non-volatile memory device; And
Be used for the device that continuation is programmed to each non-volatile memory device in the second subgroup of described one group of non-volatile memory device after stopping the programming of described first each non-volatile memory device of subgroup.
2. system according to claim 1, wherein said device for each non-volatile memory device of described one group of non-volatile memory device is programmed comprises:
Be used for applying one or more programming pulses to each non-volatile memory device of described group, until described group is verified as the device that reaches described target level; And
Be used for described group of device that whether has reached described target level of checking between each pulse that applies described one or more programming pulses.
3. system according to claim 2, wherein said be used to verifying that described group of device that whether has reached described target level comprises:
Be used for verifying whether the non-volatile memory device of described the first subgroup has reached described target level, get rid of simultaneously the device of the non-volatile memory device of described the second subgroup from checking.
4. system according to claim 2, wherein:
Described device for applying one or more programming pulses comprises between each pulse that applies described one or more programming pulses, makes the device of size increase by first step sizes of described one or more programming pulses; And
Described device for continuing each non-volatile memory device of described the second subgroup is programmed comprises:
Be used for applying one or more extra programming pulses to each non-volatile memory device of described the second subgroup, until described group is verified as the device that reaches described target level; And
Be used between each pulse that applies described one or more extra programming pulses, make the device of size increase by second step sizes of described one or more extra programming pulses.
5. system according to claim 4, wherein:
Described one or more programming pulses are included in described group and are verified as to reach and are applied to the last programming pulse of described group before described target level; And
Described device for applying one or more extra programming pulses comprises for before applying the one of described one or more extra programming pulses, makes the size of described last programming pulse increase the device of the 3rd step sizes for the described one in described one or more extra programming pulses.
6. system according to claim 4, wherein:
Described the first step sizes and described the second step sizes are identical step sizes.
7. system according to claim 2, wherein said device be used to applying one or more programming pulses comprises:
Be not verified as through wiping if be used for described group, make so the size of described one or more programming pulses reduce the device of the first step sizes after applying the first programming pulse; And
Be not verified as through wiping if be used for applying the second programming pulse after described group, make so the device of described big or small increase by second step sizes of described one or more programming pulses applying described the second programming pulse after.
8. system according to claim 1, wherein:
The non-volatile memory device of described the first subgroup comprises the internal non-volatile memory element of described group; And
The non-volatile memory device of described the second subgroup comprises the end non-volatile memory device of described group.
9. system according to claim 8, wherein:
Described the second subgroup comprises the first non-volatile memory device of the first selection grid that is adjacent to described group and is adjacent to the second non-volatile memory device of the second selection grid of described group.
10. system according to claim 9, wherein:
Described the second subgroup further comprises the 3rd non-volatile memory device that is adjacent to described the first non-volatile memory device and the 4th non-volatile memory device that is adjacent to described the second non-volatile memory device.
11. system according to claim 1, wherein:
The NAND string that described one group of non-volatile memory device is non-volatile memory device.
12. system according to claim 1, wherein:
Described one group of non-volatile memory device is one group of multimode flash memory device.
13. the method for a soft programming nonvolatile memory, it comprises:
Each non-volatile memory device in one group of non-volatile memory device is programmed, until described group is verified as and reaches target level;
Be verified as at described group the programming that stops after reaching described target level each non-volatile memory device in the first subgroup of described one group of non-volatile memory device; And
Continue after the programming of each non-volatile memory device each non-volatile memory device in the second subgroup of described one group of non-volatile memory device is programmed in stopping described the first subgroup.
14. method according to claim 13, wherein said each non-volatile memory device in one group of non-volatile memory device is programmed comprises:
Each non-volatile memory device to described group applies one or more programming pulses, until described group is verified as and reaches described target level; And
Verify described group between each pulse in applying described one or more programming pulses and whether reached described target level.
15. method according to claim 14 verifies wherein whether described group reached described target level and comprise:
Whether the non-volatile memory device of verifying described the first subgroup has reached described target level, gets rid of simultaneously the non-volatile memory device of described the second subgroup from checking.
16. method according to claim 15, whether described the first subgroup of wherein said checking has reached described target level comprises:
Each non-volatile memory device in described the first subgroup applies verifying voltage and each non-volatile memory device in described the second subgroup and applies voltage greater than described verifying voltage.
17. method according to claim 14, wherein:
Apply one or more programming pulses and be included between each pulse that applies in described one or more programming pulses, make the size of described one or more programming pulses increase by the first step sizes; And
Described continuation is programmed to each non-volatile memory device in described the second subgroup and is comprised:
Each non-volatile memory device in described the second subgroup applies one or more extra programming pulses, until described group be verified as and reach described target level, and
Between each pulse in applying described one or more extra programming pulses, make the size of described one or more extra programming pulses increase by the second step sizes.
18. method according to claim 17, wherein:
Described one or more programming pulses are included in described group and are verified as to reach and are applied to the last programming pulse of described group before described target level; And
Described applying before one or more extra programming pulses are included in the one that applies in described one or more extra programming pulses makes the size of described last programming pulse increase by the 3rd step sizes for the described one in described one or more extra programming pulses.
19. method according to claim 17, wherein:
Described the first step sizes and described the second step sizes are identical step sizes.
20. method according to claim 14, wherein said one or more programming pulses that apply comprise:
If described group is not verified as through wiping, make so the size of described one or more programming pulses reduce the first step sizes after applying the first programming pulse; And
If described group is not verified as through wiping after applying the second programming pulse, make so the size of described one or more programming pulses increase by the second step sizes after applying described the second programming pulse.
21. method according to claim 20, wherein continuing each non-volatile memory device in described the second subgroup is programmed comprises:
Each non-volatile memory device to described the second subgroup applies one or more extra programming pulses; And
Make the size of described one or more extra programming pulses increase by the 3rd step sizes between each pulse in applying described one or more extra programming pulses.
22. method according to claim 21, wherein:
Described the second step sizes and described the 3rd step sizes are identical sizes.
23. method according to claim 21, wherein:
Described one or more programming pulses are included in described group and are verified as to reach and are applied to the last programming pulse of described group before described target level; And
Described applying before one or more extra programming pulses are included in the one that applies in described one or more extra programming pulses makes the size of described last programming pulse increase by the 4th step sizes for the described one in described one or more extra programming pulses.
24. programming to each non-volatile memory device in described the second subgroup, method according to claim 13, wherein said continuation comprise:
Whether reached described target level by the non-volatile memory device of verifying described the second subgroup, get rid of simultaneously the non-volatile memory device of described the first subgroup from checking, verify whether described one group of non-volatile memory device has reached described target level, wherein said continuation is programmed to each non-volatile memory device in described the second subgroup and is continued to carry out, and reaches described target level until described the second subgroup is verified as.
25. method according to claim 24, whether the non-volatile memory device of wherein verifying described the second subgroup has reached described target level comprises:
Whether described the second subgroup of checking has reached described target level when at least one non-volatile memory device of described the second subgroup reaches described target level.
26. method according to claim 24 verifies wherein whether described the second subgroup has reached described target level and got rid of described the first subgroup simultaneously from checking and comprise:
Each non-volatile memory device in described the second subgroup applies verifying voltage; And
Apply voltage greater than described verifying voltage to each non-volatile memory device of described the first subgroup.
27. method according to claim 13, wherein:
Described each non-volatile memory device in one group of non-volatile memory device is programmed to comprise apply one or more soft programming pulses; And
Described target level is the soft programming target level.
28. method according to claim 13, wherein:
The non-volatile memory device of described the first subgroup comprises the internal non-volatile memory element of described group; And
The non-volatile memory device of described the second subgroup comprises the end non-volatile memory device of described group.
29. method according to claim 28, wherein:
Described the second subgroup comprises the first non-volatile memory device of the first selection grid that is adjacent to described group and is adjacent to the second non-volatile memory device of the second selection grid of described group.
30. method according to claim 29, wherein:
Described the second subgroup further comprises the 3rd non-volatile memory device that is adjacent to described the first non-volatile memory device and the 4th non-volatile memory device that is adjacent to described the second non-volatile memory device.
31. method according to claim 13, wherein:
The NAND string that described one group of non-volatile memory device is non-volatile memory device.
32. method according to claim 13, wherein:
Described one group of non-volatile memory device comprises a plurality of NAND strings;
When the described a plurality of NAND of predetermined number string was confirmed as comprising the non-volatile memory device that at least one has reached described target level, described group was verified as and reaches described target level.
33. method according to claim 13, wherein:
Described one group of non-volatile memory device is one group of multimode flash memory device.
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