CN101221958B - Thin film transistor array panel having a means for visual inspection and a method of performing visual inspection - Google Patents
Thin film transistor array panel having a means for visual inspection and a method of performing visual inspection Download PDFInfo
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- CN101221958B CN101221958B CN2007101996289A CN200710199628A CN101221958B CN 101221958 B CN101221958 B CN 101221958B CN 2007101996289 A CN2007101996289 A CN 2007101996289A CN 200710199628 A CN200710199628 A CN 200710199628A CN 101221958 B CN101221958 B CN 101221958B
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Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
The invention discloses a thin film transistor array panel with a visual inspection means and a method of performing visual inspection. The thin film transistor array panel includes: a first signal line formed on an insulating substrate, a second signal line formed on the insulating substrate and insulated with and intersecting the first signal line to define a display area, a plurality of driving signal lines formed on a surrounding area of the insulating substrate, a plurality of inspection signal lines formed on the surrounding area of the insulating substrate, a first thin film transistor for inspection having a drain electrode coupled to the first signal line, a source electrode coupled to any one of the inspection signal lines and a gate electrode coupled to any one of the driving signal lines, and a second thin film transistor for inspection having a drain electrode coupled to the second signal line, and a source electrode coupled to any one of the inspection signal lines and a gate electrode coupled to any one of the driving signal lines. The plurality of driving signal lines are connected to connected to a Voff voltage applying terminal and driving signal application welding points for inspection.
Description
Present specification is dividing an application of the 02122790.X application for a patent for invention submitted on June 13rd, 2002.
Technical field
The present invention relates to a kind of thin-film transistor display panel, especially relate to a kind of visual inspection (visualinspection) device and integrated therein method of carrying out visual inspection in the thin-film transistor display panel of gate driver circuit.
Background technology
Thin-film transistor display panel is as the circuit board of each pixel of drive in LCD (LCD) or organic electroluminescent (EL) display or the like; In thin-film transistor display panel, the image signal line or the data wire that are used to transmit the scan signal line or the gate line of sweep signal and are used for the images signal have been formed.Wherein also formed the thin-film transistor that is connected to gate line and data wire, be connected to pixel electrode on the thin-film transistor, be used to cover and the gate insulator of insulated gate polar curve and the passivation layer that is used to cover and be used for insulation film transistor and data wire.Thin-film transistor comprises with the semiconductor layer, gate insulator and the passivation layer that form passage as the gate electrode of a gate line part, source electrode with as the drain electrode of a data wire part.Thin-film transistor is a switch element, and it will be sent on the pixel electrode through data wire image transmitted signal according to the sweep signal through the gate line transmission.
LCD is the representative that utilizes the display unit of this thin-film transistor display panel, especially like most of COG (glass top chip) type that adopts of the middle-size and small-size LCD of reflection-type or transflective LCD.In this case, visual inspection (visual inspection) (VI) and overall test (gross test) (GT) carry out before the COGIC installation steps so that save expensive COG IC, polarizer and compensation film, and improve output.Because test needs expensive equipment, need the very long processing time in addition, therefore be difficult to GT is applied in the real process.In addition; Available VI carries out after the lead that is formed for checking at present, and this lead is connected on the gate line and data wire between the COG terminal, or is connected on the opposite side; To carry out VI; Then, carry out diamond cut, or carry out laser cutting and come separately to be used to the lead checked with panel.In this case, in this cutting process, produce contaminant particle, perhaps lead is corroded through its cutting side, thereby makes reliability decrease.
Simultaneously, the TFT panel can be through following method manufacturing, that is, and and drive integrated circult or integrally be formed directly on the thin-film transistor partly or as.As this example, there are polycrystalline SiTFT panel (multi-crystal TFT panel) and amorphous drive integrated circult panel (a-siIC panel).As in the method that integrally directly forms drive IC, GT can carry out through TFT self on the TFT panel.Yet only on the TFT panel, directly forming, the method for a part of drive IC needs expensive equipment to carry out GT.
In addition,, after inspection, be difficult to adopt laser cutting because the drive IC that is formed on the TFT workpiece act as barrier when laser cutting, and because the TFT panel forms identical size with filter, so be difficult to obtain to be used for the space of laser cutting.
Summary of the invention
The present invention is through addressing these problems the reliability that has improved LCD.
The invention provides a kind of device that is used for carrying out visual inspection at thin-film transistor with drive integrated circult.
The present invention also provides a kind of method that is used for carrying out at the thin-film transistor with drive integrated circult visual inspection.
In one aspect, the invention provides a kind of thin-film transistor display panel, it comprises the logical circuit that is used for VI, and this circuit is connected between gate driver circuit and the gate line, to apply grid inspection signal.
Say that at length thin-film transistor display panel comprises the dielectric substrate that has the viewing area and center on the zone; Be formed on first holding wire on the dielectric substrate; Be formed on the dielectric substrate and with insulation of first holding wire and the secondary signal line with the qualification viewing area of intersecting; What be formed on dielectric substrate goes up and is connected to V around the zone
OffVoltage applies many drive signal lines on the terminal; Be formed on many inspection holding wires on the zone that center on of dielectric substrate; The first film transistor that is used to check, it has the drain electrode that is connected on first holding wire, be connected to arbitrary on the inspection holding wire source electrode and be connected to the gate electrode on arbitrary the drive signal line; And second thin-film transistor that is used to check, it has the drain electrode that is connected on the secondary signal line, be connected to arbitrary on the inspection holding wire source electrode and be connected to the gate electrode on arbitrary the drive signal line.
The inspection holding wire that is connected on second thin-film transistor that is used to check comprises the first inspection holding wire and the second inspection holding wire.Second thin-film transistor that is used to check can alternately be connected to the first inspection holding wire or the second inspection holding wire.Be connected to the inspection of first on the first film transistor that is used to check holding wire and comprise the third and fourth inspection holding wire.The first film transistor that is used to check can alternately be connected to the 3rd inspection holding wire and the 4th inspection holding wire.
In addition, the inspection holding wire that is connected on second thin-film transistor that is used to check comprises first, second and the 3rd inspection holding wire.Second thin-film transistor that is used to check can be connected to first, second and the 3rd inspection holding wire successively.The inspection holding wire that is connected on the first film transistor that is used to check comprises the 4th and the 5th inspection holding wire.The first film transistor that is used to check alternately is connected to the 4th and the 5th inspection holding wire.
The drive signal line that is connected on second thin-film transistor that is used to check comprises first, second and the 3rd drive signal line.Second thin-film transistor that is used to check can be connected to first, second and the 3rd drive signal line successively.
The detailed structure of thin-film transistor display panel with the thin-film transistor that is used to check is following.
Thin-film transistor display panel comprises the dielectric substrate that has the viewing area and center on the zone; Be formed on the gate line on the dielectric substrate; Be formed on the data drive signal line on the zone that centers on of dielectric substrate; Be formed on the data checks holding wire on the zone that centers on of dielectric substrate; Be formed on the gate insulator on gate line, data drive signal line and the data checks holding wire; Be formed on the semiconductor pattern on the gate insulator, its at least a portion and data drive signal line overlap; Be formed on first and second ohmic contact layers that also expose betwixt on first semiconductor pattern with corresponding a part of first semiconductor pattern of data drive signal line; Be formed on the gate insulator and with gate line and intersect to limit the data wire of viewing area, its at least a portion is formed on second ohmic contact layer; Be formed on first electrode that is used to check on the gate insulator, its at least a portion is formed on first ohmic contact layer; Passivation layer on first electrode that is formed on data wire and is used to check; And the first pontes that is formed on the passivation layer and links to each other with first electrode that is used to check with the data checks holding wire.
Thin-film transistor display panel also comprises the gate drive signal line on the zone that centers on that is formed on dielectric substrate; Be formed on dielectric substrate and check holding wire around the grid on the zone; Be formed on second semiconductor pattern on the gate insulator, its at least a portion and gate drive signal line overlap; Be formed on third and fourth ohmic contact layer that also exposes betwixt on second semiconductor pattern with corresponding a part of second semiconductor pattern of gate drive signal line; Be formed on second electrode that is used to check on the gate insulator, its at least a portion is formed on the 3rd ohmic contact layer; Be formed on the third electrode that is used to check on the gate insulator, its at least a portion is formed on the 4th ohmic contact layer; Be formed on the passivation layer and connect gate line and second coupling part of the third electrode that is used to check; And be formed on the passivation layer and connect grid inspection holding wire and the 3rd coupling part of second electrode that is used to check.First to the 4th ohmic contact layer is respectively formed at data wire and the first whole surface to third electrode that is used to check.
Thin-film transistor display panel can also comprise: be formed on the transmission gate circuit on the zone, its lead-out terminal is connected on the data wire; And be connected to the short-circuiting bar on the input terminal of transmission gate circuit.Or also comprise and be formed on going up around the zone and having a transmission gate circuit that is connected to the output on the data wire of dielectric substrate; What be formed on dielectric substrate goes up and is connected to V around the zone
OffVoltage applies the drive signal line on the terminal; Be formed on the inspection holding wire on the zone that centers on of dielectric substrate; And the thin-film transistor that is used to check, it has the drain electrode that is connected on the data wire, is connected to the source electrode on the inspection holding wire and is connected to the gate electrode on the drive signal line.In addition, the inspection holding wire that is connected on the thin-film transistor that is used to check comprises the first and second inspection holding wires, and the thin-film transistor that preferably is used to check is connected to the first inspection signal and the second inspection signal successively.
Simultaneously, thin-film transistor display panel also comprises first short-circuiting bar that is connected on the odd data line and is connected to second short-circuiting bar on the even data line.
Even do not form this logical circuit, in following LCD, visual inspection passes through V
OnVoltage is applied on the first and second clock signal terminals, Switching Power Supply terminal, the initial terminal of scanning and the drive signal terminal of gate driver circuit; And carry out through common electric voltage is applied on the common electric voltage terminal, this LCD comprises: have the viewing area and around first dielectric substrate in zone; Be formed on many gate lines on first dielectric substrate; Be formed on first dielectric substrate and and intersect to limit many data wires of viewing area with gate line; Be formed on first dielectric substrate and be connected to the pixel thin film transistor on gate line and the data wire; Be formed on the viewing area and be connected to the pixel electrode on the pixel thin film transistor; Be formed on going up around the zone and being connected on the gate line and having the first and second clock signal terminals, Switching Power Supply terminal and scan the gate driver circuit of initial terminal of thin-film transistor; Be formed on the drive signal line on zone and the drive signal terminal that centers on of first dielectric substrate; First dielectric substrate around zone and the inspection holding wire of inspection on the signal terminal; The thin-film transistor that is used to check, it has the drain electrode that is connected on the data wire, is connected to the source electrode on the inspection holding wire and is connected to the gate electrode on the drive signal line; Be formed on the common electric voltage terminal on the zone that centers on of first insulating regions; Second dielectric substrate that relative first dielectric substrate is provided with; Be formed on second dielectric substrate and be connected to the public electrode on the common electric voltage terminal; And be injected into the liquid crystal material between first and second dielectric substrate.
In addition, in following LCD, can pass through V
OnVoltage is applied on the first and second clock signal terminals, Switching Power Supply terminal, the initial terminal of scanning and the drive signal terminal of gate driver circuit; And carry out visual inspection through checking that signal is applied to short-circuiting bar and common electric voltage being applied on the common electric voltage terminal, this LCD comprises: by the viewing area and first dielectric substrate that constitutes around the zone; Be formed on many gate lines on first dielectric substrate; Be formed on first dielectric substrate and and intersect to limit many data wires of viewing area with gate line; Be formed on first dielectric substrate and be connected to the pixel thin film transistor on gate line and the data wire; Be formed on the viewing area and be connected to the pixel electrode on the pixel thin film transistor; Be formed on going up around the zone and being connected to gate line and having the first and second clock signal terminals, Switching Power Supply terminal and scan the gate driver circuit of initial terminal of thin-film transistor; What be formed on first dielectric substrate goes up and is connected to the short-circuiting bar on the data wire around the zone; Be formed on the common electric voltage terminal on the zone that centers on of first insulating regions; Second dielectric substrate with respect to the setting of first dielectric substrate; Be formed on second dielectric substrate and be connected to the public electrode on the common electric voltage terminal; And inject the liquid crystal material between first and second dielectric substrate.
Description of drawings
Fig. 1 is the circuit diagram of the thin-film transistor of first and second embodiment according to the present invention;
Fig. 2 A and 2B are the wiring diagrams according to the thin-film transistor of first embodiment of the invention, are respectively A shown in Figure 1 and the wiring diagram of B;
Fig. 3 A and 3B are respectively the cross-sectional views along line IIIb-IIIb ' intercepting of the line IIIa-IIIa ' of Fig. 2 A and Fig. 2 B;
Fig. 4 A and 4B show the cross-sectional view of manufacturing according to each step of the thin-film transistor of first embodiment of the invention to Fig. 9 A and 9B, and " A " expression is corresponding to the part of Fig. 3 A, and " B " expression is corresponding to the part of Fig. 3 B;
Figure 10 A and 10B are the wiring diagrams according to the thin-film transistor of second embodiment of the invention, are respectively A and B shown in Figure 1;
Figure 11 A and 11B are respectively the cross-sectional views along XIb-XIb ' intercepting of the line XIa-XIa ' of Figure 10 A and Figure 10 B;
Figure 12 is the wiring diagram according to the thin-film transistor of third embodiment of the invention;
Figure 13 is the circuit diagram according to the thin-film transistor of fourth embodiment of the invention;
Figure 14 is the circuit diagram according to the thin-film transistor of fifth embodiment of the invention;
Figure 15 is the circuit diagram according to the thin-film transistor of sixth embodiment of the invention;
Figure 16 is the block diagram of the shift register of gate driver circuit;
Figure 17 is the detailed circuit diagram of one-level shift register;
Figure 18 is the clock figure of the appropriate section of Figure 17;
Figure 19 is the detailed circuit diagram of the logical circuit that is used for VI of Figure 15;
Figure 20 is the circuit diagram according to the thin-film transistor of seventh embodiment of the invention;
Figure 21 is the circuit diagram according to the thin-film transistor of eighth embodiment of the invention;
Figure 22 is the circuit diagram according to the thin-film transistor of nineth embodiment of the invention; And
Figure 23 is the circuit diagram according to the thin-film transistor of tenth embodiment of the invention.
Embodiment
To illustrate and describe thin-film transistor (TFT).
Fig. 1 is the circuit diagram of first and second embodiment according to the present invention.
Many gate line 2 horizontal expansions, and be insulated to be formed on the dielectric substrate 100 with gate line 2 crossing many data wires 3 in the vertical.Be connected to first end that a plurality of grid welding spots 20 on the gate driving IC are connected to gate line 2, and a plurality of data bond pads 30 that are connected on the data-driven IC are connected on second end of data wire 3.Gate line 2 intersects each other to limit pixel region with data wire 3, and one group of pixel region forms the viewing area.A part that is different from the viewing area is defined as around the zone.The grid TFT B that is used to check is connected to three end relative with gate line 2, and the data TFT A that is used to check is connected to four end relative with second end of data wire 3.Grid TFT B also is connected on grid inspection holding wire 22 and the gate drive signal line 24, and data TFT A also is connected on data checks holding wire 21 and the gate drive signal line 25.Gate line 2, grid inspection holding wire 22 link to each other with drain electrode, source electrode and the gate electrode of grid TFT B respectively with gate drive signal line 24.In addition, data wire 3, data checks holding wire 21 and drive signal line 25 link to each other with drain electrode, source electrode and the gate electrode of data TFT A respectively.First solder joint to the, four solder joints 39,41,32 and 40 are connected on the respective ends of grid inspection holding wire 22, gate drive signal line 24, data checks holding wire 21 and data drive signal line 25.Gate drive signal line 24 is connected to grid V through second solder joint 41
OffOn the terminal 52, and data drive signal line 25 is connected to data V
OffOn the terminal 51.That is, all gate electrodes of grid TFT B are connected to grid V
OffOn the terminal 52, and all gate electrodes of data TFT A are connected to data V
OffOn the terminal 51.V
OffTerminal 51 and 52 is through being connected to V via FPC (flexible PCB) in subsequent handling
OffOn the voltage source and as V
OffIt is constant that voltage keeps.Thereby TFT A and B are in off status always, and this is identical with off-state.So, need not carry out diamond cut or laser cutting is separated the lead that is used to check and data wire and gate line.Data checks holding wire 21 is connected respectively on third and fourth solder joint 32 and 40 with data drive signal line 25, and in an identical manner, grid inspection holding wire 22 is connected respectively on first and second solder joints 39 and 41 with gate drive signal line 24.In addition, data checks holding wire 21 and data drive signal line 25 can be extracted out from the marginal portion of the substrate 100 that will be bent.This is for while cutting data inspection holding wire 21 and data drive signal line 25 and along the purpose of line of cut (C) finished edge.
Substrate 200 faces substrate 100 that comprise public electrode, black matrix (black matrix) and colour filter.
To describe this substrate of TFT panel with reference to accompanying drawing in detail.
Fig. 2 A and 2B are the wiring diagram according to the TFT of first embodiment of the invention, and it is respectively the wiring diagram of TFTA and TFT B, and Fig. 3 A and 3B are the cross-sectional views along line IIIb-IIIb ' intercepting of the line IIIa-IIIa ' of Fig. 2 A and Fig. 2 B.
At first, with reference to Fig. 2 A and 3A the data TFT A that is used to check is described.
Be formed on the dielectric substrate 100 to data checks holding wire 21 and 25 horizontal expansions of data drive signal line, and form gate insulator 110 on it.First semiconductor pattern 401 on gate insulator 110 along longitudinal extension.First semiconductor pattern 401 intersects with data drive signal line 25, but does not arrive data checks holding wire 21.On first semiconductor pattern 401, form ohmic contact layer 501 and 502.Ohmic contact layer 501 and 502 exposes between them and data drive signal line 25 corresponding a part of first semiconductor patterns 401.Be used for the data wire 3 of data and the whole surface that source electrode 301 is formed on ohmic contact layer 501 and 502.Passivation layer 120 is formed on data wire 3 and the source electrode 301, and has first contact hole 121 and second contact hole 122 that is used to expose source electrode 301 that is used to expose data checks holding wire 21.Be used for the first pontes 101 that data checks holding wire 21 is connected with source electrode 301 is formed on passivation layer 120.
Below, will grid TFT B be described with reference to Fig. 2 B and 3B.
Be formed on the dielectric substrate 100 grid inspection holding wire 22 and gate drive signal line 24 longitudinal extensions, and gate line 2 horizontal expansions.Gate insulator 110 forms above that.Second semiconductor pattern 402 extends on gate insulator 110 in the horizontal.Second semiconductor pattern 402 intersects with gate drive signal line 24, but does not arrive grid inspection holding wire 22.On second semiconductor pattern 402, form ohmic contact layer 503 and 504.Ohmic contact layer 503 and 504 exposes between them and gate drive signal line 24 corresponding a part of second semiconductor patterns 402.The drain electrode 302 that is used for grid and the source electrode 303 that is used for grid are formed on the whole surface of ohmic contact layer 503 and 504.Passivation layer 120 is formed on drain electrode 302 and the source electrode 303, and has the 3rd contact hole 123 that is used to expose gate line 2, is used to expose the 4th contact hole 124 of drain electrode 302, the 6th contact hole 126 that is used to expose the 5th contact hole 125 of source electrode 303 and is used to expose grid inspection holding wire 22.Second coupling part 102 that is used for gate line 2 is connected with drain electrode 302 is formed on passivation layer 120 with source electrode 303 with the 3rd coupling part 103 that grid inspection holding wire 22 is connected with being used for.
Fig. 4 A and 4B are the cross-sectional view of demonstration manufacturing according to each step of the thin-film transistor of first embodiment of the invention to Fig. 9 A and 9B, and " A " expression is corresponding to the part of Fig. 3 A, and " B " expression is corresponding to the part of Fig. 3 B.
At first; Shown in Fig. 4 A and Fig. 4 B; On insulating barrier 100, deposition gate metal layer and photoetching are to form gate line 2, grid inspection holding wire 22, gate drive signal line 24, data checks holding wire 21 and data drive signal line 25, and they can form bilayer.For example, Cr or Mo alloy-layer that deposition has required physicochemical characteristics, to form ground floor, then, Al or Ag alloy that deposition has less resistive are to form the second layer on ground floor.
Then; Shown in Fig. 5 A and 5B; Through chemical vapour deposition (CVD) will be deposited as successively by gate insulator 110, semiconductor layer 400 and the ohmic contact layer 500 that SiNx processes 1500～5000
thick, 500～2000
thick and 300～600
thick; Then; Deposition data metal layer 300; Then, apply the thick light-sensitive surface of 1～2 μ m above that.Data metal layer can form bilayer.For example, Cr or Mo alloy-layer that deposition has required physicochemical characteristics, to form ground floor, then, Al or Ag alloy that deposition has less resistive are to form the second layer on ground floor.Metal level can be through for example sputtering method deposition.In addition, gate insulator 110 is processed by SiNx, and semiconductor layer 400 is processed by amorphous silicon, and ohmic contact layer is processed by the amorphous silicon with the N type impurity of high-concentration dopant such as P.
Then, through being shone in the light-sensitive surface 900 and develop through mask, light forms light-sensitive surface pattern 911 and 912.Remove light-sensitive surface 900, to stay first 912 and second portion 911, first 912 is formed thinlyyer than second portion 911.First 912 is between the source electrode (not shown) and drain electrode (not shown) of viewing area, between data wire 3 and the source electrode 301 and between drain electrode 302 and the source electrode 303, and second portion 911 is positioned at formation is comprised on the data Layer pattern 3,301,302 and 303 part of source electrode and drain electrode, data wire 3 and source electrode 301, drain electrode 302 and source electrode 303 of viewing area.In this case, the thickness of staying the first 912 in the channel part C changes with the etching condition that the ratio of the thickness of staying the second portion 911 among the data Layer pattern part A is described with the back.For example; The thickness of first 912 is half the less than second portion 911; For example, less than 4000
.
As stated, be useful on, and slit-type or grid type pattern be formed on the mask according to the different several different methods that change the thickness of light-sensitive surface in position, or through utilizing semitransparent thin film to form translucent area above that, with the transmittance amount in the control band A.
In this respect; Preferably; The line width of the pattern of in slit, placing or the interval of pattern, that is, the width of slit is less than utilizing the resolution that is used to make public under the semitransparent thin film situation; And when making mask, can regulate transmissivity with film with different transmissivities or different-thickness.
When light shines on the light-sensitive surface through this mask; Polymerizable molecular in the part that directly is exposed in the light decomposes fully; And the polymerizable molecular in slit pattern or the formed part of semitransparent thin film reduces owing to the rayed amount and not decomposition fully, and the polymer molecule in the light shading film shield portions is difficult to decompose.Then, when light-sensitive surface develops, have only the undecomposed part of polymerizable molecular to be able to stay, and the part that light shines a little is thinner than the complete non-irradiated part of light.In order to obtain this effect, should suitably regulate the time for exposure.
The light-sensitive surface that utilization is processed by material that can remelting (reflow) forms this thin light-sensitive surface.That is, it is with common mask exposure, and this mask has the part of complete transmitted ray and the part of transmitted ray not fully, then, develop and remelting so that a part of light-sensitive surface flow to the not part of residual photosensitive film, so, form thin light-sensitive surface.
Then, light-sensitive surface 900 and lower film thereof, that is, data metal layer 300, ohmic contact layer 500 and semiconductor layer 400 are etched.Data metal layer 300 and lower film thereof are retained among the data Layer pattern part A equally, have only semiconductor layer 400 to stay among the channel part C, and three layers 300,500 and 400 all are removed to expose gate insulator 110 in other parts B.
At first, shown in Fig. 6 A and 6B, the data metal layer 300 that is exposed among other parts B is removed to expose its ohmic contact layer 500.In this step, use dry etching and wet etching.Be etched in that data metal layer 300 is etched and the etched hardly condition of light-sensitive surface pattern 911 and 912 under carry out.Yet, in dry etching, be not easy to find and have only data metal layer 300 to be etched and the not etched condition of light-sensitive surface pattern 911 and 912, therefore, dry etching can carry out under the also etched condition of light-sensitive surface pattern 911 and 912.The thickness of in this case, required is first 912 is than the thicker that in wet etching, obtains, so that do not expose following data metal layer 300.
By this way; Shown in Fig. 6 A and 6B; Data metal layer 300 in channel part C and data Layer pattern part A; That is, only the data wire 3 of viewing area is able to stay with source electrode 301, drain electrode 302 and source electrode 303, and the data metal layer among other parts B is removed to expose its ohmic contact layer 500.Remaining data metal layer 310 has identical form with 320 with data Layer pattern 3,301,302 and 303, and except source electrode with the drain electrode, data wire 3 does not separate with source electrode 303 with source electrode 301 and drain electrode 302.Simultaneously, when using dry etching, photosensitive pattern 911 and 912 etches into thickness to a certain degree.
Then, shown in Fig. 7 A and Fig. 7 B, the ohmic contact layer 500 that in other parts B, exposes and lower semiconductor layer thereof 400 are removed by dry etching with first simultaneously.The etching of ohmic contact layer 500 and semiconductor layer 400 should be carried out under etching simultaneously of light-sensitive surface pattern 911 and 912, ohmic contact layer 500 and semiconductor layer 400 (semiconductor layer and intermediate layer have etching selectivity hardly) quilt and the not etched condition of gate insulator 110.Especially, preferably light-sensitive surface pattern 911 and 912 and the etching ratio of semiconductor pattern 400 much at one.For example, when utilizing SF
6With HCl or SF
6And O
2Mist the time, this two-layer can etching thickness much at one.When light-sensitive surface pattern 911 was identical with 912 and the etching ratio of semiconductor pattern 400, the thickness summation of the thickness of first 912 and semiconductor layer 400 and ohmic contact layer 500 was identical or less than the latter.
By this way; Shown in Fig. 7 A and Fig. 7 B; First 912 among the channel part C is removed exposing remaining data metal layer 310 and 320, and the ohmic contact layer 500 in other parts B is removed to expose its underpart gate insulator 110 with semiconductor layer 400.Simultaneously, the second portion 911 among the data Layer pattern part A also is etched, and it is thinner to become thus.In addition, in this step, accomplish semiconductor pattern 401 and 402.Reference numeral 510 and 520 is represented the bottom ohmic contact layer pattern of remaining data metal layer 310 and 320 respectively.
Then, data metal layer 310 and the light-sensitive surface in 320 surfaces stayed among the channel part C are remaining through the cineration technics removal.
Then, shown in Fig. 8 A and 8B, the data metal layer 310 in channel part C and 320 and its underpart ohmic contact layer pattern 510 and 520 be etched removal.Their etching can only utilize dry etching to realize that remaining data metal layer 310 and 320 can be come etching by wet etching, and ohmic contact layer pattern 510 and 520 can come etching by dry etching.Under former instance; Preferably; Remaining data metal layer 310 and 320 and its underpart ohmic contact layer 510 and 520 under the big condition of its etching selectivity, carry out etching, this be because, if etching selectivity is little; Then be not easy to find etched terminating point, be not easy to regulate the semiconductor pattern 401 stayed in the channel part C and 402 thickness thus.Carrying out one by one under the back situation of dry etching and wet etching; Remaining data metal level 310 and 320 sidepiece come etching by wet etching; Yet ohmic contact layer pattern 510 and 520 almost can not come etching through dry etching, forms step shape thus.As being used for the remaining data metal layer 310 of etching and 320 and the following example of ohmic contact layer pattern 510 and 520 etching gas, there is above-mentioned CF
4With HCl mist or CF
4And O
2Mist.If use CF
4And O
2Mist, can stay semiconductor pattern 401 and 402 with uniform thickness.Aspect this, shown in Figure 16 B, part semiconductor pattern 401 and 402 is removed, thereby and its thickness become thinner, and here, the second portion 911 of light-sensitive surface pattern is also etched to thickness to a certain degree.This is etched under the not etched condition of gate insulator 110 and carries out, and preferably the light-sensitive surface pattern is thicker, makes second portion 911 be etched and does not expose the data Layer pattern 3,301,302 and 303 of bottom.
By this way; The source electrode of viewing area and drain electrode, data wire 3 and source electrode 301, source electrode 303 and drain electrode 302 are isolated from each other, and data Layer pattern 3,301,302 and 303 and the ohmic contact layer pattern 501,502,503 and 504 of its underpart accomplish simultaneously.
At last; The second portion 911 of staying the light-sensitive surface in the data Layer pattern part A is removed; Yet second portion 911 can be after the data metal layer in the channel part C 310 and 320 be etched, and the ohmic contact layer pattern 510 and 520 in its underpart is removed before being removed.
As stated, wet etching and dry etching can use one by one, or can only use dry etching.The latter is simple relatively on technology owing to use a kind of etching, but etching condition is not easy to find.On the contrary, the former the relative latter is complicated, but etching condition relatively easily finds.
Then, passivation layer 120 passes through the inorganic insulation layer of deposition such as SiNx, SiOx etc., or passes through to apply organic insulator, or forms through grown by chemical vapour deposition (CVD) a-Si:C:O film or a-Si:O:F film.At this, a-Si:C:O film or a-Si:O:F film are inorganic insulation layer, and have low-down dielectric constant, and this dielectric constant is in 2 to 4 scope.Under the situation of a-Si:C:O film, SiH (CH
3)
3, SiO
2(CH
3)
4, (SiH)
4O
4(CH
3)
4, Si (C
2H
5O)
4Deng as alkaline source (basicsource), and such as N
2O or O
2Oxidant and flowed with deposition a-Si:C:O such as the mist of Ar or He.In addition, under the situation of a-Si:C:F, O
2And SiH
4, SiF
4Mist flowed with its deposition.At this, CF
4Can be used as auxiliary fluorine source and add.
Then; Shown in Fig. 9 A and 9B; Passivation layer 120 together comes etching by photoetching with gate insulator 110, to form first to the 6th contact hole, is used for exposing respectively data checks holding wire 21, source electrode 301, gate line 2, drain electrode 302 and grid inspection holding wire 22.In this case, also formed the contact hole (not shown) that is used to expose grid welding spot (not shown), data bond pads (not shown) and drain electrode (not shown).
At last; Shown in Fig. 3 A and 3B; Have 4000
to 500
ITO of thickness or IZO is deposited and photoetching, to form first to the 3rd coupling part 101,102 and 103.Equally, in this step, also form the viewing area the pixel electrode (not shown), be connected to the auxiliary grid solder joint (not shown) of grid welding spot and be connected to the auxiliary data solder joint (not shown) on the data bond pads.
Because the Cr etchant can be used as etchant; Therefore in the place that forms first to the 3rd coupling part 101,102 and 103, pixel electrode, auxiliary grid solder joint and auxiliary data solder joint with IZO, prevented that data wire or the gate line metal through contact holes exposing is corroded in the operation that forms these elements.As this Cr etchant, there is HNO
3/ (NH
4)
2Ce (NO
3)
6/ H
2O etc.In addition, preferably IZO is in the temperature deposit of room temperature to 200 ℃, so that make the contact resistance of contact portion reduce to minimum, and the target that is used to form the IZO film comprises In
2O
3And ZnO, and ZnO content is in the 15-20atm% scope.
Simultaneously, preferably nitrogen is used as the gas that adopts in ITO or the preheating before of IZO deposition, and this is to expose on the upside of metal film because of having prevented that metal oxide film is formed on through contact hole 121,122,123,124,125 and 126.
Technology and the structure thereof of the TFT that is formed for checking when four photoetching processes of applications exploiting are made the method for TFT panel have been described.Will be described below method and the structure thereof of utilizing five photoetching process manufacturing TFT panels.
At first its structure will be described.
Figure 10 A and 10B are the wiring diagrams according to the thin-film transistor of second embodiment of the invention, are respectively A and B shown in Figure 1, and Figure 11 A and B are respectively the cross-sectional views along line XIb-XIb ' intercepting of the line XIa-XIa ' of Figure 10 A and Figure 10 B.
At first, will the data TFTA that be used to check be described with reference to Figure 10 A and Figure 11 A.
Be formed on the dielectric substrate 100 to data checks holding wire 21 and 25 horizontal expansions of data drive signal line, and gate insulator 110 is formed on data checks holding wire 21 and the data drive signal line 25.On gate insulator 110, first semiconductor pattern 401 forms island shape on the upside of data drive signal line 25.Ohmic contact layer 501 and 502 is formed on first semiconductor pattern 401, and between them, exposes and data drive signal line 25 corresponding a part of first semiconductors 401.The data wire that is used for data 3 and the source electrode 301 of horizontal expansion are formed on ohmic contact layer 501 and 502.Data wire 3 extends on the ohmic contact layer 501, and source electrode 301 has the pattern identical with other ohmic contact layers 501.Passivation layer 120 is formed on data wire 3 and the source electrode 301, and has first contact hole 121 and second contact hole 122 that is used to expose source electrode 301 that is used to expose data checks holding wire 21.Be used for first contact portion 101 that data checks holding wire 21 is connected with source electrode 301 is formed on passivation layer 120.
Then, will the grid TFT B that be used to check be described with reference to Figure 10 B and Figure 11 B.
Be formed on the dielectric substrate 100, and gate line 2 forms in the horizontal grid inspection holding wire 22 and gate drive signal line 24 longitudinal extensions.Gate insulator 110 is formed on gate line 2, grid inspection holding wire 22 and the gate drive signal line 24.On gate insulator 110, second semiconductor pattern 402 forms the island shape on gate drive signal line 24 upsides.Ohmic contact layer 503 and 504 is formed on second semiconductor pattern 402, and between them, exposes and gate drive signal line 24 corresponding a part of second semiconductor patterns 402.The drain electrode 302 that is used for grid is formed on ohmic contact layer 503 and 504 with source electrode 303.Drain electrode 302 extends on the ohmic contact layer 503, and source electrode 303 extends on another ohmic contact layer 504.Passivation layer 120 is formed on drain electrode 302 and the source electrode 303, and have the 3rd contact hole 123 that is used to expose gate line 2, be used to expose drain electrode 302 the 4th contact hole 124, be used to expose the 5th contact hole 125 of source electrode 303 and be used to expose the 6th contact hole of grid inspection holding wire 22.Second coupling part 102 that is used for gate line 2 is connected with drain electrode 302 is formed on passivation layer 120 with source electrode 303 with the 3rd coupling part 103 that grid inspection holding wire 22 is connected with being used for.
Then, with describing the method for making TFT with structure like this.
At first, deposition and composition gate metal layer on dielectric substrate are to form gate line 2, grid inspection holding wire 22, gate drive signal line 24, data checks holding wire 21 and data drive signal line 25.
Then; The gate insulator of being processed by SiNx 110, the semiconductor layer of being processed by amorphous silicon and these three layers of ohmic contact layer of being processed by the amorphous silicon that mixes deposit successively; Then, etching semiconductor layer and ohmic contact layer have the semiconductor layer 401 and 402 and have and semiconductor layer 401 and 402 identical shaped ohmic contact layer patterns of island shape with formation.
Then, deposition and lithography data metal level, forming the data Layer pattern, it comprises the data wire that intersects with gate line 2, is used for the source electrode 301 of data, the source electrode 303 that is used for the drain electrode 302 of grid and is used for grid.
Then; Be not able to etching by the ohmic contact layer of data Layer pattern blocks; Being divided into, thereby expose the semiconductor layer pattern 401 and 402 in ohmic contact layer pattern 501,502,503 and 504 around the opposite side of gate drive signal line 24 and data drive signal line 25.Can carry out oxygen gas plasma and handle, so that make the exposed surface of semiconductor pattern 401 and 402 stable.
Then, through the inorganic insulation layer of deposition such as SiNx, SiOx etc., or through the deposition organic insulator, or through forming passivation layer 120 by chemical vapor deposition growth a-Si:C:O film or a-Si:O:F film.
Then, through photoetching, composition passivation layer 120 and gate insulator 110 together are to form first to the 6th contact hole 121,122,123,124,125 and 126.
At last, shown in Figure 11 A and 11B, deposition and photoetching ITO film or IZO film are to form first to the 3rd coupling part 101,102 and 103.
Described wherein each grid TFT that is used to check and the data TFT that is used to check and be applied with identical sweep signal and picture signal so that by the TFT panel that drives simultaneously.Yet, can not detect the short circuit that produces between the adjacent wires.Below description is had the structure that can detect the short circuit that produces between the adjacent wires the TFT panel.
Figure 12 is the circuit diagram according to the thin-film transistor display panel of third embodiment of the invention.
Many gate line 2 extends in the horizontal, and is insulated to be formed on the dielectric substrate 100 with gate line 2 crossing many data wires 3 in the vertical.The a plurality of grid welding spots 20 that are connected to gate driving IC are connected on first end of gate line 2, and a plurality of data bond pads 30 that are connected on the data-driven IC are connected on second end of data wire 3.Gate line 2 intersects each other with data wire 3, and limiting a pixel region, and one group of pixel region forms viewing area 17.The first and second grid thin-film transistors that are used to check (below be called TFT) (B
1, B
2) be connected on the 3rd end of first end of relative gate line 2, and the first and second data TFT (A that are used to check
1, A
2) be connected on the 4th end relative with second end of data wire 3.First grid TFT B
1Be connected on first grid inspection holding wire 22a and the gate drive signal line 24, and second grid TFT B
2Be connected on second grid holding wire 22b and the gate driving inspection holding wire 24.In addition, the first data TFT A
1Be connected on the first data checks holding wire 21a and the gate drive signal line 25, and the second data TFT A
2Be connected on the second data checks holding wire 21b and the data drive signal line 25.Gate line 2 is connected to the first and second grid TFT B
1And B
2Drain electrode on, and gate drive signal line 24 is connected to the first and second grid TFT B
1And B
2Source electrode on.The first inspection holding wire 22a is connected to first grid TFT B
1Source electrode on, and second grid inspection holding wire is connected to second grid TFT B
2Source electrode on.In addition, data wire 3 is connected to the first and second data TFT A
1And A
2Drain electrode on, and data drive signal line 25 is connected to the first and second data TFT A
1And A
2Gate electrode on.The first data checks holding wire 21 is connected to the first data TFT A
1Source electrode on, and the second data checks holding wire 21b is connected to the second data TFT A
2Source electrode on.The first and second data checks holding wire 21a and 21b, first and second grids inspection holding wire 22a and 22b, gate drive signal line 24 and data drive signal line 25 are connected to first to the 6th data bond pads 32a that is used to check, 32b, 39a, 39b, a corresponding end of 41 and 40.In this case, data drive signal line 24 is connected to grid V through the 5th solder joint 41
OffOn the terminal 52, and data drive signal line 25 is connected to data V
OffOn the terminal 51, that is, and grid TFT B
1And B
2All gate electrodes be connected to grid V
OffOn the terminal 52, and data TFT A
1And A
2All gate electrodes be connected to data V
OffOn the terminal 51.V
OffTerminal 51 and 52 is through being connected to V through FPC in the step of back
OffOn the voltage source and be held constant at V
OffVoltage.Thereby TFT A is in the off status identical with off-state with B always, so, need not carry out diamond cut or laser cutting is separated the lead that is used to check and data wire and gate line.
Substrate 200 faces substrate 100 that comprise public electrode, black matrix and colour filter.
Simultaneously, because gate line 2 is connected to first grid TFT B successively
1With second grid TFT B
2On, and data wire 3 is connected to the first data TFT A successively
1With the second data TFT A
2On, so can pass through individual drive TFT A
1, A
2, B
1And B
2Driving data lines 3 and gate line 2 successively.So, can detect the short circuit in gate line 2 and the data wire 3.
Figure 13 is the circuit diagram according to the TFT panel of fourth embodiment of the invention.
In the TFT panel according to fourth embodiment of the invention, the data TFT that is used to check is connected to three data checks holding wire 21R, 21G and 21B successively.Signal line 22a and 22b extend, to such an extent as to the solder joint 39a of signal line 22a and 22b and 39b are formed on solder joint 32R, 32G and the 32B position adjacent with data checks holding wire 21R, 21G and 21B.
Because data TFT is connected on three data checks holding wire 21R, 21G and the 21B successively, so can check red, green and blue every kind of color.Through with solder joint 32R, 32G and the 32B position adjacent of data checks holding wire 21R, 21G and 21B on form solder joint 39a and the 39b of signal line 22a and 22b; Be convenient to be connected with the drive unit that is used to check; And this can be applied to the 5th embodiment of first to the 3rd above-mentioned embodiment and back description.
Figure 14 is the circuit diagram according to the TFT panel of fifth embodiment of the invention.
As among the 4th embodiment, in the 5th embodiment, the inspection of each color is connected to three data drive signal line 25R, 25G and 25B through the data TFT that will be used to check and goes up and to become possibility, yet, different among its connection status and the 4th embodiment.Promptly; The source electrode of the data TFT that in the 4th embodiment, is used to check is connected to three data checks holding wire 21R, 21G and 21B successively, but the gate electrode of the data TFT that is used to check is connected to three data drive signal line 25R, 25G and 25B successively.In addition, as among first embodiment, the grid TFT that is used to check is connected to grid inspection holding wire 22 and gate drive signal line 24.In this structure, the short circuit between can the detection data line.
In the 6th following embodiment, formed and to have utilized logical circuit to carry out the TFT panel that is used for LCD of VI.
Figure 15 is the circuit diagram according to the thin-film transistor of sixth embodiment of the invention.Figure 16 is the block diagram of the shift register of gate driver circuit, and Figure 17 is the detailed circuit diagram in the one-level shift register, and Figure 18 is the clock figure (timing diagram) of the appropriate section of Figure 17, and Figure 19 is the detailed circuit diagram of the logical circuit that is used for VI of Figure 15.
As an example, below use description to the TFT panel of LCD.
With reference to Figure 15; On TFT panel 10, form viewing area 150, this zone comprises a plurality of pixels, gate driver circuit 170, is used for the logical circuit 180 of VI, as the holding wire 111 and a plurality of signal solder joint V that comprise a plurality of transistor ST2 and the transmission gate portion 120TG of ST3, a plurality of VI of being used for of the part of data drive circuit
On, V
Off, VCK1, VCK2, VST, CON1, CON2, CON3, TG1, TG2 and Vcom.These elements together form in the process that forms TFT and pixel electrode.
Viewing area 150 comprises the side of being expert at upwardly extending m bar data wire DL1～DLm and the side upwardly extending n bar gate lines G L1～GLn that is being listed as.
Switching transistor ST1 is formed on the intersection point of data wire and gate line.The drain electrode of switching transistor ST1 is connected on the data wire Dli, and its grid is connected on the gate lines G li.The source electrode of switching transistor ST1 is connected on the transparent pixels electrode PE.In the transparent common electrode that liquid crystal LC forms between transparent pixels electrode PE and colour filter (not shown).
The light quantity of transmission is through controlling the arrangement of liquid crystal and regulate according to being applied to voltage on transparent pixels electrode PE and the transparent common electrode CE, thereby demonstrates the gray scale of each pixel.
To describe gate driver circuit 170 shown in Figure 15 in detail with reference to Figure 16 to 18.
Gate driver circuit 170 comprises shift register.Shift register 174 shown in Figure 16 has the utmost point and joins a plurality of grades of SRC1～SRC193 that connect.That is corresponding lead-out terminal OUT, at different levels are connected on the input terminal IN of next stage.These grades comprise having the number of stages consistent with gate line quantity the empty level of level SRC1～SRC192 and (dummy stage) SRC193 of (being 192 in the present embodiment) constitutes.Every grade has an input terminal IN, a lead-out terminal OUT, a control terminal CT, a clock signal input terminal CK, one first power supply voltage terminal VSS and a second source voltage terminal VDD.In this case, the input terminal IN of first order SRC1 is connected on the VST solder joint, and the first power supply voltage terminal VSS is connected to V
OffSolder joint, and second source voltage terminal VDD is connected to V
OnSolder joint.In addition, the sub-CK of clock signal input terminal of level SRC1～SRC193 is connected to VCK1 or VCK2.
Initial signal ST shown in Figure 180 is input on the input terminal of the first order.At this, initial signal is the pulse signal synchronous with vertical synchronizing signal.
Output signal OUT1～OUT192 at different levels are connected on the relevant gate line.Odd level SRC1 and SRC3 are provided with the first clock signal C K, and even level SRC2 and SRC4 are provided with second clock signal CKB.The first clock signal C K and second clock signal CKB are inverting each other.
The control terminal of every grade (for example SRC1) is provided for the output signal (for example OUT2) of next stage (for example SRC2) as control signal.That is, be input to of the work period delay of the control signal of control terminal CT by itself.
Therefore, (active interval) (high attitude (high state)) produces successively because output signal at different levels is to gain merit at interval, so select the horizontal line corresponding to the meritorious interval of each output signal.
With reference to Figure 17, with the exemplary configurations of the circuit of describing SRC1～SRC193 at different levels in detail.
Shown in figure 17, every grade shift register 174 comprise drawing upwardly device 181, pull device 182, on draw drive unit 184, drop-down drive unit 186, anti-floating device 188 and anti-conducting device 190.
Drawing upwardly device 181 comprises and draws nmos pass transistor NT1 that it has the drain electrode that is connected to the sub-CK of clock signal input terminal, the source electrode that is connected to the grid of first node N1 and is connected to lead-out terminal OUT.
Pull device 182 comprises pull-down NMOS transistor NT2, and it has the drain electrode that is connected to lead-out terminal OUT, the source electrode that is connected to the grid of Section Point N2 and is connected to the first supply voltage VSS.
On draw drive unit 184 to comprise capacitor C and nmos pass transistor NT3～NT5.Capacitor is connected between first node N1 and the lead-out terminal OUT.Transistor NT3 has and is connected to the drain and gate on the input terminal IN jointly and is connected to the source electrode on the first node N1.Transistor NT4 has the drain electrode that is connected on the first node N1, is connected to the grid on the Section Point N2 and is connected to the source electrode on the first supply voltage VSS.Transistor NT5 has the drain electrode that is connected on the first node N1, is connected to the grid on the control terminal CT and is connected to the source electrode on the first supply voltage VSS.
Drop-down drive unit 186 comprises two nmos pass transistor NT6 and NT7.Transistor NT6 has the drain electrode that is connected on the second source voltage VDD, is connected to the grid on the control terminal CT and is connected to the source electrode on the Section Point N2.Transistor NT7 has the drain electrode that is connected on the Section Point N2, is connected to the grid on the input terminal IN and is connected to the source electrode on the first supply voltage VSS.
Anti-floating device 188 comprises nmos pass transistor NT8, and it has and is connected to the drain and gate on the second source voltage VDD jointly and is connected to the source electrode on the Section Point N2.It is relatively little that transistor NT18 is configured to size, for example is 1/20th of transistor NT7.
Anti-conducting device 190 comprises nmos pass transistor NT9, and it has the drain electrode that is connected on the Section Point N2, is connected to the grid on the lead-out terminal OUT and is connected to the source electrode on the first supply voltage VSS.The size of transistor NT9 is approximately 1: 2 with respect to transistor NT7.
Shown in figure 18; When the first and second clock signal C K and CKB and scanning initial signal ST are applied to 170 last times of shift register; The front of first order SRC1 responding scanning initial signal ST; And the time that the high level interval delay of first clock signal is specific (Tdr1) produces the output signal to output then.
The meritorious interval of scanning initial signal ST has the leading phase (leading phase) in about 1/4 cycle at interval with respect to high level.The meritorious interval of initial signal ST is divided into from the start-up time that the front or the rising edge of pulse begin (set time) Ts1 and the retention time Ts2 that begins from the back or the trailing edge of pulse.
So the front of output signal OUT1 has the front that about 2～4 μ s postpone, that is, and the rising edge of the starting point of self-hold-time Ts2.That is to say that the meritorious interval of the first clock signal C K or high level are postponed Tdr1 at interval, in lead-out terminal OUT, to produce.
This delay characteristic former because on draw the capacitor C of drive unit 184 to begin to charge from the cut-off state of transistor NT4 via transistor NT3 at the place, front; Then; After the charging voltage of capacitor C is charged to the threshold voltage of the gate-to-source that surpasses the NT1 that pulls up transistor; The conducting that pulls up transistor, and the high level of the first clock signal C K begins to produce at lead-out terminal at interval.
When the high level in the clock signal of lead-out terminal began to produce at interval, this output voltage was booted (bootstrap) in capacitor C, so that the grid voltage that pulls up transistor is increased to above conducting voltage VDD.So the NT1 that pulls up transistor of nmos pass transistor remains on fully conducting state.
On the other hand, in drop-down drive unit 186, owing to transistor NT7 ends under the cut-off state of transistor NT6, so the voltage of Section Point N2 is reduced to the first supply voltage VSS.In this case; The transistor NT8 of anti-floating device 188 remains conducting state; Yet, because the transistor NT7 of conducting is bigger approximately 20 times than transistor NT8, so Section Point N2 is reduced to the first supply voltage VSS under the state of second source voltage VDD.Thus, pull-down transistor NT2 becomes cut-off state from conducting state.
When conducting voltage (VON=VDD) produces on lead-out terminal OUT, prevent the transistor NT9 conducting of conducting device 190, and increase about 50% with the efficient of first supply voltage VSS driving Section Point N2.Therefore, the drain electrode of pull-down transistor-source electrode capacitor parasitics can prevent that the voltage of Section Point N2 from increasing in rising-displacement place of output signal.So, can prevent misoperation at the rising-displacement place conducting pull-down transistor of output signal.
The output signal OUT1 of lead-out terminal OUT was produced by the work period of the first clock signal C K.
When the output signal voltage of lead-out terminal OUT is in cut-ff voltage (VOFF=VSS) state; Transistor NT9 ends; Only second source voltage VDD being provided on the Section Point through transistor NT8, and the voltage of Section Point N2 begins to rise to second source voltage VDD from the first supply voltage VSS thus.When the voltage of Section Point began to rise, transistor NT4 began conducting, and thus, the charging voltage of capacitor begins the discharge through transistor NT4, so the NT1 that pulls up transistor also begins to end.
After this, increase to conducting voltage owing to provide to the output signal of the next stage of control terminal CT, so this causes transistor NT5 and NT6 conducting.Therefore, the voltage of Section Point N2 increases to the second source voltage VDD that is provided by transistor NT6 and NT8 fast, and the voltage of first node N1 drops to the first supply voltage VSS fast through transistor NT4 and NT5.
So the NT1 that pulls up transistor ends, and pull-down transistor NT2 conducting, thereby lead-out terminal OUT is from conducting voltage V
OnBe reduced to the cut-ff voltage V of first supply voltage
Off
Be in low level and "off" transistor NT6 even offer the output signal of the next stage of control terminal CT; But Section Point N2 remains the bias state of second source voltage through transistor, and first node N1 remains the bias state of the first supply voltage VSS through the transistor NT4 that keeps conducting state.Therefore, even the threshold voltage of transistor NT2 and NT4 is owing to long-term the use increases, also can steady operation, and can not remain the misoperation that "off" transistor NT2 appears in second source voltage VDD owing to the voltage of Section Point N2.
Then, will describe the logical circuit that is used for VI 180 shown in Figure 15 in detail with reference to Figure 19.
Logical circuit 180 comprises two row NOR (or non-) doors, and first input end of the NOR gate NOR1 in first row correspondingly is connected on the lead-out terminal of SRC1～SRC192 at different levels, and its second input terminal is connected on the CON1 solder joint entirely.NOR gate NOR2 among second row and first input end of NOR3 correspondingly are connected on the lead-out terminal of NOR gate NOR1, and its second input terminal is connected on CON2 solder joint or the CON3 solder joint.In this embodiment of the present invention, the NOR gate NOR2 in the odd column is connected on the CON2 solder joint, and the NOR gate NOR3 in the even column is connected on the CON3 solder joint.
When carrying out visual inspection (VI), there be not the level SRC1～SRC2 input of signal from gate driver circuit 170.Therefore, the signal of first input end always is in pass (0) state.In this case, when opening (1) signal and be input on second input terminal, produce at the lead-out terminal place of NOR1 and to close (0) signal via the CON1 solder joint.That is to say, close (0) signal and be input on first input end of NOR2 and NOR3.Therefore, depend on the signal that is input on its second input terminal, have only odd column or have only even column to be switched on (1), perhaps their all conductings (1).When closing (0) signal when being input on second input terminal of NOR2 through the CON2 solder joint, produce at the gate line place of odd column and open (1) signal, and when opening (1) signal and be input to it on via the CON2 solder joint, generation pass, gate line place (0) signal in odd column.When closing (0) signal when being input on second input terminal of NOR3 via the CON3 solder joint, produce at the gate line place of even column and open (1) signal, and when opening (1) signal it is gone up via the input of CON3 solder joint, generation pass, gate line place (0) signal in even column.
When after during the driving liquid crystal device, close (0) signal and be applied to all CON1, CON2 and CON3 solder joint.In this mode, owing to be applied to the signal deciding that the signal on the gate line is exported according to the SRC1 at different levels～SRC192 from gate driver circuit 170, the logical circuit 180 that therefore is used for VI is equal to and does not exist.
Above-mentioned logical expressions are in table 1.
Table 1
| CON1 | CON2 | CON3 | |
| The odd number lead is opened | 1 | 0 | 1 |
| The even number lead is opened | 1 | 1 | 0 |
| All leads are opened | 1 | 0 | 0 |
| All leads close | 1 | 1 | 1 |
| When panel is worked | 0 | 0 | 0 |
Now, use description to the lead-in wire of the data wire of VI.
Shown in figure 15, the transmission gate portion 120 a part of as drive circuit is formed on the TFT panel, and the input terminal of transmission gate all is connected on the short-circuiting bar 111.The source electrode of each TFT ST2 and ST3 is connected on the short-circuiting bar 111, and as the input terminal of transmission gate, its drain electrode is connected on each data wire DL1 and the DL2, and its gate electrode is connected among two transmission gate terminal TG1 and the TG2.In Figure 15, odd number TFT ST2 is connected on the TG1, and even number TFT ST3 is connected on the TG2.
When in this structure, carrying out VI, picture signal is input on the short-circuiting bar 111 via the Vs terminal.The TFT ST2 of transmission gate portion 120 and ST3 can be according to being input to signal and the conducting on TG1 and the TG2 terminal or ending, picture signal is provided on odd data line or the even data line, perhaps on all data wires.
Sixth embodiment of the invention has realized the 2G that can utilize the logical circuit part 180 that is used for VI to drive odd gates line and even number gate line distinctively and can utilize short-circuiting bar 111 and transmission gate portion 120 to drive the 2D of odd data line and even data line distinctively.Thereby, can detect the short circuit between adjacent data line DL1～DLn and the adjacent gate polar curve GL1～GLn.
In Figure 15, A representes the position of installation data drive integrated circult (IC), and B representes the line of laser radiation after accomplishing VI, short-circuiting bar 111 and transmission gate portion were left in 120 minutes.
When VI carries out under aforesaid structure, from the signal indication of each solder joint input table 2.
Table 2
| Sequence number | The solder joint title | Be applied to the voltage on the solder joint |
| 1 | V on | V on |
| 2 | V off | V off |
| 3 | Vcom | Vcom |
| 4 | CON1 | V on |
| 5 | CON2 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 6 | CON3 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 7 | Vs | Picture signal |
| 8 | TG1 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 9 | TG2 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
The seventh embodiment of the present invention will be described.
Figure 20 is the circuit diagram according to the TFT of seventh embodiment of the invention.
The seventh embodiment of the present invention is identical with the 6th embodiment, is two except not having transmission gate portion and short-circuiting bar.In the 7th embodiment, the odd data line is connected on first short-circuiting bar 112, and the even data line is connected on second short-circuiting bar 113.First short-circuiting bar 112 and second short-circuiting bar, 114 each bar all are connected on Vs1 and the Vs2 terminal to form the 2D structure.The seventh embodiment of the present invention will be in only integrated 2G, 2D and the VI structure of realizing under the situation of gate driver circuit on the TFT panel.
When structure down carries out VI as stated, the signal indication of importing from each solder joint is table 3.
Table 3
| Sequence number | The solder joint title | Be applied to the voltage on the solder joint |
| 1 | V on | V on |
| 2 | V off | V off |
| 3 | Vcom | Vcom |
| 4 | CON1 | V on |
| 5 | CON2 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 6 | CON3 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 7 | Vs1 | Picture signal 1 |
| 8 | Vs2 | Picture signal 2 |
Figure 21 is the circuit diagram according to the TFT panel of eighth embodiment of the invention.
The eighth embodiment of the present invention is identical with the 6th embodiment, and difference is there is not short-circuiting bar, and the substitute is and formed the first and second data TFTA that are used to check
1And A
2
Shown in figure 21, the first data TFT A
1Be connected on the first data checks holding wire 21a and the data drive signal line 25, and the second data TFT A
2Be connected on the second data checks holding wire 21b and the data drive signal line 25.In addition, data wire DL1～DLn is connected to the first and second data TFT A
1And A
2Drain electrode on, and data drive signal line 25 is connected to the first and second data TFT A
1And A
2Gate electrode on.The first data checks holding wire 21a is connected to the first data TFT A
1Source electrode on, and the second data checks holding wire 21b is connected to the second data TFT A
2Source electrode on.First to the 3rd solder joint 32a, the 32b and 40 that is used to check is connected to an end of every first and second inspection data wire 21a and 21b and data drive signal line 25.In this case, data drive signal line 25 is connected to data V
OffOn the terminal 51.That is to say data TFT A
1And A
2Gate electrode all be connected to data V
OffOn the terminal 51.V
OffTerminal 51 is through being connected to V via the FPC in the modularization technology of back
OffOn the voltage supply circuit and keep V always
OffVoltage.Thereby, data TFT A
1And A
2Be in identical off-state, this is because it remains on off status when liquid crystal display-driving always.So, need not carry out diamond cut or laser cutting the lead that is used to check and data wire and gate line are separated.
Simultaneously, because data wire DL1～DLn is connected to the first data TFT A successively
1With the second data TFT A
2On, so can pass through individual drive TFT A
1And A
2Come driving data lines DL1～DLn successively.So, can detect the short circuit among adjacent data line DL1～DLn.
When in aforesaid this structure, carrying out VI, from the signal indication of each solder joint input table 4.
Table 4
| Sequence number | The solder joint title | Be applied to the voltage on the solder joint |
| 1 | V on | V on |
| 2 | V off | V off |
| 3 | Vcom | Vcom |
| 4 | CON1 | V on |
| 5 | CON2 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 6 | CON3 | V onOr V off(according to wanting driven odd gates line or even number gate line to change) |
| 7 | 40 | V on |
| 8 | 32a | Picture signal 1 |
| 9 | 32b | Picture signal 2 |
Simultaneously, the structure of omitting transmission gate circuit also can realize in Figure 21.
Figure 22 is the circuit diagram according to the TFT panel of nineth embodiment of the invention.
Identical according to the TFT panel of nineth embodiment of the invention and the 8th embodiment is except omitting logical circuit.
Can to each solder joint of the TFT with this structure, carry out 1G and 2D VI through applying voltage as shown in table 5.That is to say, can be through making all gate lines G L1～GLn be in out state and carrying out VI through conducting successively or by data wire DL1～DLn.
Table 5
| Sequence number | The solder joint title | Be applied to the voltage on the solder joint |
| 1 | V on | V on |
| 2 | V off | V on |
| 3 | Vcom | Vcom |
| 4 | VST | V on |
| 5 | VCK1 | V on |
| 6 | VCK2 | V on |
| 7 | 40 | V on |
| 8 | 32a | Picture signal 1 |
| 9 | 32b | Picture signal 2 |
Equally, similar with the 8th embodiment in TFT panel according to nineth embodiment of the invention, V
OffTerminal 51 is through being connected to V via the FPC in the modularization technology of back
OffOn the voltage supply circuit and keep V always
OffVoltage.Thereby, data TFT A
1And A
2Be in identical off-state, this is always to remain under the off status owing to when liquid crystal display-driving, rising.So, need not carry out diamond cut or laser cutting the lead that is used to check and data wire and gate line are separated.
Figure 23 is the circuit diagram according to the TFT panel of tenth embodiment of the invention.
Identical according to the TFT panel of tenth embodiment of the invention and the 7th embodiment is except having omitted the logical circuit part that is used for VI.
Can be through carrying out 1G and 2D VI on each solder joint that voltage as shown in table 6 is applied to TFT with this structure.That is to say, can be in out state, and carry out VI through conducting successively or by data wire DL1～DLn through making all gate lines G L1～GLn.
Tenth embodiment of the invention need be carried out laser cutting or diamond cut, after carrying out VI, short-circuiting bar 112 and 113 is separated with data wire.
The drive IC that the foregoing description can directly apply to any kind on the TFT panel forms part, like multi-crystal TFT panel or amorphous silicon drive IC panel.
Table 6
| Sequence number | The solder joint title | Be applied to the voltage on the solder joint |
| 1 | V on | V on |
| 2 | V off | V on |
| 3 | Vcom | Vcom |
| 4 | VST | V on |
| 5 | VCK1 | V on |
| 6 | VCK2 | V on |
| 7 | Vs1 | Picture signal 1 |
| 8 | Vs2 | Picture signal 2 |
Though the present invention explains with reference to exemplary embodiment that it is not limited to top disclosed embodiment.Scope of the present invention comprises various modifications and the equivalent thereof that is covered by in the appended claims.
As stated, be connected to data wire and gate line via the TFT that is used to check through the lead that will be used to check, and after inspection, through with V
OffVoltage is applied to the TFT that is used to check, inspection is able to carry out, and this TFT remains and cuts off identical state, and does not need independent cutting process.Therefore, can remove the additional process and the solution of cutting the lead that is used to check is corroded by the lead that cutting causes.
Simultaneously, according to the present invention, can be at the integrated visual inspection that carries out 2G and 2D or 1G and 2D in the TFT panel of gate driving IC.
Claims (15)
1. thin-film transistor display panel comprises:
Have the viewing area and center on regional dielectric substrate;
Be formed on first holding wire on the dielectric substrate;
Be formed on the dielectric substrate and with insulation of first holding wire and the secondary signal line with the qualification viewing area of intersecting;
Be formed on many drive signal lines on the zone that center on of dielectric substrate;
Be formed on many inspection holding wires on the zone that center on of dielectric substrate;
The first film transistor that is used to check, it has the drain electrode that is connected on first holding wire, be connected to arbitrary on the inspection holding wire source electrode and be connected to the gate electrode on arbitrary the drive signal line; And
Second thin-film transistor that is used to check, it has the drain electrode that is connected on the secondary signal line, be connected to arbitrary on the inspection holding wire source electrode and be connected to the gate electrode on arbitrary the drive signal line,
Wherein said many drive signal lines are connected to cut-ff voltage and apply terminal and apply solder joint with the drive signal that is used to check.
2. thin-film transistor display panel as claimed in claim 1; Wherein, The inspection holding wire that is connected on second thin-film transistor that is used to check comprises the first inspection holding wire and the second inspection holding wire, and second thin-film transistor that is used to check alternately is connected to the first inspection holding wire and the second inspection holding wire.
3. thin-film transistor display panel as claimed in claim 2; Wherein, Be connected to the inspection of first on the first film transistor that is used to check holding wire and comprise the third and fourth inspection holding wire, and the first film transistor that is used to check alternately is connected to the 3rd inspection holding wire and the 4th inspection holding wire.
4. thin-film transistor display panel as claimed in claim 1; Wherein, The inspection holding wire that is connected on second thin-film transistor that is used to check comprises first, second and the 3rd inspection holding wire, and second thin-film transistor that is used to check is connected to first, second and the 3rd inspection holding wire successively.
5. thin-film transistor display panel as claimed in claim 4; Wherein, The inspection holding wire that is connected on the first film transistor that is used to check comprises the 4th and the 5th inspection holding wire, and the first film transistor that is used to check alternately is connected to the 4th and the 5th inspection holding wire.
6. thin-film transistor display panel as claimed in claim 1; Wherein, The drive signal line that is connected on second thin-film transistor that is used to check comprises first, second and the 3rd drive signal line, and second thin-film transistor that is used to check is connected to first, second and the 3rd drive signal line successively.
7. thin-film transistor display panel as claimed in claim 1, wherein said first holding wire is a gate line, and said secondary signal line is data wire,
The said drive signal line that is connected to said second thin-film transistor is the data drive signal line, and the said inspection holding wire that is connected to said second thin-film transistor is the data checks holding wire;
Wherein said second thin-film transistor comprises:
Be formed on the gate insulator on data drive signal line and the data checks holding wire;
Be formed on first semiconductor pattern on the gate insulator, itself and data drive signal line intersect, but do not arrive the data checks holding wire;
Be formed on first and second ohmic contact layers that also expose betwixt on first semiconductor pattern with corresponding a part of first semiconductor pattern of data drive signal line; Wherein said data wire is formed on the gate insulator and is positioned on the whole surface of second ohmic contact layer, and wherein the source electrode of second thin-film transistor is formed on the gate insulator and is positioned on the whole surface of first ohmic contact layer;
Be formed on the passivation layer on the source electrode of the data wire and second thin-film transistor; And
Be formed on the passivation layer and the first pontes that links to each other with the source electrode of the data checks holding wire and second thin-film transistor.
8. thin-film transistor display panel as claimed in claim 7, wherein:
Being connected to the transistorized drive signal line of the first film is the gate drive signal line, and being connected to the transistorized inspection holding wire of the first film is grid inspection holding wire;
Said the first film transistor comprises:
Be formed on second semiconductor pattern on the gate insulator, itself and gate drive signal line intersect but do not arrive grid inspection holding wire;
Be formed on third and fourth ohmic contact layer that also exposes betwixt on second semiconductor pattern with corresponding a part of second semiconductor pattern of gate drive signal line; Wherein the transistorized source electrode of the first film is formed on the gate insulator and is positioned on the whole surface of the 3rd ohmic contact layer, and wherein the first film transistor drain electrode is formed on the gate insulator and is positioned on the whole surface of the 4th ohmic contact layer;
Be formed on the passivation layer and connect gate line and second coupling part of the first film transistor drain electrode; And
Be formed on the passivation layer and connect the 3rd coupling part of grid inspection holding wire and the transistorized source electrode of the first film.
9. thin-film transistor display panel as claimed in claim 8; Wherein, first to the 4th ohmic contact layer is respectively formed on the whole surface of the transistorized source electrode of source electrode, data wire, the first film and the first film transistor drain electrode of second thin-film transistor.
10. thin-film transistor display panel as claimed in claim 8; Wherein said cut-ff voltage applies terminal and comprises that first cut-ff voltage applies terminal and second cut-ff voltage applies terminal; And the drive signal that is used to check applies solder joint and comprises that first drive signal that is used to check applies solder joint and applies solder joint with second drive signal that is used to check
Wherein said data drive signal line is connected to first cut-ff voltage and applies terminal and apply solder joint with first drive signal that is used to check, and said gate drive signal line is connected to second cut-ff voltage and applies terminal and apply solder joint with second drive signal that is used to check.
11. a method of making thin-film transistor display panel comprises:
Form the first step of gate line, data checks holding wire and data drive signal line;
Second step of deposition gate insulator, semiconductor layer, ohmic contact layer and conductive layer;
Utilize photoetching composition conductive layer, ohmic contact layer and a semiconductor layer to form data wire, first electrode that is used to check, the ohmic contact layer pattern under first electrode that is used to check and data wire, the third step of semiconductor layer pattern under the ohmic contact layer pattern;
On data wire and first electrode that is used to check, form the 4th step of passivation layer; And
Form the 5th step that connects the data checks holding wire and the first pontes of first electrode that is used to check.
12. method as claimed in claim 11; Wherein, Grid inspection holding wire and gate drive signal line form in first step; Second and the third electrode that are used for checking form at third step, connect second coupling part of gate line and the third electrode that is used for checking and be connected grid to check that holding wire and the 3rd coupling part of second electrode that is used to check form in the 5th step.
13. method as claimed in claim 12 also is included in the third step light-sensitive surface pattern that forms as etching mask, wherein, the light-sensitive surface pattern has first, than thick second portion of first and the third part thinner than first.
14. method as claimed in claim 13; Wherein, The first of light-sensitive surface pattern is between first electrode that is used to check and the data wire and between second electrode that is used to check and the third electrode that is used to check, and its second portion be positioned at data wire be used to check first to third electrode.
15. a method of in LCD, carrying out visual inspection, this LCD comprises: have the viewing area and center on the first regional dielectric substrate; Be formed on many gate lines on first dielectric substrate; Be formed on first dielectric substrate and and intersect to limit many data wires of viewing area with gate line; Be formed on first dielectric substrate and be connected to the pixel thin film transistor on gate line and the data wire; Be formed on the viewing area and be connected to the pixel electrode on the pixel thin film transistor; Be formed on going up around the zone and being connected on the gate line and having the first and second clock signal terminals, Switching Power Supply terminal and scan the gate driver circuit of initial terminal of thin-film transistor; Be formed on the drive signal line on zone and the drive signal terminal that centers on of first dielectric substrate; First dielectric substrate around zone and the inspection holding wire of inspection on the signal terminal; The thin-film transistor that is used to check, it has the drain electrode that is connected on the data wire, is connected to the source electrode on the inspection holding wire and is connected to the gate electrode on the drive signal line; Be formed on the common electric voltage terminal on the zone that centers on of first insulating regions; Second dielectric substrate that relative first dielectric substrate is provided with; Be formed on second dielectric substrate and be connected to the public electrode on the common electric voltage terminal; And be injected into the liquid crystal material between first and second dielectric substrate,
The method of wherein, carrying out visual inspection comprises V
OnVoltage is applied on the first and second clock signal terminals, Switching Power Supply terminal, the initial terminal of scanning and the drive signal terminal of gate driver circuit, and common electric voltage is applied on the common electric voltage terminal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010062619A KR100816336B1 (en) | 2001-10-11 | 2001-10-11 | a thin film transistor array panel and a method of the same |
| KR62619/01 | 2001-10-11 | ||
| KR81049/01 | 2001-12-19 | ||
| KR1020010081049A KR100864487B1 (en) | 2001-12-19 | 2001-12-19 | a thin film transistor array panel having a means for visual inspection and a method of visual test |
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| CNB02122790XA Division CN100414405C (en) | 2001-10-11 | 2002-06-13 | Film transistor array panel with visual checking device and its checking method |
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| US5563427A (en) * | 1993-02-10 | 1996-10-08 | Seiko Epson Corporation | Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels |
| JP2653099B2 (en) * | 1988-05-17 | 1997-09-10 | セイコーエプソン株式会社 | Active matrix panel, projection display and viewfinder |
| CN1287650A (en) * | 1998-10-16 | 2001-03-14 | 精工爱普生株式会社 | Substrate for electrooptic device, active matrix substrate, and method of testing substrate for electrooptic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10260391A (en) * | 1997-03-19 | 1998-09-29 | Fujitsu Ltd | Liquid crystal display device with inspecting circuit |
| KR100239749B1 (en) * | 1997-04-11 | 2000-01-15 | 윤종용 | Tft fabrication method structure of lcd, test apparatus and method for gross test |
| KR100628440B1 (en) * | 1999-05-26 | 2006-09-27 | 삼성전자주식회사 | Liquid crystal display |
| JP2001235725A (en) * | 2000-02-24 | 2001-08-31 | Victor Co Of Japan Ltd | Liquid crystal display device |
-
2001
- 2001-10-11 KR KR1020010062619A patent/KR100816336B1/en active IP Right Grant
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2002
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2653099B2 (en) * | 1988-05-17 | 1997-09-10 | セイコーエプソン株式会社 | Active matrix panel, projection display and viewfinder |
| US5563427A (en) * | 1993-02-10 | 1996-10-08 | Seiko Epson Corporation | Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels |
| CN1287650A (en) * | 1998-10-16 | 2001-03-14 | 精工爱普生株式会社 | Substrate for electrooptic device, active matrix substrate, and method of testing substrate for electrooptic device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20030030470A (en) | 2003-04-18 |
| CN101221958A (en) | 2008-07-16 |
| KR100816336B1 (en) | 2008-03-24 |
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