CN101237546A - High-speed audio and video magnitude storage method and device for vehicular environment - Google Patents
High-speed audio and video magnitude storage method and device for vehicular environment Download PDFInfo
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- CN101237546A CN101237546A CNA2007101355913A CN200710135591A CN101237546A CN 101237546 A CN101237546 A CN 101237546A CN A2007101355913 A CNA2007101355913 A CN A2007101355913A CN 200710135591 A CN200710135591 A CN 200710135591A CN 101237546 A CN101237546 A CN 101237546A
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Abstract
A high-speed audio-video mass storing method used in vehicular environment comprises the following steps: through adopting a plurality of parallel-operation intelligent nodes to increase bandwidth, data is stored in a high-speed volatile memory unit at first; then, a plurality of intelligent nodes respectively writes the data block in the high-speed volatile memory unit belonging to each intelligent node in the low-speed nonvolatile memory unit controlled by a corresponding intelligent node. A high-speed audio-video mass storing device, which is used in vehicular environment and is designed according to the method, is provided with a main processor circuit, a volatile cache circuit, an embedded intelligent node circuit and a low-speed nonvolatile memory circuit, wherein the volatile cache circuit which adopts a duplex interface is respectively connected with the main processor circuit and the embedded intelligent node circuit; the main processor circuit exchanges data and commands with the embedded intelligent node circuit through the volatile cache circuit; moreover, the embedded intelligent node circuit reads out data from the volatile cache circuit and writes the data in the low-speed nonvolatile memory circuit.
Description
Technical field
The present invention relates to magnanimity non-volatile memory at a high speed, particularly a kind of high-speed audio and video mass memory method and device thereof that is applied to vehicle environment.
Background technology
Mass storage generally adopts hard disk, because the technology of hard disk, miniaturization and antidetonation etc. is difficult to accomplish that especially the damage probability of hard disk is very high under vibration environment; Because the storage medium work characteristics of hard disk whenever writes data and all will wipe, wait for simultaneously, write, wait for four processes, can't write in real time each piece memory block.And under occasion, cube little as vehicle-mounted audio frequency and video record, and low-power consumption and very strong shock resistance and reliability, under the occasion of audio frequency and video record simultaneously, the record flow of data is big especially, and general non-volatile memory medium is difficult to accomplish so big bandwidth.Therefore, need a kind of technology, overcome above difficulty, realize that audio/video flow is stored continuously under the vehicle environment.
Summary of the invention
The objective of the invention is to address the above problem, a kind of high-speed audio and video mass memory method and device thereof that is applied to vehicle environment is provided, realize by following technical proposals: a kind of high-speed audio and video mass memory method that is applied to vehicle environment, it is characterized in that: take a plurality of intelligent node parallel work-flows to increase the mode of bandwidth, earlier metadata cache is easily being lost at a high speed in the memory cell, will easily lose in the memory cell at a high speed respectively by a plurality of intelligent nodes then in one's own data block write in the low speed nonvolatile memory cell of own this intelligent node control.
When main processor unit needed storage, the number that data block of main processor unit write-once storage device, the size of data block equal parallel node in the system multiply by the size of a sector of the low speed nonvolatile storage that is adopted; After main processor unit writes easy mistake cache element with this blocks of data, notify corresponding intelligent node, after intelligent node is received instruction, the data of easily losing in the cache element are write the low speed non-volatile memory cells, and notify main processor operation to finish, wait for that then next blocks of data of primary processor writes request command.
The high-speed audio and video high-capacity storage that is applied to vehicle environment according to the said method design, it is characterized in that: main processor circuit is set, easily lose cache circuit, embedded intelligence node circuit and low speed non-volatile memory circuits, easily lose the mode that cache circuit adopts the twoport interface, its number is consistent with parallel intelligent node number, be connected with the embedded intelligence node circuit with main processor circuit respectively, main processor circuit, the embedded intelligence node circuit is by easily losing cache circuit swap data and order, and the embedded intelligence node circuit writes the low speed non-volatile memory circuits from easy mistake cache circuit sense data.Can adopt the parallel processing mode between the circuit, improve storage speed.
The present invention has following advantage and effect:
The FLASH storage medium that method by parallel work-flow writes low speed reaches bigger memory bandwidth;
The extensibility of system is good, only needs to increase the number of parallel node, just can increase memory bandwidth accordingly;
The realization volume of system is little, and resistance to shock is superior.Adopt common FLASH, the monolithic volume is very little, and antidetonation is good.
Description of drawings
Fig. 1 is the theory diagram of high speed mass memory method of the present invention;
Fig. 2 is a main processor circuit workflow of the present invention;
Fig. 3 is an embedded intelligence node circuit workflow of the present invention.
Embodiment
The present invention takes a plurality of intelligent node parallel work-flows to increase the mode of bandwidth, earlier metadata cache is easily being lost in the memory cell at a high speed and logically is being divided into some, will easily lose in the memory cell at a high speed respectively by a plurality of intelligent nodes then in one's own data block write in the low speed nonvolatile memory cell of own this intelligent node control.The size that at every turn needs data blocks stored is relevant with the size (n) of a sector of intelligent node number (m) and Nonvolatile memory device, and the speed that writes this contrive equipment is relevant with an erasable block size (n) required time (t) of intelligent node number (m) and Nonvolatile memory device; Operating master control each time deposits the data of m*n size in and easily loses memory cell at a high speed, intelligent node 1 writes the data of the first block size n in the low speed nonvolatile memory cell, intelligent node 2 writes the data of the second block size n in the low speed nonvolatile memory cell, and the like, because each intelligent node all is to move simultaneously and non-interfering, the time that then writes the data block of this contrive equipment m*n size is that t/m. that is to say that the number of node is big more, and the bandwidth of gained is big more.High speed of the present invention is easily lost the general employing of memory cell and is not limited only to multi-port memory unit simultaneously for many mouthfuls.
Referring to Fig. 1-3, easily lose the mode that cache circuit adopts the twoport interface, connecing main place device circuit with main processing respectively links to each other with the embedded intelligence node circuit, main Processing Interface circuit, embedded intelligence node circuit are by easily losing cache circuit swap data and order, the embedded intelligence node circuit writes the low speed non-volatile memory circuits from easy mistake cache circuit sense data, easily losing on the level of cache circuit, embedded intelligence node circuit, low speed non-volatile memory circuits, system has comprised m node.
Easily lose the interface that cache circuit adopts twoport, thereby the mutual use of main treatment circuit and the order of embedded intelligence node circuit writes the pin saltus step that data make chip by the command address to the twoport buffer memory, the opposite end adopts interruption or inquiry mode to obtain this order, and concrete order then will be checked the data block on the address of appointing in advance.
On main processor circuit was realized, main processor circuit was divided the data that needs write low speed non-volatile memory circuits (general available FLASH), and the size of each piece is n (n is the size of a sector of FLASH).Make that low speed non-volatile memory circuits interstitial content is m, then, write the 1st, the 2... m of low speed non-volatile memory circuits respectively respectively with the 1st, the 2... m piece of data flow.
Main processor circuit realize to be gone up on the algorithm flow as shown in Figure 2, main processor circuit can be taken turns the state information that continuous query easily loses the embedded intelligence node circuit of depositing in the cache circuit, when finding that the last operation of a certain node has been finished, the low speed non-volatile memory circuits data that will current needs be held under the arm as correspondence again write easy mistake cache circuit, and, notify the embedded intelligence node circuit to have data to need operation by the mode that Fig. 2 describes.
Be that respectively and easily an end address/data mouth of mistake cache circuit and the address/data mouth of low speed non-volatile memory circuits link to each other with the bus of a slice processor on the circuit of embedded intelligence node is realized.
The software flow of embedded intelligence node is seen Fig. 3, and the embedded intelligence node circuit is checked the data that leave in the easy mistake cache circuit after having received the message of main processor circuit transmission, parses data storage addresses and data length.Wipe then and see whether target sector is empty, and non-NULL is wiped.Then data are write the low speed non-volatile memory circuits, the mode of describing by Fig. 3 notifies the main processor circuit operation to finish at last.
Claims (4)
1, a kind of high-speed audio and video mass memory method that is applied to vehicle environment, it is characterized in that: take a plurality of intelligent node parallel work-flows to increase the mode of bandwidth, earlier metadata cache is easily being lost at a high speed in the memory cell, will easily lose in the memory cell at a high speed respectively by a plurality of intelligent nodes then in one's own data block write in the low speed nonvolatile memory cell of own this intelligent node control.
2, the high-speed audio and video mass memory method that is applied to vehicle environment according to claim 1, it is characterized in that: when main processor unit needs storage, the number that data block of main processor unit write-once storage device, the size of data block equal parallel node in the system multiply by the size of a sector of the low speed nonvolatile storage that is adopted; After main processor unit writes easy mistake cache element with this blocks of data, notify corresponding intelligent node, after intelligent node is received instruction, the data of easily losing in the cache element are write the low speed non-volatile memory cells, and notify main processor operation to finish, wait for that then next blocks of data of primary processor writes request command.
3, the high-speed audio and video high-capacity storage that is applied to vehicle environment according to the said method design, it is characterized in that: main processor circuit is set, easily lose cache circuit, embedded intelligence node circuit and low speed non-volatile memory circuits, easily lose the mode that cache circuit adopts the twoport interface, its number is consistent with parallel intelligent node number, be connected with the embedded intelligence node circuit with main processor circuit respectively, main processor circuit, the embedded intelligence node circuit is by easily losing cache circuit swap data and order, and the embedded intelligence node circuit writes the low speed non-volatile memory circuits from easy mistake cache circuit sense data.
4, the high-speed audio and video high-capacity storage that is applied to vehicle environment according to claim 3 is characterized in that: adopt the parallel processing mode between the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNA2007101355913A CN101237546A (en) | 2007-11-13 | 2007-11-13 | High-speed audio and video magnitude storage method and device for vehicular environment |
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| CNA2007101355913A CN101237546A (en) | 2007-11-13 | 2007-11-13 | High-speed audio and video magnitude storage method and device for vehicular environment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103946826A (en) * | 2011-09-30 | 2014-07-23 | 英特尔公司 | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
| US9342453B2 (en) | 2011-09-30 | 2016-05-17 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9600407B2 (en) | 2011-09-30 | 2017-03-21 | Intel Corporation | Generation of far memory access signals based on usage statistic tracking |
| US10241912B2 (en) | 2011-09-30 | 2019-03-26 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
-
2007
- 2007-11-13 CN CNA2007101355913A patent/CN101237546A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103946826A (en) * | 2011-09-30 | 2014-07-23 | 英特尔公司 | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
| US9317429B2 (en) | 2011-09-30 | 2016-04-19 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy over common memory channels |
| US9342453B2 (en) | 2011-09-30 | 2016-05-17 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US9600407B2 (en) | 2011-09-30 | 2017-03-21 | Intel Corporation | Generation of far memory access signals based on usage statistic tracking |
| US9619408B2 (en) | 2011-09-30 | 2017-04-11 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10241912B2 (en) | 2011-09-30 | 2019-03-26 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
| US10241943B2 (en) | 2011-09-30 | 2019-03-26 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10282322B2 (en) | 2011-09-30 | 2019-05-07 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10282323B2 (en) | 2011-09-30 | 2019-05-07 | Intel Corporation | Memory channel that supports near memory and far memory access |
| CN103946826B (en) * | 2011-09-30 | 2019-05-31 | 英特尔公司 | For realizing the device and method of multi-level store level on common storage channel |
| US10691626B2 (en) | 2011-09-30 | 2020-06-23 | Intel Corporation | Memory channel that supports near memory and far memory access |
| US10719443B2 (en) | 2011-09-30 | 2020-07-21 | Intel Corporation | Apparatus and method for implementing a multi-level memory hierarchy |
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