CN101253626A - 电路装置及其制造方法 - Google Patents

电路装置及其制造方法 Download PDF

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CN101253626A
CN101253626A CNA2006800320484A CN200680032048A CN101253626A CN 101253626 A CN101253626 A CN 101253626A CN A2006800320484 A CNA2006800320484 A CN A2006800320484A CN 200680032048 A CN200680032048 A CN 200680032048A CN 101253626 A CN101253626 A CN 101253626A
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circuit
circuit substrate
substrate
lead
conductive pattern
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CN101253626B (zh
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高草木贞道
坂本则明
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种使组装的电路的动作稳定化的电路装置。混合集成电路装置(10)具备大致在同一平面上配置的多个电路基板(11A)、(11B)、(11C)。在这些电路基板各自上面形成有由导电图形和电路元件构成的电路。且这些电路基板被密封树脂(14)一体支承。与电路基板表面形成的电路连接的引线(25)被从密封树脂(14)向外部导出。

Description

电路装置及其制造方法
技术领域
本发明涉及电路装置及其制造方法，特别是涉及具有多个表面组装有电路的电路基板的电路装置及其制造方法。
背景技术
参照图6说明现有的混合集成电路装置100的结构(例如参照日本特开平5-102645)。在矩形基板101的表面经由绝缘层102形成有导电图形103。电路元件固着在导电图形103的希望的部位而形成规定的电路。在此，作为电路元件是把半导体元件105A和芯片元件105B与导电图形103连接。引线104与基板101周边部形成的、由导电图形103构成的焊盘109连接，作为外部端子起作用。密封树脂108具有把基板101表面形成的电路密封的功能。
但上述混合集成电路装置100由于把多个电路元件安装在单一的基板101上，所以存在电路元件之间相互产生恶劣影响的问题。具体说就是，作为半导体元件105A有时采用进行大电流开关动作的功率类开关元件和进行小信号处理的LSI。这时，随着开关元件的动作，由金属构成的基板101的电位变动，通过LSI的数mA的电信号有可能恶化。并且，作为电路元件而采用发热量大的元件时，则基板101整体被加热，LSI等其他电路元件有可能受到恶劣影响。
在制造方法上，当变更基板101表面组装的电路时，则需要变更导电图形103的图形形状和电路元件的配置，有产生巨大成本的问题。
发明内容
本发明是鉴于上述问题而开发的，本发明的主要目的在于提供一种使组装的电路动作稳定化的电路装置。并且，本发明的目的在于提供一种能灵活应对内置的电路变更的电路装置的制造方法。
本发明的电路装置具备：电路基板、由所述电路基板上面形成的导电图形和电路元件构成的电路、与所述电路电连接并向外部导出的引线，设置有多个独立的所述电路基板，在各个所述电路基板上设置所述导电图形、所述电路元件和所述引线。
本发明电路装置的制造方法具备：准备具有由多个引线构成的单元的引线框的工序、在电路基板的上面形成由导电图形和电路元件构成的电路的工序、把多个电路基板与一个所述单元的引线连接并把所述电路基板机械地保持在所述引线框上的工序、由密封树脂把所述多个电路基板一体覆盖的工序。
附图说明
图1(A)是本发明电路装置的立体图，图1(B)是本发明电路装置的立体图；
图2(A)是本发明电路装置的剖面图，图2(B)是本发明电路装置的电路图；
图3(A)是说明本发明电路装置制造方法的平面图，图3(B)是说明本发明电路装置制造方法的平面图；
图4(A)是说明本发明电路装置制造方法的平面图，图4(B)是说明本发明电路装置制造方法的剖面图；
图5(A)是说明本发明电路装置制造方法的剖面图，图5(B)是说明本发明电路装置制造方法的平面图；
图6是说明现有混合集成电路装置的剖面图。
具体实施方式
<第一实施例>
本实施例作为电路装置的一例来说明混合集成电路装置10的结构。
参照图1说明本发明混合集成电路装置10的结构。图1(A)是从斜上方看混合集成电路装置10的立体图。图1(B)是省略了密封整体的密封树脂14的混合集成电路装置10的立体图。
参照图1(A)和图1(B)，本实施例的混合集成电路装置10具备配置在大致同一平面上的多个电路基板11A、11B、11C。这些电路基板各自的上面形成有由导电图形和电路元件构成的电路。这些电路基板被密封树脂14一体支承。与电路基板表面形成的电路连接的引线25被从密封树脂14向外部导出。各个电路基板11A、11B、11C的结构基本相同，所以以下说明电路基板11A的结构。
电路基板11A是以(Al)或铜(Cu)等金属为主要材料的金属基板。电路基板11A的具体大小例如是长×宽×厚度＝30mm×15mm×1.5mm左右。作为电路基板11A在采用由铝构成的基板时，电路基板11A的两主面形成有氧化膜，被进行阳极化处理。
电路基板11A侧面的形状随制造方法不同而不同。在使用冲压机冲压来制造电路基板11A时，电路基板11A的侧面是直线形状。另一方面，在形成V字形分断槽来制造电路基板11A时，电路基板11A的侧面成为向外侧突出的形状。
绝缘层12A形成为把电路基板11A的整个上面覆盖。绝缘层12A由高填充有Al2O3等填料的环氧树脂等构成。通过在绝缘层12A混入填料而能降低绝缘层12A的热阻抗，能把内置的电路元件所产生的热积极地向电路基板11A传导。绝缘层12A的具体厚度例如是50μm左右。
也可以把电路基板11A的背面由绝缘层12A覆盖。这样，即使把电路基板11A的背面从密封树脂14向外部露出，也能使电路基板11A的背面与外部绝缘。
导电图形13A由铜等金属构成，并形成规定电路而形成在绝缘层12A的表面。在引线25A导出的边上形成有由导电图形13构成的焊盘。且在电路元件15A的周围也形成有由导电图形13A构成的多个焊盘，该焊盘与电路元件15A通过金属细线17连接。在此，图示了单层的导电图形13A，但也可以把经由绝缘层层积的多层导电图形13A形成在电路基板11A的上面。且也可以形成用于与其他电路基板11B、11C连接的焊盘18A。
作为安装在电路基板11A上的电路元件15A可以全面地采用有源元件或无源元件。具体地说，能把晶体管、LSI芯片、二极管、芯片阻抗、芯片电容、电感、热敏电阻、天线、振荡器等作为电路元件15A采用。树脂密封型的封装体等也能作为电路元件15A固着在导电图形13A上。图中把芯片元件和半导体元件作为电路元件15A进行了图示。本实施例中作为电路元件15A是采用功率类开关元件。该电路元件15A由安装在电路基板11B的控制元件即电路元件15B所控制。
本实施例具有表面安装有电路元件的多个电路基板，各电路基板安装有不同的电路元件。在此作为一例，位于中央的电路基板11B安装有作为控制元件发挥作用的LSI即电路元件15B。位于电路基板11B两端的电路基板11A、11C安装有被电路元件15B控制的开关元件即电路元件15A、15C。在此，作为电路元件15A、15C例如能采用有1A以上大电流通过的半导体元件。具体地说，能把MOSFET(Metal-Oxide Semiconductor FieldEffect Transistor：金属氧化物场效应晶体管)、IGBT(Insulated Gate BipolarTransistor：绝缘栅双极型晶体管)、IC(Integrated Circuit：集成电路)、双极型晶体管等作为电路元件15A、15C来采用。
引线25A的一端与电路基板11A上的焊盘电连接，另一端从密封树脂14向外部导出。引线25A由以铜(Cu)、铝(Al)或Fe-Ni合金等为主要成分的金属构成。在此，与沿电路基板11A相对的两个侧边设置的焊盘上连接有引线25A。但也可以与沿电路基板11A的一个侧边或四个侧边设置焊盘，在该焊盘上连接引线25A。
密封树脂14通过使用热固性树脂的传递模注塑或使用热塑性树脂的喷射注塑来形成。在此，可以使也包括背面的电路基板11A整体被密封树脂14包覆，也可以使电路基板11A的背面从密封树脂14露出。在此，通过密封树脂14把三个电路基板11A、11B、11C一体支承。
以上是电路基板11A的结构，内置于混合集成电路装置10的其他电路基板11B、11C的结构也基本相同。这些电路基板之间的不同点在于表面所形成的电路不同。
各电路基板11A、11B、11C的表面所形成的电路经由作为连接机构的金属细线17而相互连接。具体说就是电路基板11A的表面所形成的焊盘18A与电路基板11B的表面所形成的焊盘18B经由金属细线17连接。电路基板11B的表面所形成的焊盘18B与电路基板11C的表面所形成的焊盘18C经由金属细线17连接。也可以把电路基板11A的焊盘18A与电路基板11C的焊盘18C使用金属细线17连接。这种情况在通过位于中央的电路基板11B的上方形成金属细线17。在此，也可以代替金属细线17而使用引线形状等的板状导电部件。
参照图2(A)说明连接部19A的结构。连接部19A是把电路基板11A与导电图形13A电连接的部位，其他电路基板11B、11C也可以设置同样形状的连接部。
连接部19A的结构是：使覆盖电路基板11A上面的绝缘层12A开口而部分地把电路基板11A露出，把露出部分的电路基板11A与导电图形13A由金属细线17连接。
通过设置连接部19A，能使电路基板11A上面形成的电路的动作稳定化。例如当导电图形13A与电路基板11A的电位不同时，由于绝缘层12A位于两者之间而有可能产生寄生电容，导致电路的误动作。本实施例通过连接部19A而保持导电图形13A与电路基板11A的电位大致相同，所以能降低寄生电容。因此，能使电路基板11A上面形成的由导电图形13A和电路元件15A构成电路的动作稳定化。
当经由连接部19A把电路基板11A与固着电位(例如电源电位或接地电位)连接，则电路基板11A的电位就被一直固着，所以能更增大稳定上述电路的效果。
参照图2(B)说明本实施例混合集成电路装置10中内置电路的一例。在此图示的是驱动三相电机20的变换电路。该变换电路具有被控制电路24控制的六个开关元件Q1～Q6。Q1与Q2的中间点、Q3与Q4的中间点、Q5与Q6的中间点与电机20连接。开关元件Q1～Q6的控制电极与控制电路24连接。
根据从控制电路24供给的控制信号而开关元件Q1～Q6在规定的时刻进行开关动作，这样从电源21供给的直流电就被变换成交流电。被变换的交流电向电机20供给，则电机20旋转。
参照图1，上述控制电路24相当于安装在电路基板11B的电路元件15B。上述开关元件Q1～Q6相当于安装在电路基板11A、11C的电路元件15A、15C。因此，当本实施例混合集成电路装置10内置有变换电路时，能使该变换电路的动作稳定化。
下面详细叙述本实施例的优点。
根据本实施例的混合集成电路装置10，即使内置的电路产生变更时，也能容易且低成本地进行应对。具体说就是本实施例中，组合被模块化的电路基板11A、11B、11C来构成具有规定功能的混合集成电路装置10。在此，把安装有控制元件即电路元件15B的电路基板11B、和安装有被该电路元件15B控制的开关元件即电路元件15A、15C的电路基板11A、11C进行组合。把各电路基板所安装的电路元件使用金属细线17连接。因此，即使混合集成电路装置10内置的电路产生变更，则仅变更电路基板11A、11B、11C的任一个就能应对。例如在控制整个电路动作的控制电路产生变更时，则仅更换安装有控制元件即电路元件15B的电路基板11B就能应对。在变更开关元件的容量等时，则仅变更电路基板11A或11C就能应对。
本实施例的混合集成电路装置10把开关元件即电路元件15A和控制元件即电路元件15B安装在不同的基板上，所以能防止由电路元件15A的发热而引起的电路元件15B的误动作。具体说就是，开关元件即电路元件15A由于有大电流通过，所以产生大量的热。因此，若把电路元件15A和电路元件15B安装在同一电路基板上，则电路元件15A所产生的热经由导热性优良的电路基板向电路元件15B传导，有可能招致电路元件15B的误动作。于是本实施例把电路元件15A和电路元件15B安装在不同的电路基板11A、11B上。结果是即使电路元件15A发热，也是加热安装有电路元件15A的电路基板11A，而与电路基板11A离开配置的电路基板11B不会成为太高的温度。因此，控制元件即电路元件15B几乎不受开关元件即电路元件15A发热的影响。
利用上述结构能防止由电路基板电位变动而引起的电路误动作。具体说就是，向开关元件即电路元件15A例如施加数十V的高电压。另一方面向控制元件即电路元件15B施加数V的低电压。因此，若把两者安装在同一电路基板上，则随着电路元件15A的开关电路基板的电位变动，控制元件即电路元件15B有产生误动作的危险性。本实施例把开关元件即电路元件15A和控制元件即电路元件15B安装在各自的电路基板11A、11B上。因此，即使电路元件15A进行开关动作，而电位变动的仅是安装有电路元件15A的电路基板11A，电路基板11B的电位不变动。结果是控制元件即电路元件15B不会受到开关元件即电路元件15A的电气方面的恶劣影响。
利用上述本实施例的结构，即使把不同种类的电路内置在一个电路装置中时，也能抑制电路之间相互给予的恶劣影响。例如把有源滤波器和变换电路内置在一个电路装置中时，有源滤波器是容易受噪声的恶劣影响的精密电路。因此需要抑制构成变换电路的高频开关元件所产生的噪声向有源滤波器传播。若采用本实施例，则能把有源滤波器和变换电路形成在不同的基板上面而把两者分离，能抑制变换电路所产生的噪声给予有源滤波器的恶劣影响。
<第二实施例>
本实施例参照图3到图5说明混合集成电路装置的制造方法。
参照图3，首先准备设置有多个引线25的引线框40。图3(A)是表示引线框40上设置的一个单元46的平面图，图3(B)是表示引线框40整体的平面图。
参照图3(A)，单元46由一端位于安装有电路基板11A、11B、11C的区域内的多个引线25构成。引线25在纸面上从左右两个方向向安装有电路基板的区域延伸。多个引线25通过从外框41延伸的连接杆44相互连接而能防止变形。本实施例由于把引线25的端部固着在电路基板的上面，所以引线25的前端部延伸到电路基板的内部区域。本实施例在一个单元46中配置有三个电路基板11A、11B、11C。
参照图3(B)，长方形的引线框40中多个上述结构的单元46分开地配置。本实施例通过向引线框40设置多个单元46来制造混合集成电路装置，能把引线接合和注塑工序等一并进行，提高生产性。
参照图4，接着在引线框40上固着电路基板。图4(A)是表示引线框40的单元46的平面图，图4(B)是固着有电路基板11A的部位的剖面图。
参照图4(A)，如上述那样，本实施例在一个单元46中固着有多个电路基板。在这些电路基板表面设置的由导电图形构成的焊盘上，经由焊锡等固着材料而固着引线25的前端部，这样，各电路基板就相对引线框40被固着。
在此，经由引线25在一个单元46中固着有三个电路基板11A、11B、11C。这样，能使用引线框40把三个电路基板11A、11B、11C的相对位置固着。即把电路基板11A、11B、11C配置在大致同一平面上且离开规定的距离。这样，在形成金属细线的工序和进行树脂密封的工序中，不需要对各电路基板进行个别的位置辨认，能把这些工序简略化。在此是把三个电路基板11A、11B、11C配置在一个单元46中，但配置的电路基板数目也可以是两个、也可以是四个以上。
本实施例也可以把安装有半导体元件等电路元件15A、15B、15C的电路基板11A、11B、11C固着在引线框40上，也可以把电路基板固着在引线框40上之后再进行电路元件的安装和金属细线的形成。
把电路基板11A、11B、11C固着在引线框40上之后，使用金属细线17把各电路基板表面形成的电路电连接。具体地是使用金属细线17连接电路基板11A的表面所形成的焊盘18A与连接于电路基板11B表面的焊盘18B。同样地，把电路基板11B的表面所形成的焊盘18B与电路基板11C的表面所形成的焊盘18C连接。在此，也可以代替金属细线17而使用引线等板状导电部件。
参照图5，接着以覆盖各电路基板的方式形成密封树脂14。图5(A)是表示使用模具对电路基板11进行注塑的工序的剖面图，图5(B)是表示进行注塑后引线框40的平面图。
参照图5(A)，首先把电路基板收容在由上模具22A和下模具22B形成的模腔23中。该剖面图表示了一个电路基板11A，但实际上在一个模腔23中配置有三个电路基板11A、11B、11C，被密封树脂14一体密封。
在此，通过使上模具22A和下模具22B与引线25接触而固着电路基板11A等在模腔23内部的位置。从设置在模具上的注塑口(未图示)向模腔23注入树脂而把电路基板密封。随着向模腔23内部注入密封树脂而模腔23内部的空气经由未图示的注塑口被向外部放出。本实施例进行使用热固性树脂的传递模注塑或使用热塑性树脂的喷射注塑。
参照图5(B)，在上述注塑工序结束后把引线25从引线框40分离。具体说就是在设置有连接杆44的部位把引线25个别分离，把图1所示的混合集成电路装置10从引线框40分离。本实施例在密封树脂14的内部内置有三个电路基板11A、11B、11C。
根据本发明的电路装置，在多个电路基板各自的上面形成有由导电图形和电路元件构成的电路。因此，配置在不同基板上的电路元件之间相互不会有恶劣影响，所以能使装置内部形成的电路的动作稳定化。
根据本发明电路装置的制造方法，把表面形成有电路的电路基板多个组合而构成电路装置。因此，即使电路装置内置的电路产生变更，也能通过仅更换电路基板的组合就能应对，所以，能降低伴随电路变更的成本。

Claims (11)

1、一种电路装置，其特征在于，具备：电路基板、由所述电路基板上面形成的导电图形和电路元件构成的电路、与所述电路电连接并向外部导出的引线，
设置有多个独立的所述电路基板，
在各个所述电路基板上设置所述导电图形、所述电路元件和所述引线。
2、如权利要求1所述的电路装置，其特征在于，在不同的所述电路基板上形成的所述电路经由连接机构被电连接。
3、如权利要求2所述的电路装置，其特征在于，所述连接机构是金属细线。
4、如权利要求1所述的电路装置，其特征在于，至少在一个所述电路基板上设置有连接所述导电图形和所述电路基板的连接部。
5、如权利要求1所述的电路装置，其特征在于，所述电路元件包括控制元件和被所述控制元件控制的开关元件，
所述控制元件和所述开关元件被安装在不同的所述电路基板上。
6、如权利要求1所述的电路装置，其特征在于，在同一平面上配置多个所述电路基板。
7、如权利要求1所述的电路装置，其特征在于，多个所述电路基板利用密封树脂被一体支承。
8、如权利要求1所述的电路装置，其特征在于，内置的所述电路基板相互离开地配置。
9、一种电路装置的制造方法，其特征在于，具备：
准备具有由多个引线构成的单元的引线框的工序、
在电路基板的上面形成由导电图形和电路元件构成的电路的工序、
把多个电路基板与一个所述单元的引线连接并把所述电路基板机械地保持在所述引线框上的工序、
由密封树脂把所述多个电路基板一体覆盖的工序。
10、如权利要求9所述的电路装置的制造方法，其特征在于，
在所述电路基板的表面形成有由导电图形构成的焊盘，
通过把所述引线经由固着材料固着在所述焊盘上而把所述电路基板固着在所述引线框上。
11、如权利要求9所述的电路装置的制造方法，其特征在于，经由金属细线把不同的所述电路基板上形成的所述电路进行连接。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347307A (zh) * 2010-07-22 2012-02-08 安森美半导体贸易公司 电路基板、电路装置及其制造方法、带有绝缘层的导电箔
CN102548214A (zh) * 2010-12-24 2012-07-04 半导体元件工业有限责任公司 电路装置及其制造方法
CN108000798A (zh) * 2017-12-13 2018-05-08 陕西宝成航空仪表有限责任公司 适用于电沉积工艺制造的微型导电环环体成型方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5749468B2 (ja) * 2010-09-24 2015-07-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 回路装置およびその製造方法
JP5743922B2 (ja) * 2012-02-21 2015-07-01 日立オートモティブシステムズ株式会社 熱式空気流量測定装置
US10629521B2 (en) * 2014-04-08 2020-04-21 Mitsubishi Electric Corporation Molded module
US11437304B2 (en) 2014-11-06 2022-09-06 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9408301B2 (en) 2014-11-06 2016-08-02 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
US9397017B2 (en) 2014-11-06 2016-07-19 Semiconductor Components Industries, Llc Substrate structures and methods of manufacture
TWI730604B (zh) * 2019-01-22 2021-06-11 美商莫仕有限公司 使用專用電子封裝製造工藝的智能連接器及其製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6197895A (ja) 1984-10-18 1986-05-16 日本電気株式会社 混成集積回路装置
KR910001419B1 (ko) * 1987-03-31 1991-03-05 가부시키가이샤 도시바 수지봉합형 집적회로장치
EP0339154B1 (en) * 1988-04-26 1994-11-17 Citizen Watch Co. Ltd. Memory card
JP2828752B2 (ja) 1990-08-31 1998-11-25 三洋電機株式会社 混成集積回路装置
JP2951102B2 (ja) 1991-05-23 1999-09-20 三洋電機株式会社 混成集積回路
US5559374A (en) * 1993-03-25 1996-09-24 Sanyo Electric Co., Ltd. Hybrid integrated circuit
JP3233507B2 (ja) * 1993-08-13 2001-11-26 株式会社東芝 半導体装置
JP3516789B2 (ja) * 1995-11-15 2004-04-05 三菱電機株式会社 半導体パワーモジュール
JPH09213877A (ja) * 1996-02-02 1997-08-15 Toshiba Corp マルチチップモジュール半導体装置
JPH11233712A (ja) * 1998-02-12 1999-08-27 Hitachi Ltd 半導体装置及びその製法とそれを使った電気機器
JP2001203314A (ja) 2000-01-20 2001-07-27 Matsushita Electric Ind Co Ltd 半導体装置
JP4037589B2 (ja) * 2000-03-07 2008-01-23 三菱電機株式会社 樹脂封止形電力用半導体装置
JP2002083927A (ja) 2000-09-07 2002-03-22 Matsushita Electric Ind Co Ltd 半導体装置
JP3910383B2 (ja) * 2001-07-17 2007-04-25 株式会社日立製作所 パワーモジュールおよびインバータ
DE102005016830A1 (de) * 2004-04-14 2005-11-03 Denso Corp., Kariya Halbleitervorrichtung und Verfahren zu ihrer Herstellung
US7565738B2 (en) * 2004-05-31 2009-07-28 Sanyo Electric Co., Ltd. Method for manufacturing circuit device
US7273300B2 (en) * 2004-08-06 2007-09-25 Lumination Llc Curvilinear LED light source

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102347307A (zh) * 2010-07-22 2012-02-08 安森美半导体贸易公司 电路基板、电路装置及其制造方法、带有绝缘层的导电箔
CN102548214A (zh) * 2010-12-24 2012-07-04 半导体元件工业有限责任公司 电路装置及其制造方法
CN108000798A (zh) * 2017-12-13 2018-05-08 陕西宝成航空仪表有限责任公司 适用于电沉积工艺制造的微型导电环环体成型方法

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WO2007026945A1 (ja) 2007-03-08
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US20090135572A1 (en) 2009-05-28
CN101253626B (zh) 2010-09-29
JP5378683B2 (ja) 2013-12-25
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