CN101261880A - 可编程导体随机存取存储器以及用于检测它的方法 - Google Patents

可编程导体随机存取存储器以及用于检测它的方法 Download PDF

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CN101261880A
CN101261880A CNA2008100915787A CN200810091578A CN101261880A CN 101261880 A CN101261880 A CN 101261880A CN A2008100915787 A CNA2008100915787 A CN A2008100915787A CN 200810091578 A CN200810091578 A CN 200810091578A CN 101261880 A CN101261880 A CN 101261880A
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CN101261880B (zh
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S·L·卡斯珀
K·G·迪斯曼
G·胡斯
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Micron Technology Inc
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
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    • G11C13/0069—Writing or programming circuits or methods
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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    • G11C—STATIC STORES
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    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Abstract

提供了一种用于检测可编程导体随机存取存储器(PCRAM)单元的电阻等级的读取电路。通过激活存取晶体管、根据升高的行线电压将电压电势差引入PCRAM单元的两端。将数字线和数字互补参考线预充电为第一预定电压。正被读出的单元具有预充电电压，所述预充电电压经由PCRAM单元的可编程导体存储器元件的电阻而放电。将数字线处读取的电压和基准导体处的电压进行比较。如果数字线处的电压大于参考电压，那么将所述单元作为高电阻值(例如逻辑高)读取；然而，如果测量于数字线的电压低于参考电压，那么将所述单元作为低电阻值(例如逻辑低)读取。

Description

可编程导体随机存取存储器以及用于检测它的方法
本分案申请的母案申请的国家申请号是03808768.5，母案申请的国际申请日为2003年2月10日，母案申请的国际申请号为PCT/US03/03674。
发明背景
1.发明领域：
本发明涉及集成的存储电路。更具体地说，它涉及一种用于读出可编程导体随机存取存储器(PCRAM)单元的内容的方法。
2.现有技术说明：
DRAM集成电路阵列已经存在了三十多年了，并且它们在存储容量方面的惊人的增加通过半导体制造技术以及电路设计工艺方面的进展而得以实现。这两个技术方面的惊人发展，也进一步获得了越来越高的集成度，在增强了处理能力的同时，极大地降低了存储器的阵列大小和成本。
DRAM存储器单元通常包括，作为基本部件的存取晶体管(开关)以及电容器，所述电容器以电荷的形式存储二进制数据位。通常，将一个极性的电荷存储在所述电容器上以表示逻辑高(例如二进制“1”)，而存储的相反极性的电荷表示逻辑低(例如二进制“0”)。DRAM的基本缺陷在于：电容器上的电荷会最终泄漏，因此必须定期的“刷新”电容器电荷，否则存储器单元存储的数据位会丢失。
另一方面，常规的SRAM存储器单元包括存取晶体管，或者多个晶体管和以两个或更多集成电路设备互联作为双稳锁存器形式的存储器元件作为基本部件。这种双稳锁存器的例子可以是诸如：交叉耦合反相器。在DRAM存储器单元的情况下，双稳锁存器不需要“刷新”，并且将长时间可靠地存储数据位，只要它们能连续接收电源电压。
人们一直在努力去发现其他形式的非易失性或者半易失性存储器元件。最近的研究已经集中在这样一种电阻材料上，所述材料可以被编程以表现出或高或低的稳定电阻状态。这种材料的可编程电阻元件可以被编程(设置)为高阻状态，以便存储例如二进制“1”的数据位，或者被编程为低阻状态，以便存储二进制“0”的数据位。存取设备因此能通过检测接通电阻存储器元件的读出电流的数值来检索所存储的数据位，由此来揭示其预先编程的稳定的电阻状态。
最新的可编程导体存储器元件已经设计出来。例如，已经研究出将具有可转换的电阻状态的硫族化物玻璃作为数据存储器单元以供存储器件之用，诸如DRAM存储器件。美国专利5,761,115、5,896,312、5,914,893和6,084,796均描述了这种技术，在此一并引用，以供参考。诸如上述的硫族化物玻璃形式的可编程导体存储器元件的特性之一在于：它通常包括这样一种硫族化物玻璃，其被掺杂金属离子，并且阴极和阳极被隔开，分布在一个或多个玻璃表面上。掺杂玻璃具有正常和稳定的高阻状态。在阴极和阳极两端施加的电压在玻璃中产生了稳定的低电阻通路。由此，可以使用稳定的低阻和高阻状态来存储二进制数据。
由掺杂硫族化物玻璃材料形成的可编程导体存储器元件通常具有稳定的高阻状态，可以通过把电压加到存储器元件两端来将其编程为低阻状态。为了将所述存储器单元恢复为高阻状态，通常人们需要利用负电压或反相电压来编程所述存储器单元，其中所述电压等于或者大于用于将所述存储器元件编程为低阻状态的电压。一种特别有前景的可编程导体硫族化物玻璃含有Ge:Se玻璃成分，并且掺杂了银。
而用于从可编程导体存储器元件阵列读出数据的适当的电路还没有完全开发出来。据此，为了实现功能性的可编程导体存储器，需要适当的读取电路来非破坏性地读出存储在所述阵列的存储器元件中的数据。
发明概述
提供了一种用于读取可编程导体随机存取存储器(PCRAM)单元的电阻水平的电路。通过根据上升行线电压激活存取晶体管、将电势差引入PCRAM单元两端。将数字线和数字互补基准线预先充电到最初的预定电压。被读出的单元具有预充电电压，所述预充电电压经由PCRAM单元的可编程导体存储器元件的电阻而放电。对数字线处读取的电压和在基准导体处读取的电压进行比较。如果数字线处的电压大于所述基准电压，那么将所述单元作为高电阻值(例如逻辑高)读出；然而，如果测量于数字线的电压低于基准电压，那么将所述单元作为低电阻值(例如逻辑低)读出。依照本发明的另一方面，为了将逻辑“HIGH(高)”重写回单元中，在读出所述单元之后，可以将与被读出单元相关联的行线提升为高压。
附图简述
本发明的上述及其他优势和特征，通过结合附图对本发明的优选实施例的详细说明而变得更为明朗，其中：
图1描述了依照本发明示范性实施例、均采用多个PCRAM存储器单元的两个存储器阵列；
图2(a)-2(d)均描述了图1的PCRAM存储器单元；
图3描述了用于图1存储器阵列的N检测放大器；
图4描述了用于图1存储器阵列的P检测放大器；
图5示出了依照本发明示范性实施例描述操作流程的流程图；
图6描述了依照本发明示范性实施例、在读出的存储器单元中读取高电阻的时序图；
图7描述了依照本发明示范性实施例、在读出的存储器单元中读取低电阻的时序图；以及
图8描述了依照本发明示范性实施例、包含PCRAM存储器的基于处理器的系统框图。
优选实施例详述
本发明将结合图1-8，依照在下面描述的示范性实施例中阐述的那样来描述。其他实施例也可以实现，并且在不脱离本发明的精神或者范围的情况下，可以对所公开的实施例做出其他修改。
依照本发明的示范性实施例，将一对存储器阵列与相应的多个检测放大器耦合，其中每个存储器阵列由多个可编程导体存储器单元组成。为了读取特定存储器单元的逻辑状态，必须将适当的电压差施加在可编程导体存储器元件两端。所述电压差必须足以能够支持对可编程导体存储器元件的读操作，但是不足以对所述元件进行编程(或者写入)。一旦所述存储器元件两端施加适当的电压差，数字(位)线电压值经由所述存储器单元以及经由所述可编程导体存储器元件进行放电。在放电开始后的预定时间，经由与特定存储器单元相关联的检测放大器、在数字线电压以及基准位线处的数字互补基准电压之间进行比较。
如果在预定时间之后，数字线电压高于基准线处电压，那么检测到的状态为高阻状态，并且将基准线接地。然而，如果数字线电压低于基准线106处的电压，那么检测到的状态为低阻状态，并且将数字线接地。所述基准电压由与相邻存储器阵列相关联的数字互补线提供。当两个存储器阵列的另一个包含所选择的存储器单元时，所述两个相邻的存储器阵列分别充当基准电压的电源。图1提供了本发明的示范性实施例的更多细节。
图1描述了一对存储器阵列100，165的一部分，每个均具有多个列108，112，106，110以及多个行122，126，128，124，130，132。在列和行的每个交点处形成可编程导体随机存取存储器(PCBAM)单元，诸如存储器单元120。检测放大器102接收来自列线108和列线106的输入。检测放大器104接收来自列线112和列线110的输入。将每个检测放大器102，104经配置，可以对正被读取的单元120的数字(位)线(例如108)处的电压与基准线(例如106)处的电压进行比较，以便确定读出的存储器单元120存储了逻辑高的值还是逻辑低的值。依照图1的体系结构，如果单元120正被读取，那么检测放大器102将数字线108处的电压与补充数字线106上的基准电压比较。
取决于检测放大器102的哪端包含感兴趣的存储器单元120，数字线108或者106充当数字线D，另一端的数字线106充当基准数字线D*。在此例子中，假设存储器单元120是正被读出的单元。与存储器单元120相关联的列线108称为数字(位)线D。列线106称为数字互补线D*或者基准线。
每个可编程导体存储器单元120包括存取晶体管114和可编程导体存储器元件116。可编程导体存储器元件116的一端与单元极板118耦合。所述可编程导体存储器元件116的另一端与存取晶体管114的源/漏极耦合。存取晶体管114的另一源/漏极与数字线108耦合。存取晶体管114的栅极与行线122耦合，所述行线122与存储器单元120相关联。
此外，D和D*线与预充电电路175耦合，所收预充电电路用于将D和D*线预充电为预定电压值(例如Vdd)。所述D*线耦合到p型互补金属氧化物半导体(CMOS)晶体管177的一个端子，而晶体管177的另一端子与Vdd耦合。所述D线与p型CMOS晶体管179的一个端子耦合，而晶体管179的另一端子与Vdd耦合。将晶体管177，179的栅极连接在一起，以便接收预充电控制信号。当接收到所述预充电控制信号时，晶体管177，179都被导通，并且数字线D和数字互补线D*被充电至Vdd。图1还示出了均衡电路176，用于均衡D和D*数字线上的电压。在通过预充电信号将D和D*预充电为Vdd之后，通过均衡施加到晶体管180的EQ信号来均衡所述线。
转向图2(a)，图2(a)描述了可编程导体存储器单元120的简单示意图。利用有代表性的单元120来描述本发明，在预充电期间，数字线D 108与Vdd耦合，并且还与存取晶体管114的第一端子耦合。把存取晶体管114描写成n型CMOS晶体管；然而，可以轻易地将存取晶体管114替换为p型CMOS晶体管，只要据此修改另一个部件的相应极性和电压就行。所述可编程导体存储器元件116的第一端子与存取晶体管114的第二端子耦合。如上所述，可编程导体存储器元件116可以用硫族化物玻璃制成，或者允许存储二进制值的所有其他双稳态电阻材料制成。所述可编程导体存储器元件116与单元极板118耦合，其也是多个可编程导体存储器元件的通用导体。所述单元极板118附带有电压端子，用于向单元极板118提供预定电压电平(例如Vdd/2)。存取晶体管114的栅极附带有行线122。当将足够的电压施加到行线122，存取晶体管114被导通，并且导电，同时将数字线D 108耦合到可编程导体存储器元件116。
施加到行线122的电压值反映了在可编程导体存储器元件116上进行过何种操作。例如，假定D线108附带有Vdd(例如2.5V)，单元极板附带有1/2Vdd(例如1.25V)，那么为了激活存取晶体管114，最少必须将2.05V的电压施加到它的栅极。由于其在与单元极板118耦合的栅极和源/漏极之间建立了至少近似0.8V阈值电压(Vt)的电势差，所以存取晶体管114的栅极处的2.05V电压足以导通晶体管114。
虽然施加到存取晶体管114栅极的2.05V电压足以使其导通，但是它不足以从可编程导体存储器单元120读取或者向其写入。依照本发明的示范性实施例，在可编程导体存储器元件116两端需要大约0.2V电压以便读取它。此外，为了向可编程导体存储器元件116写入(例如重编程其值)，它两端最少需要0.25V电压，并且0.25V电压的极性取决于正被重写入存储器元件116的是逻辑高还是逻辑低。
转向图2(b)，将更加详细的论述电压电平和它们的极性。对于读操作来说，由于在可编程导体存储器元件116的两端需要大约0.2V电压，所以将大约2.25V的电压施加到与存取晶体管122栅极耦合的行线122。2.25V中减去阈值电压Vt，则节点A的电压大约1.45V。正处于1.25V电压的单元极板在可编程导体存储器元件116的两端产生0.2V的电压降；此电压足以读取元件116的内容，但是不足以对所述元件116进行写。
图2(c)描述了用于将逻辑低写回可编程导体存储器元件116的示范性电压电平以及极性。正如下面要更加详细描述的那样，当已经读取逻辑低电平作为可编程导体存储器单元120正存储的时，检测放大器102将D线108接地。点A同时处于近似接地电压，因此，在可编程导体的两端有大约-1.25V的电压降，并且可能将逻辑低重写回可编程导体存储器元件116。
图2(d)描述了用于将逻辑高写回可编程导体存储器元件116的示范性电压电平以及极性。正如下面要更加详细描述的那样，当已经读取逻辑高电平作为可编程导体存储器单元120正存储的时，检测放大器102将D线108升高到近似Vdd电压。然后，行线122从近似2.25V电压(在读操作期间它的电压电平)提升到近似Vdd，由此在点A处设置大约1.7V的电压。点A处1.7V的电压在可编程导体存储器元件116两端建立近似0.45V的势差，以便重写逻辑高电平。
返回参考图1，所述检测放大器102包括N检测放大器部件以及P检测放大器部件。图3描述了N检测放大器部件350。N检测放大器350的第一端子接收数字互补线D*(即，邻近于包含感兴趣的存储器单元的存储器阵列的存储器阵列中的列线)，并且还将其与N型CMOS晶体管305的栅极以及N型CMOS晶体管300的第一端子耦合。N检测放大器350的第二端子接收数字线D(即，邻近于包含感兴趣单元的存储器阵列中的列线)，并且还将其与晶体管300的栅极以及晶体管305的第一端子耦合。将晶体管300的第二端子以及晶体管305的第二端子与CMOS晶体管310的第一端子耦合。将晶体管310的第二端子与地耦合，并且晶体管310的栅极接收Fire N控制信号。在激发所要求的存储器单元列线之后的一预定时间，由N检测放大器350接收Fire N控制信号，如下面将描述的那样。
图4描述了诸如检测放大器102的检测放大器的P检测放大器部件360。P检测放大器360的第一端子接收数字互补线D*，并且还与p型CMOS晶体管330的栅极以及p型CMOS晶体管325的第一端子耦合。P检测放大器360的第二端子接收数字线D，并且还与晶体管325的栅极以及晶体管330的第一端子耦合。将晶体管325的第二端子以及晶体管330的第二端子与晶体管320的第一端子耦合。晶体管320的栅极接收Fire P控制信号。在N检测放大器350接收到Fire N控制信号之后的预定时间，P检测放大器360接收所述Fire P控制信号。
转向图5，依照本发明的示范性实施例，示出了描述图1和2示意图的操作流程的流程图。在此示范性处理流程中，假定PCRAM单元的以下参数：(i)用于在可编程导体存储器元件116中生成枝状物、将其转换为高阻状态，并且由此写逻辑“1”的擦除电压是0.25V；(ii)擦除电流大约10μA；(iii)编程电压(将“1”元件写为逻辑“0”)是-0.25V；(iv)编程电流大约10μA；(v)对应于逻辑“0”的电阻大约10KΩ；并且(vi)对应于逻辑“1”的电阻是大于大约10MΩ的任一值。显而易见的是，在不脱离本发明的精神和范围的情况下，可以选择替换参数以及操作电压和电阻用于PCRAM单元。
所述过程从处理阶段500开始。在阶段502，检测放大器102寻找两个线D和D*，其中D和D*是来自于不同存储器阵列100，165的相应列线108，106。为了描述，我们假设Vdd近似2.5V电压。所述单元极板118附带有预定电压(例如Vdd/2或者近似1.25V)，其既可以是一个无论什么时候激活，都存在的条件，也可以通过存储操作对其进行转换。依照此示出的实施例，在处理阶段506导通Vdd/2电压。在阶段508，线D、D*108，106经由预充电电路175预充电到预定电压(例如，Vdd＝近似2.5V)，然后通过均衡电路176均衡。
在阶段510，通过将来自于列线解码器的预定电压施加到该行线122，所选择的行线122得以激发。在此例子中，如此处将描述的那样，预定电压已选择为大约2.25V。为了读取存储器单元120的内容，或者更具体地说，为了读取存储器单元120的可编程导体存储器元件116的电阻，在元件116两端必须施加大约0.2V的电压。这意味着必须将近似2.25V的电压施加到行线122。施加到行线122的近似2.25V的电压导通晶体管114。由于晶体管114的阈值电压大约0.8V，那么点A处存在近似1.45V的电压，同时单元极板118处存在近似1.25V的电压，由此产生了近似0.2V的电压差，这是需要的读取电压，如图5的阶段512所示。
应该提及的是，当存取晶体管114导通时，因为存储器单元的列线108和行线122之间的内在寄生电容(例如图1的138)，数字线D 108的电压实际上增加了大约0.1V(高达大约2.6V)。这样在数字线D、与正被读取的单元120相关联的列线108、D*106、基准数字线之间产生了大约0.1V的电压差。所述寄生电容138可以依照存储器单元的结构功能而改变，或者还可以提供制造的电容器形式的其他电容，将其接入电路，并且在读操作期间将其与数字线D 108相连接；因此，依照本发明的示范性实施例，当激发行线122时，所增加的电压量可以由所述存储器体系结构来控制。在阶段514描述了D 108处的电压升高。
通过检测放大器102可以看出，可以采取其他方式来增大D和D*之间的电压差。例如，在不感兴趣的存储器阵列中(例如165)可以采用虚(dummy)行线124，如此使得虚行线124始终保持在、并且预充电为Vdd(近似2.5V)。那么，当激发所要求的行线122时，并且所要求的数字线D 108提上高到近似2.6V电压时，由于寄生电容138，虚行线124关闭，由此，数字互补线D*106处的电压因虚行线124和列线106之间的寄生电容138而降至大约2.4V。最后结果是：当D 108开始放电时，D 108和D*106相差大约至少0.2V电压，如下所述。
仍参见图5，在阶段516，感兴趣的数字线D 108经由可编程导体存储器元件的电阻开始从大约2.6V放电至大约1.25V电压，这是单元极板118的电压。放电操作的时间持续越长，可编程导体存储器元件116的电阻水平越大。在所选择的行线122被激发之后的预定时间(例如15-30ns)，在阶段510，通过控制信号Fire N启动N检测放大器350，在阶段518，比较D 108上的电压和D*106线上的电压。在阶段520，确定可编程导体元件116具有的是低电阻水平还是高电阻水平。
例如，在阶段522，确定D 108上的初始电压是否已经在预定时间帧内(例如15-30ns)放电到低于D*106上的电压。返回参考图3，分别将D*106和D 108处的电压值送到晶体管305和300的栅极。如果在预定时间t2，数字线D 108处的电压高于数字互补线D*106处的电压，那么将D*106接地，而D保持悬空并且被认为是具有高电阻水平(例如逻辑高)，阶段524。
应该注意的是，行线122在存取晶体管114导通之后被关断。然而，这样做将使可编程导体存储器元件116被重写。正如可编程导体存储器元件116的正常状态那样，因为在逻辑高的每个读操作之后未必要求重写，并且重复的不必要的重写可能随时间的延长而导致元件116损坏，故而当读取逻辑高时，可能需要这样做。
仍参见阶段522，如果在预定时间t2，D 108处的电压低于D*106处的电压，那么将D 108接地，而在阶段526，将D 108认为是具有低电阻水平(例如逻辑低)。
在阶段528，在启动N检测放大器350之后的预定时间(例如1-5ns))，通过控制信号Fire P启动P检测放大器360。如果在阶段524识别出高电阻水平(即，D 108是逻辑高)，那么晶体管330是导通的，而晶体管325是关断的，并且线D 108处的电压被升高到大约Vdd，阶段530。
如果在阶段524识别出低电阻水平(即，D 108是逻辑低)，那么晶体管330是关断的，而晶体管325是导通的，在阶段532线D*106处的电压维持在大约Vdd的水平上。
在阶段534，行线122电压被升高到大约Vdd。如果所述可编程导体存储器元件116包含低阻状态，那么如上所述，对于重写低阻状态来说，不必将行线122的电压提升到大约Vdd；然而，仍然升高行线122，以便于重写高阻状态。也就是说，如果所述可编程导体存储器元件116包含高阻状态，那么升高行线122的电压到大约Vdd，可以将点A处的电压设置为近似1.7V，由此将可编程导体存储器元件116两端的电势差置于大约0.45V，这是足以进行重写的电压。
图6结合图5的描述示出了用于寻找高电阻水平的处理流程的时序图。例如，最初将D 108和D*106都预充电到大约Vdd。在时间t1，行线122激发并且导通晶体管114。因为行线122和列线108之间的寄生电容138使得D 108处的电压增加了大约0.1V，从而达到2.6V。然后，线D 108从大约2.6V电压开始放电达15-30ns之久，而线D*106维持在近似Vdd的水平上。在时间t2，启动N检测放大器350并且比较线D 108处的电压与线D*106的电压。如果D 108处测量的电压大于D*106的电压，那么识别出高电阻水平，如结合图5所描述的那样。此外，在时间t2，将线D*106强制接地(0V)。在时间t3，启动P检测放大器360，并且将线D升高到Vdd，并且读作逻辑高。在时间t4，行线122的电压从近似2.25升高到近似Vdd，由此能够重写可编程导体元件116的内容。
图7结合图5的描述示出了用于寻找低电阻水平的处理流程的时序图。例如，最初将线D 108和D*106都预充电为大约Vdd。在时间t1，行线122激发并且导通晶体管114。因为寄生电容138使得D 108处的电压增加了大约0.1V，从而达到2.6V。然后，D 108从大约2.6V开始放电达15-30ns之久，而线D*106维持在大约Vdd的水平上。在时间t2，启动N检测放大器350并且比较线D 108处的电压与线D*106的电压。如果D 108处测量到的电压低于D*106的电压，那么识别出低电阻水平，如结合图5所描述的那样。此外，在时间t2，将线D 108强迫接地(0V)。在时间t3，启动P检测放大器360，并且线D保留在0V并读作逻辑低，而线D*维持在大约Vdd的水平上。在时间t4，行线122的电压从大约2.25升高到大约Vdd。如上所述，尽管对于在可编程导体存储器元件116中重写入低电阻水平来说这是不必要的，但是这样做可以重写用于存储高电阻水平的其他存储器单元。
图8如结合图1-7所描述的那样示出了包含PCRAM半导体存储器的处理器系统800的框图。例如，结合图1-7描述的PCRAM存储器阵列100，165可以是随机存取存储器(RAM)808的一部分，其可以被构造为包含一个或多个存储器件的插入式模块，所述一个或多个存储器件，具有如上所述的PCBAM结构。基于处理器的系统800可以是计算机系统或者任意其他处理器系统。所述系统800包括中央处理单元(CPU)802，例如，微处理器，其经由总线820与软盘驱动器812、CD ROM驱动器814和RAM 808通信。必须指出，总线820可以是在基于处理器的系统中通用的一系列总线和桥接器，但是仅仅是出于说明方便，将总线820以单条总线的形式示出。输入/输出(I/O)设备(例如监视器)804、806也可以与总线820相连，但是在本发明的实施中并不需要。基于处理器的系统800还包括只读存储器(ROM)800，其也可以用于存储软件程序。
虽然图8的框图只示出了一个CPU 802，但是也可以将图8的系统配置为并行处理器机来执行并行处理。正如本领域所公知的，并行处理器机可以归类为单指令/多数据(SIMD)或者多指令/多数据(MIMD)形式，所述单指令/多数据指的是所有处理器同时执行同一指令，多指令/多数据指的是每个处理器执行不同的指令。
本发明提供了PCBAM单元120以及用于读取存储器单元120的内容的方法。所述存储器单元120包括与存取晶体管114的第一端子串联的可编程导体存储器元件116。所述可编程导体存储器元件116的另一端与单元极板118耦合，所述单元极板118可以扩展到多个可编程导体存储器元件116上。存取晶体管114的第二端子与列线108耦合，其可以是所期望的数字线(D)。存取晶体管114的栅极与存储器单元120的行线122耦合。将第一预定电压电势(例如Vdd)施加到数字线D 108以及相邻存储器阵列165的基准数字线D*106。将第二预定电压电势施加到单元极板118。当以第三预定电压电势(例如近似2.25V)激发所要求的存储器单元120的行线122时，存取晶体管114导通，并且导电，而数字线D 108与此同时进行放电达预定时间周期(例如15-30ns)，利用检测放大器102比较线D 108和线D*106，以便确定可编程导体元件116包含高电阻水平还是低电阻水平。然后，正读取的存储器单元120通过将电线D 108和线D*106以及行线122的电压预充电为大约Vdd来为下一个周期做准备，以便当存储器单元实际上具有高电阻水平时，所述高电阻水平可以被重写入存储器单元120。如果所述存储器单元120具有低电阻水平，那么提高线D 108和D*106以及行线122的电压电势对于存储器单元120的电阻来说没有影响。
当已经知晓结合优选的实施例详细说明本发明时，不难理解，本发明不局限于所公开的实施例。更确切的说，本发明可以被修改以合并迄今未描述的许多变化、变换、置换或等效结构，但是这些都不脱离本发明的精神和范围。例如，虽然已经结合特殊的电压电平描述了本发明，但是显而易见的是，不同于此处所述的电压电平也可以实现相同的结果。此外，虽然已经结合N型和p型CMOS晶体管描述了本发明，但是显而易见的是，其余的CMOS晶体管也可以代替使用。此外，虽然已经结合存储器单元120的特殊极性描述了本发明，但是所述极性可以反相，以产生不同的电压电平来施加到晶体管114、单元极板118、数字线D 108和数字互补线D*106。据此，本发明不由上述描述或者附图限制，而是只由所附权利要求的范围来限定。

Claims (29)

1.一种用于读取可变电阻存储器单元的方法，所述方法包括以下步骤：
将所述单元的单元极板的电压设置为第一预定电压，其中所述单元的电阻元件的第一部分与其耦合；
将所述单元的存取晶体管的第一端子和参考导体充电为第二预定电压，其中所述第一端子与所述单元的列线耦合，其中所述晶体管的第二端子与所述电阻元件的第二部分耦合，并且其中所述第一端子和所述基准导体与比较器的各个输入端耦合；
将所述存取晶体管的栅极充电为第三预定电压，以便读取所述单元，其中所述栅极与所述单元的行线耦合；
经由所述电阻元件将所述第一端子从第二预定电压放电；并且
在所述放电动作开始之后的预定时间段，比较所述第一端子处的电压与所述第二预定电压，以便确定所述单元的逻辑状态。
2.如权利要求1所述的方法，其中所述第二预定电压大于所述第一预定电压。
3.如权利要求1所述的方法，其中所述放电动作包括：将所述第一端子从第四预定电压开始放电，所述第四预定电压与所述第二预定电压稍有不同，所述第四预定电压是由与所述列线相关联的寄生电容引起的。
4.如权利要求1所述的方法，还包括在已经读取了所述存储单元之后，将所述第三预定电压改变为足以对所述存储单元重写入电阻水平的水平。
5.如权利要求4所述的方法，其中所述改变动作包括将所述第三预定电压提高到所述第二预定电压。
6.如权利要求5所述的方法，其中所述改变动作包括将所述第三预定电压电平提高到大约Vdd。
7.如权利要求4所述的方法，还包括对所述存储单元重写入所述高电阻水平。
8.如权利要求1所述的方法，其中所述设置动作包括将所述单元极板的所述电压设置为大约Vdd。
9.如权利要求8所述的方法，其中所述设置动作包括将所述单元极板的电压设置为大约Vdd/2。
10.如权利要求1所述的方法，其中所述对晶体管的第一端子进行充电的动作包括将所述第一端子和所述基准导体充电为大约Vdd。
11.如权利要求1所述的方法，其中所述对栅极充电的动作包括将所述栅极充电为足以读取所述电阻元件的值，但是要低于能够对所述单元进行编程的值。
12.如权利要求11所述的方法，其中所述对栅极进行充电的动作包括将所述栅极充电为所述第一和所述第二预定电压之间的电压电平。
13.如权利要求3所述的方法，其中所述对所述第一端子放电的动作包括将所述第一端子从大约Vdd加上附加电压开始放电。
14.如权利要求13所述的方法，其中所述对所述第一端子放电的动作包括将所述第一端子从大约Vdd加上大约0.1V开始放电。
15.如权利要求1所述的方法，其中所述比较动作包括在所述放电动作已经开始大约15-30ns之后，将第一端子处的电压与所述第二预定电压进行比较。
16.如权利要求1所述的方法，还包括确定所述存储单元具有逻辑高状态。
17.如权利要求1所述的方法，还包括确定所述存储单元具有逻辑低状态。
18.一种用于检测可变电阻存储器单元的存储值的方法，所述方法包括以下步骤：
将与所述单元的存取晶体管的第一端子耦合的数字线预充电为第一预定电压；
将所述单元的单元极板充电为第二预定电压，所述第二预定电压是0V和所述第一预定电压之间的值；并且
向与所述存取晶体管的栅极耦合的行线施加第三预定电压，如此使得所述可变电阻存储器单元两端产生的电压足以读取所述单元的逻辑状态，但是不足以对所述单元进行编程。
19.一种半导体存储器，包括：
可变电阻存储器元件；
列线；
行线；
用于向所述可变电阻存储器元件的第一端子施加第一电压的导体；
用于响应施加到所述行线的栅极电压，有选择地耦合所述列线与所述可变电阻存储器元件的另一端子的晶体管；
与所述列线和基准导体耦合的检测放大器；以及
预充电电路，用于在向所述行线施加栅极电压之前、将所述列线以及参考导体预充电为预定电压，
所述检测放大器比较所述列线以及参考线上的电压，以便在将所述栅极电压施加到所述行线之后、确定所述可变电阻存储器元件的电阻值。
20.如权利要求19所述的存储器，其中所述第一电压是0V和大约Vdd之间的电压。
21.如权利要求19所述的存储器，其中所述可变电阻存储器元件包括具有第一和第二电极的硫族化物玻璃。
22.如权利要求21所述的存储器，其中所述硫族化物玻璃含有Ge、Se和Ag成分。
23.如权利要求19所述的存储器，其中所述栅极电压足以读取所述存储器元件，但是不足以编程所述存储器元件。
24.如权利要求19所述的存储器，还包括与所述列线相关联的可变寄生电容，所述可变寄生电容令所述列线被充电为高于预定电压的电压电平，所述预定电压由所述预充电电路响应于施加到行线的栅极电压而提供。
25.如权利要求24所述的存储器，其中所述可变寄生电容令所述列线被充电为高于所述预定电压大约0.1V，所述预定电压由所述预充电电路提供。
26.如权利要求19所述的存储器，其中所述检测放大器包括：
N检测放大器；以及
与所述N检测放大器耦合的P检测放大器，其中所述N检测放大器和P检测放大器比较所述列线和所述基准导体处的电压值。
27.如权利要求19所述的存储器，其中所述参考导体与不同于与所述存储器元件关联的存储器阵列的存储器阵列相关联。
28.如权利要求19所述的存储器，还包括与所述基准导体相关联的虚行线，所述虚行线通常被激发到虚行线电压，并且当将所述栅极电压被施加到所述行线时，所述虚行线失效，由此所述参考导体处的所述预定电压因为与所述虚行线相关联的列线处的寄生电容而减小。
29.一种处理器系统，包括：
处理器；以及
与所述处理器耦合的半导体存储器，所述半导体存储器包括：
可变电阻存储器元件；
列线；
行线；
用于向所述可变电阻存储器元件的第一端子施加第一电压的导体；
用于响应施加到所述行线的栅极电压，有选择地耦合所述列线与所述可变电阻存储器元件的另一端子的晶体管；
检测放大器，与所述列线以及基准导体耦合；以及
预充电电路，用于在向所述行线施加栅极电压之前、将所述列线以及参考导体预充电为预定电压，所述检测放大器比较所述列线以及参考线上的电压，以便在将所述栅极电压施加到所述行线之后、确定所述可变电阻存储器元件的电阻值。
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CN1647210A (zh) 2005-07-27
ATE396482T1 (de) 2008-06-15
JP2005518627A (ja) 2005-06-23
US20030156463A1 (en) 2003-08-21
US20050018493A1 (en) 2005-01-27
EP1476877B1 (en) 2008-05-21

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