CN101267004B - Storage unit structure and its operation method - Google Patents
Storage unit structure and its operation method Download PDFInfo
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- CN101267004B CN101267004B CN2007100867793A CN200710086779A CN101267004B CN 101267004 B CN101267004 B CN 101267004B CN 2007100867793 A CN2007100867793 A CN 2007100867793A CN 200710086779 A CN200710086779 A CN 200710086779A CN 101267004 B CN101267004 B CN 101267004B
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Abstract
A storing unit comprises a silicon substrate, a capture layer on the silicon substrate, a first doping region and a second doping region respectively disposed in the silicon substrate sandwiching the capture layer, a grid on the capture layer, a first oxidation layer between the grid and the capture layer, a high interface capture density (high-Dit) material layer between the silicon substrate and the capture layer, and a second oxidation layer between the high interface capture density material layer and the capture layer, wherein the interface capture density between the high interface capture density material layer and the silicon substrate ranges in 10<SUP>11</SUP>10<SUP>13</SUP>cm<SUP>-2</SUP>eV<SUP>-1</SUP>.
Description
Technical field
The invention relates to a kind of memory cell structure (memory unit structure), and particularly relevant for a kind of memory cell structure and method of operation thereof that after operation, reduces swing deterioration (swing degradation) impact (impact).
Background technology
In the present non-voltile memory product, has the actions such as depositing in, read, erase that to carry out repeatedly data, and can in a memory cell, carry out the SONOS memory cell of two bits (2bit) operations, become extensively a kind of memory subassembly of employing of personal computer and electronic equipment institute.
Generally speaking, the SONOS memory cell is to adopt one deck electric charge capture layer (charge trappinglayer) to replace the polysilicon floating gate (floating gate) of known flash memory, and one deck silicon oxide layer is respectively arranged usually up and down at this electric charge capture layer, to form the nesting structural embedded control (stacked structure) that is constituted by silicon oxide/silicon nitride/silicon oxide (ONO) layer.Moreover, in the substrate of ONO layer both sides, have source electrode and drain electrode, on the ONO layer, then be provided with grid.
Because the bottom oxide (bottom oxide) in the ONO layer of traditional SONOS memory cell is directly to utilize thermal oxidation method to be formed on the substrate, so be that density (interface trap density is caught at low interface between the substrate of itself and silicon, Dit), about 10
10Cm
-2EV
-1But being found, this Dit value can increase with the cycle-index of memory cell and increase gradually, as shown in Figure 1, wherein no matter be initial erase state (initial erase state) still initial sequencing state (initial program state) all the slope differences heteropole with circulate 10,000 times erased status and sequencing state is big.Thereby cause swinging usefulness (swing performance) reduction, and then influence operation, circulation persistence (cycleendurance) and the data retentivity (retention) of memory cell.
Summary of the invention
The object of the present invention is to provide a kind of memory cell structure, but the swing usefulness after the stable circulation operation.
Another purpose of the present invention is to provide a kind of method of operation of memory cell, can do the high persistent operation of two bits to memory cell.
For achieving the above object, the invention provides memory cell structure, comprising:
One silicon substrate;
One catches layer, is positioned on this silicon substrate;
One first doped region and one second doped region lay respectively in this silicon substrate of these seizure layer both sides;
One grid is positioned on this seizure layer;
One first oxide layer is caught between the layer at this grid and this;
Density (high-Dit) material layer is caught at one high interface, catches between the layer at this silicon substrate and this, and wherein (interfacetrap density is Dit) 10 for the interface seizure density between this high interface seizure density material layer and this silicon substrate
11～10
13Cm
-2EV
-1Between; And
One second oxide layer is caught the density material layer at this high interface and this is caught between the layer.
Described memory cell structure, wherein, the interface seizure density that catch between density material layer and this silicon substrate at this high interface is 10
12Cm
-2EV
-1
Described memory cell structure, wherein, the thickness of density material layer is caught between 10～70 dusts in this high interface.
Described memory cell structure, wherein, the material that the density material layer is caught at this high interface comprises silicon nitride.
Described memory cell structure, wherein, the material that the density material layer is caught at this high interface comprises hafnium oxide (HfO
2), zirconium dioxide (ZrO
2), nitrogen zirconia (ZrO
xN
y), nitrogen hafnium oxide (HfO
xN
y), hafnium silicate (HfSi
xO
y), zirconium silicate (ZrSi
xO
y), nitrogen-oxygen-silicon hafnium (HfSi
xO
yN
z), alundum (Al (Al
2O
3), titanium dioxide (TiO
2), tantalum pentoxide (Ta
2O
5), lanthanum sesquioxide (La
2O
3), plutonium oxide (CeO
2), bismuth silicate (Bi
4Si
2O
12), tungsten oxide (WO
3), yittrium oxide (Y
2O
3), lanthanum aluminate (LaAlO
3), barium strontium (Ba
1-xSr
xTiO
3), barium titanate (BaTiO
3), lead zirconates (PbZrO
3), tantalic acid scandium lead (PbSczTa
1-zO
3, be called for short PST), zinc niobate lead (PbZn
zNb
1-zO
3, be called for short PZN), lead zirconate titanate (PbZrO
3-PbTiO
3, be called for short PZT) or niobic acid magnesium lead (PbMgzNb
1-zO
3, be called for short PMN).
Described memory cell structure, wherein, this silicon substrate is a p type silicon substrate, and this first doped region and this second doped region are n type doped regions.
The method of operation of memory cell provided by the invention, be applicable to a memory cell, this memory cell has a silicon substrate, be positioned at one on this silicon substrate and catch layer, lay respectively at interior one first doped region and one second doped region of this silicon substrate of these seizure layer both sides, be positioned at the grid on this seizure layer, one first oxide layer between this grid and this seizure layer, catch that the density material layer is caught at a high interface between the layer and catch density material layer at this high interface and catch one second oxide layer between the layer at this silicon substrate and this with this, wherein should high interface seizure density material layer and this silicon substrate between interface seizure density (Dit) 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one first positive voltage, apply one second positive voltage, and to make this first doped region be 0 volt in this second doped region, to utilize channel hot electron (channel hot electron, CHE) bit of one of this memory cell of mode sequencing side;
When erasing this memory cell, on this grid, apply one first negative voltage, apply one the 3rd positive voltage in this second doped region, and to make this first doped region be 0 volt, to utilize valence band to valence band hot hole (band-to-band tunneling hot hole, BTBTHH) the mode bit of this side of this memory cell of erasing.
The method of operation of described memory cell, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
The method of operation of described memory cell, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
The method of operation of described memory cell, wherein, this first positive voltage is greater than this second positive voltage.
The present invention also provides a kind of method of operation of memory cell, be applicable to a memory cell, this memory cell has a silicon substrate, be positioned at one on this silicon substrate and catch layer, lay respectively at interior one first doped region and one second doped region of this silicon substrate of these seizure layer both sides, be positioned at the grid on this seizure layer, one first oxide layer between this grid and this seizure layer, catch that the density material layer is caught at a high interface between the layer and catch density material layer at this high interface and catch one second oxide layer between the layer at this silicon substrate and this with this, wherein should high interface seizure density material layer and this silicon substrate between interface seizure density (Dit) 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one the 4th positive voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (Fowler-Nordheim, FN) this memory cell of mode sequencing;
When erasing this memory cell, on this grid, apply one second negative voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (FN) mode this memory cell of erasing.
The method of operation of described memory cell, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
The method of operation of described memory cell, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
The present invention provides a kind of memory cell structure again, comprising:
One silicon substrate;
One catches layer, is positioned on this silicon substrate;
One first doped region and one second doped region lay respectively in this silicon substrate of these seizure layer both sides;
One grid is positioned on this seizure layer;
One first dielectric layer is caught between the layer at this grid and this; And
One second dielectric layer is caught between the layer at this silicon substrate and this, and wherein density (Dit) is caught 10 in the interface between this second dielectric layer and this silicon substrate
11～10
13Cm
-2EV
-1Between.
Described memory cell structure, wherein, it is 10 that density is caught at the interface between this second dielectric layer and this silicon substrate
12Cm
-2EV
-1
Described memory cell structure, wherein, this second dielectric layer comprises oxide layer.
Described memory cell structure, wherein, this silicon substrate is a p type silicon substrate, and this first doped region and this second doped region are n type doped regions.
Described memory cell structure, wherein, this first dielectric layer comprises oxide layer.
The present invention provides a kind of method of operation of memory cell again, be applicable to a memory cell, this memory cell has a silicon substrate, catching layer, lay respectively at one first doped region and one second doped region in this silicon substrates of this seizures layer both sides on this silicon substrate, at the grid on this seizures layer, at one first dielectric layer between this grid and this seizure layer and at one second dielectric layer between this silicon substrate and this seizure layer, wherein the seizure density of the interface between this second dielectric layer and this silicon substrate (Dit) is 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one first positive voltage, apply one second positive voltage, and to make this first doped region be 0 volt, to utilize the bit of this memory cell one side of channel hot electron (CHE) mode sequencing in this second doped region;
When erasing this memory cell, on this grid, apply one first negative voltage, apply one the 3rd positive voltage in this second doped region, and to make this first doped region be 0 volt, to utilize valence band to the erase bit of this side of this memory cell of valence band hot hole (BTBTHH) mode.
The method of operation of described memory cell, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
The method of operation of described memory cell, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
The method of operation of described memory cell, wherein, this first positive voltage is greater than this second positive voltage.
The present invention provides a kind of method of operation of memory cell again, be applicable to a memory cell, this memory cell has a silicon substrate, catching layer, lay respectively at one first doped region and one second doped region in this silicon substrates of this seizures layer both sides on this silicon substrate, at the grid on this seizures layer, at one first dielectric layer between this grid and this seizure layer and at one second dielectric layer between this silicon substrate and this seizure layer, wherein the seizure density of the interface between this second dielectric layer and this silicon substrate (Dit) is 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one the 4th positive voltage, and to make this first doped region and this second doped region be 0 volt, to utilize this memory cell of Fu Le-Nuo Dehan (FN) mode sequencing;
When erasing this memory cell, on this grid, apply one second negative voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (FN) mode this memory cell of erasing.
The method of operation of described memory cell, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
The method of operation of described memory cell, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
In other words, the present invention proposes a kind of memory cell, comprise a silicon substrate, the one deck that is positioned on the silicon substrate is caught layer, lay respectively at first and second doped region in the silicon substrate of catching layer both sides, be positioned at a grid of catching on the layer, one deck first oxide layer between grid and seizure layer, density (interface trap density is caught at a floor height interface between silicon substrate and seizure layer, Dit) material layer and one deck second oxide layer between high interface seizure density material layer and seizure layer, density is caught 10 in the interface that catch between density material layer and the silicon substrate at wherein high interface
11～10
13Cm
-2EV
-1Between.
In one embodiment of this invention, the interface seizure density between above-mentioned high interface seizure density material layer and the silicon substrate is 10
12Cm
-2EV
-1
In one embodiment of this invention, the thickness of density material layer is caught between 10～70 dusts in above-mentioned high interface.
In one embodiment of this invention, the material of above-mentioned high interface seizure density material layer comprises silicon nitride.
In one embodiment of this invention, the material of above-mentioned high interface seizure density material layer comprises hafnium oxide (HfO
2), zirconium dioxide (ZrO
2), nitrogen zirconia (ZrO
xN
y), nitrogen hafnium oxide (HfO
xN
y), hafnium silicate (HfSi
xO
y), zirconium silicate (ZrSi
xO
y), nitrogen-oxygen-silicon hafnium (HfSi
xO
yN
z), alundum (Al (Al
2O
3), titanium dioxide (TiO
2), tantalum pentoxide (Ta
2O
5), lanthanum sesquioxide (La
2O
3), plutonium oxide (CeO
2), bismuth silicate (Bi
4Si
2O
12), tungsten oxide (WO
3), yittrium oxide (Y
2O
3), lanthanum aluminate (LaAlO
3), barium strontium (Ba
1-xSr
xTiO
3), barium titanate (BaTiO
3), lead zirconates (PbZrO
3), tantalic acid scandium lead (PbSc
zTa
1-zO
3, be called for short PST), zinc niobate lead (PbZn
zNb
1-zO
3, be called for short PZN), lead zirconate titanate (PbZrO
3-PbTiO
3, be called for short PZT) or niobic acid magnesium lead (PbMg
zNb
1-zO
3, be called for short PMN).
In one embodiment of this invention, above-mentioned silicon substrate is a p type silicon substrate, and first doped region and second doped region are n type doped regions.
The present invention proposes a kind of method of operation of memory cell again, is applicable to that it is 10 that density (Dit) is caught at above-mentioned interface of catching at high interface between density material layer and the silicon substrate
11～10
13Cm
-2EV
-1Between memory cell.Its method of operation comprises: during the sequencing memory cell, on grid, apply first positive voltage, apply second positive voltage, and to make first doped region be 0 volt in second doped region, to utilize channel hot electron (channel hot electron, CHE) bit of mode sequencing memory cell one side; When erasing memory cell, on grid, apply one first negative voltage, apply one the 3rd positive voltage in second doped region, and to make first doped region be 0 volt, to utilize valence band to valence band hot hole (band-to-bandtunneling hot hole, BTBTHH) the mode bit of this side of memory cell of erasing.
The present invention reintroduces a kind of method of operation of memory cell, is applicable to that it is 10 that density (Dit) is caught at above-mentioned interface of catching at high interface between density material layer and the silicon substrate
11～10
13Cm
-2EV
-1Between memory cell.Its method of operation comprises: during the sequencing memory cell, apply one the 4th positive voltage on grid, and to make first doped region and second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (Fowler-Nordheim, FN) the described memory cell of mode sequencing; And when erasing memory cell, on grid, apply one second negative voltage, and to make first doped region and second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (FN) mode described memory cell of erasing.
In one embodiment of this invention, above-mentioned first doped region is that source electrode, second doped region are drain electrodes.
In one embodiment of this invention, above-mentioned first doped region is that drain electrode, second doped region are source electrodes.
In one embodiment of this invention, above-mentioned first positive voltage is greater than second positive voltage.
The present invention proposes a kind of memory cell in addition, comprise a silicon substrate, the one deck on silicon substrate catch layer, lay respectively at first and second doped region in the silicon substrate of catching layer both sides, catch a grid on the layer, between grid should seizures layer one deck first dielectric layer and at one deck second dielectric layer between silicon substrate and the seizure layer, wherein the seizure density of the interface between second dielectric layer and the silicon substrate (Dit) is 10
11～10
13Cm
-2EV
-1Between.
In another embodiment of the present invention, it is 10 that density is caught at the interface between said second dielectric layer and the silicon substrate
12Cm
-2EV
-1
In another embodiment of the present invention, said second dielectric layer comprises oxide layer.
In another embodiment of the present invention, above-mentioned silicon substrate is a p type silicon substrate, and first doped region and second doped region are n type doped regions.
In another embodiment of the present invention, said first dielectric layer comprises oxide layer.
The present invention proposes a kind of method of operation of memory cell again, is applicable to that it is 10 that density (Dit) is caught at above-mentioned interface between second dielectric layer and silicon substrate
11～10
13Cm
-2EV
-1Between memory cell.Its method of operation comprises: during the sequencing memory cell, apply first positive voltage on grid, apply second positive voltage in second doped region, and to make first doped region be 0 volt, to utilize the bit of channel hot electron (CHE) mode sequencing memory cell one side; When erasing memory cell, on grid, apply one first negative voltage, apply one the 3rd positive voltage, and to make first doped region be 0 volt, to utilize valence band the erase bit of this side of memory cell of valence band hot hole (BTBTHH) mode in second doped region.
The present invention reintroduces a kind of method of operation of memory cell, is applicable to that it is 10 that density (Dit) is caught at above-mentioned interface between second dielectric layer and silicon substrate
11～10
13Cm
-2EV
-1Between memory cell.Its method of operation comprises: during the sequencing memory cell, apply one the 4th positive voltage on grid, and to make first doped region and second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (FN) mode sequencing memory cell; And when erasing memory cell, on grid, apply one second negative voltage, and to make first doped region and second doped region be 0 volt, to utilize Fu Le-Nuo Dehan (FN) mode memory cell of erasing.
In another embodiment of the present invention, above-mentioned first doped region is that source electrode, second doped region are drain electrodes.
In another embodiment of the present invention, above-mentioned first doped region is that drain electrode, second doped region are source electrodes.
In another embodiment of the present invention, above-mentioned first positive voltage is greater than second positive voltage.
The present invention is because be made as the interface between silicon substrate and its upper strata 10
11～10
13Cm
-2EV
-1Between high interface catch density (Dit), so after the operational cycle number of times increases gradually, its swing usefulness can maintain certain degree, therefore operation, circulation persistence and the data retentivity of memory cell all can maintain in the permissible scope as much as possible, and are unlikely to make storage-unit-failure.
Memory cell structure provided by the invention: but the swing usefulness after the stable circulation operation; To be reduced in the impact of operation back swing deterioration.
The method of operation of memory cell provided by the invention: can do the high persistent operation of two bits to memory cell; To solve the problem of start voltage (Vt) loss; Can keep the data retentivity of memory cell; Operate and can improve the circulation persistence of memory cell to carry out single bit.
Description of drawings
Fig. 1 is known SONOS memory cell and an I-V curve chart through one ten thousand circulation after initial in operation.
Fig. 2 A is the generalized section of a kind of memory cell structure according to first embodiment of the invention when carrying out two bit programming operations.
Fig. 2 B is the generalized section of Fig. 2 A memory cell structure when carrying out two bit erase operation for use.
Fig. 2 C is the generalized section of Fig. 2 A memory cell structure when carrying out single bit programming operations.
Fig. 2 D is the generalized section of Fig. 2 A memory cell structure when carrying out single bit erase operation for use.
Fig. 3 A is that Fig. 2 A memory cell structure carries out the initial and I-V curve chart after 15K time, 30K time circulation of two bit programming operations.
Fig. 3 B is that Fig. 2 A memory cell structure carries out the initial and I-V curve chart after 15K time, 30K time circulation of two bit erase operation for use.
Fig. 4 A is the generalized section of a kind of memory cell structure according to second embodiment of the invention when carrying out two bit programming operations.
Fig. 4 B is the generalized section of Fig. 4 A memory cell structure when carrying out two bit erase operation for use.
Fig. 4 C is the generalized section of Fig. 4 A memory cell structure when carrying out single bit programming operations.
Fig. 4 D is the generalized section of Fig. 4 A memory cell structure when carrying out single bit erase operation for use.
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, especially exemplified by preferred embodiment, and conjunction with figs. elaborates.
Below will embodiments of the invention be described more fully with accompanying drawing.But, the present invention still can multiple multi-form the practice, and it should be interpreted as be limited to the embodiment that specification is stated.And, in the accompanying drawings, for the purpose of clear and definite, may lavish praise on oneself the size in each layer and zone, and not illustrate according to actual ratio.
In addition, employed term only is for describing following Application Example in specification, and is not to be used for limiting the present invention.As for terms such as employed in the specification " first ", " second ", just be used for a certain zone, layer or part and another zone, layer or part are distinguished, do not represent its formation order or operating sequence.
First embodiment
Fig. 2 A is the generalized section of a kind of memory cell structure according to first embodiment of the invention when carrying out two bit programming operations.
Please refer to Fig. 2 A, the memory cell of first embodiment comprises that a silicon substrate 200, one deck are caught layer 202, the first doped region 204a and density (high-Dit) material layer 210 and one deck second oxide layer 212 are caught in the second doped region 204b, grid 206, one deck first oxide layer 208, a floor height interface.In the present embodiment, silicon substrate 200 is p type silicon substrates, and the first doped region 204a and the second doped region 204b are n type doped regions.Catch layer 202 and be on the silicon substrate 200, first and second doped region 204a and 204b then be that silicon substrate 200, the grid 206 of catching layer 202 both sides caught on the layer 202 respectively, 208 of first oxide layers grid 206 with catch between layers 202.Catching density material layer 210 as for high interface is between silicon substrate 200 and seizure layer 202,212 of second oxide layers are caught density material layer 210 and are caught between layers 202 at high interface, density is caught at interface between wherein high interface seizure density material layer 210 and the silicon substrate 200, and (interface trap density is Dit) 10
11～10
13Cm
-2EV
-1Between; Be preferably 10
12Cm
-2EV
-1In addition, high interface is caught the thickness of density material layer 210 such as is between 10～70 dusts; Be preferably 30 dusts.The material of catching density material layer 210 as for high interface can be silicon nitride; Or, hafnium oxide (HfO
2), zirconium dioxide (ZrO
2), nitrogen zirconia (ZrO
xN
y), nitrogen hafnium oxide (HfO
xN
y), hafnium silicate (HfSi
xO
y), zirconium silicate (ZrSi
xO
y), nitrogen-oxygen-silicon hafnium (HfSi
xO
yN
z), alundum (Al (Al
2O
3), titanium dioxide (TiO
2), tantalum pentoxide (Ta
2O
5), lanthanum sesquioxide (La
2O
3), plutonium oxide (CeO
2), bismuth silicate (Bi
4Si
2O
12), tungsten oxide (WO
3), yittrium oxide (Y
2O
3), lanthanum aluminate (LaAlO
3), barium strontium (Ba
1-xSr
xTiO
3), barium titanate (BaTiO
3), lead zirconates (PbZrO
3), tantalic acid scandium lead (PbSc
zTa
1-zO
3, be called for short PST), zinc niobate lead (PbZn
zNb
1-zO
3, be called for short PZN), lead zirconate titanate (PbZrO
3-PbTiO
3, be called for short PZT) and niobic acid magnesium lead (PbMg
zNb
1-zO
3, be called for short PMN) one of them.
Please continue A with reference to Fig. 2, when the operation the present embodiment memory cell carried out as the two bit sequencing of Fig. 2 A, can on grid 206, apply first positive voltage (as the Vg=10 volt), apply second positive voltage (as the Vd=5 volt) in the second doped region 204b (can be used as drain electrode this moment), and make the first doped region 204a (can be used as source electrode this moment) be the Vs=0 volt, to utilize channel hot electron (channel hotelectron, CHE) mode sequencing memory cell one side bit (being the drain side bit), and silicon substrate 200 is a ground connection usually, so its V
Sub=0 volt.On the other hand, the above-mentioned first doped region 204a also can be used as drain electrode, the second doped region 204b can be used as source electrode; In other words, when applying first positive voltage on the grid, adding second positive voltage, drain electrode when being 0 volt at source electrode, programmable cell source side bit.And above-mentioned first positive voltage is greater than second positive voltage.
Fig. 2 B then is the generalized section of Fig. 2 A memory cell structure when carrying out two bit erase operation for use.
Please refer to Fig. 2 B, when the memory cell of present embodiment is carried out two bit erase operation for use, need on grid 206, apply one first negative voltage (as the Vg=-10 volt), apply one the 3rd positive voltage (as the Vd=5 volt) in the second doped region 204b, and to make the first doped region 204a be 0 volt (as Vs=0 volt), to utilize valence band to valence band hot hole (band-to-band tunneling hot hole, BTBTHH) the mode memory cell one side bit (being the drain side bit) of erasing.
Except the operation of two bits, the memory cell structure of first embodiment also can utilize the mode of single bit operation to carry out, shown in Fig. 2 C and Fig. 2 D.
Fig. 2 C is the generalized section of Fig. 2 A memory cell structure when carrying out single bit programming operations.Please refer to Fig. 2 C, when the present embodiment memory cell being carried out single bit programming operations, need be to apply on the grid 206 one the 4th positive voltage (as the Vg=20 volt), and to make the first doped region 204a and the second doped region 204b be 0 volt (Vs=0 volt, Vd=0 volt), to utilize Fu Le-Nuo Dehan (Fowler-Nordheim, FN) the described memory cell of mode sequencing.
Fig. 2 D is the generalized section of Fig. 2 A memory cell structure when carrying out single bit erase operation for use.Please refer to Fig. 2 D, when the present embodiment memory cell being carried out single bit erase operation for use, need on grid 204, to apply one second negative voltage (as the Vg=-20 volt), and to make the first doped region 204a and the second doped region 204b be 0 volt (Vs=0 volt, Vd=0 volt), to utilize Fu Le-Nuo Dehan (FN) mode described memory cell of erasing.
For the memory cell that confirms first embodiment can please refer to Fig. 3 A and Fig. 3 B repeatedly still keeping stable swing usefulness after the circulation really.
Fig. 3 A is that Fig. 2 A memory cell structure carries out that two bit programming operations are initial and inferior through 15,000 (15K), the I-V curve chart after the inferior circulation of 30,000 (30K).Fig. 3 B is that Fig. 2 B memory cell structure carries out the initial and I-V curve chart after 15K time, 30K time circulation of two bit erase operation for use.From Fig. 3 A and Fig. 3 B as can be known, no matter it is be the still initial erase state (initial erase state) among Fig. 3 B of initial sequencing state (initial program state) among Fig. 3 A, all few with the slope differences of 30K time sequencing state and erased status with circulation 15K time.In other words, the memory cell of first embodiment can still be kept stable swing usefulness after the multi-pass operation circulation.
Second embodiment
Fig. 4 A is the generalized section of a kind of memory cell structure according to second embodiment of the invention when carrying out two bit programming operations.
Please refer to Fig. 4 A, the memory cell of second embodiment comprises a silicon substrate 400, one deck seizure layer 402, first doped region 404a and the second doped region 404b, grid 406, one deck first dielectric layer 408 and one deck second dielectric layer 410.In the present embodiment, silicon substrate 400 is p type silicon substrates, and the first doped region 404a and the second doped region 404b are n type doped regions, and wherein said first dielectric layer 408 for example is an oxide layer.As for, then having the interface 412 that (high interface trap is abbreviated as HIT) characteristic is caught at high interface between second dielectric layer 410 and the silicon substrate 400, density (Dit) is caught 10 in its interface
11～10
13Cm
-2EV
-1Between; Be preferably 10
12Cm
-2EV
-1In addition, second dielectric layer 410 can be an oxide layer; For instance, can select to use the poorest thermal oxidation processing procedure or behind the thermal oxidation processing procedure, make the Dit at interface 412 between 10 in implantation mode (implantation)
11～10
13Cm
-2EV
-1Between.And in the present embodiment, above-mentioned silicon substrate 400 for example is a p type silicon substrate, and the first doped region 404a and the second doped region 404b for example are n type doped regions.
Please continue A with reference to Fig. 4, when the present embodiment memory cell is carried out the operation of two bit sequencing, can on grid 406, apply first positive voltage (as the Vg=10 volt), apply second positive voltage (as the Vd=5 volt) in the second doped region 404b (can be used as drain electrode this moment), and make the first doped region 404a (can be used as source electrode this moment) be the Vs=0 volt, utilizing the bit (being the drain side bit) of channel hot electron (CHE) mode sequencing memory cell one side, and V usually
Sub=0 volt.Moreover also interchangeable do drain electrode of the above-mentioned first doped region 104a and the second doped region 104b and source electrode are described and be not limited to second embodiment; In other words, when applying first positive voltage on the grid, adding second positive voltage, drain electrode when being 0 volt at source electrode, programmable cell source side bit.And generally speaking above-mentioned first positive voltage is greater than second positive voltage.
Fig. 4 B then is the generalized section of Fig. 4 A memory cell structure when carrying out two bit erase operation for use.
Please refer to Fig. 4 B, when the present embodiment memory cell is carried out two bit erase operation for use, need on grid 406, to apply first negative voltage (as the Vg=-10 volt), apply the 3rd positive voltage (as the Vd=5 volt) in the second doped region 404b, and to make the first doped region 404a be 0 volt (as Vs=0 volt), to utilize valence band to valence band hot hole (BTBTHH) the mode memory cell one side bit (being the drain side bit) of erasing.
About the memory cell structure of second embodiment, still can utilize the mode of single bit operation to carry out sequencing and erase, shown in Fig. 4 C and Fig. 4 D, it is respectively the generalized section of Fig. 4 A memory cell structure when carrying out single bit sequencing and erase operation for use.
Please refer to Fig. 4 C, on grid 406, apply one the 4th positive voltage (as the Vg=20 volt), and to make the first doped region 404a and the second doped region 404b be 0 volt (Vs=0 volt, Vd=0 volt), can utilize the described memory cell of Fu Le-Nuo Dehan (FN) mode sequencing.
Please refer to Fig. 4 D, on grid 404, apply one second negative voltage (as the Vg=-20 volt), and to make the first doped region 404a and the second doped region 404b be 0 volt (Vs=0 volt, Vd=0 volt), can utilize Fu Le-Nuo Dehan (FN) mode described memory cell of erasing.
In sum, the present invention is owing to be made as 10 with the interface between silicon substrate and the upper strata thereof
11～10
13Cm
-2EV
-1High interface catch density (Dit), so after the memory cell operation number of times increased gradually, the variation of Dit value was little.Therefore, the swing usefulness of memory cell can obviously not reduce, so the operation of memory cell, circulation persistence and data retentivity can be improved after cycle-index increases gradually.
Though the present invention describes as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art are not breaking away from the spirit and scope of the invention, and when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the content that the claim scope defined.
Claims (23)
1. memory cell structure comprises:
One silicon substrate;
One catches layer, is positioned on this silicon substrate;
One first doped region and one second doped region lay respectively in this silicon substrate of these seizure layer both sides;
One grid is positioned on this seizure layer;
One first oxide layer is caught between the layer at this grid and this;
The density material layer is caught at one high interface, catches between the layer at this silicon substrate and this, and wherein density is caught 10 in the interface between this high interface seizure density material layer and this silicon substrate
11～10
13Cm
-2EV
-1Between, and the material that the density material layer is caught at this high interface comprises silicon nitride, hafnium oxide, zirconium dioxide, nitrogen zirconia, nitrogen hafnium oxide, hafnium silicate, zirconium silicate, nitrogen-oxygen-silicon hafnium, alundum (Al, titanium dioxide, tantalum pentoxide, lanthanum sesquioxide, plutonium oxide, bismuth silicate, tungsten oxide, yittrium oxide, lanthanum aluminate, barium strontium, barium titanate, lead zirconates, tantalic acid scandium lead, zinc niobate lead, lead zirconate titanate or niobic acid magnesium lead; And
One second oxide layer is caught the density material layer at this high interface and this is caught between the layer.
2. memory cell structure as claimed in claim 1, wherein, the interface seizure density that catch between density material layer and this silicon substrate at this high interface is 10
12Cm
-2EV
-1
3. memory cell structure as claimed in claim 1, wherein, the thickness of density material layer is caught between 10～70 dusts in this high interface.
4. memory cell structure as claimed in claim 1, wherein, this silicon substrate is a p type silicon substrate, and this first doped region and this second doped region are n type doped regions.
5. the method for operation of a memory cell, be applicable to a memory cell, this memory cell has a silicon substrate, be positioned at one on this silicon substrate and catch layer, lay respectively at interior one first doped region and one second doped region of this silicon substrate of these seizure layer both sides, be positioned at the grid on this seizure layer, one first oxide layer between this grid and this seizure layer, catch that the density material layer is caught at a high interface between the layer and catch density material layer at this high interface and catch one second oxide layer between the layer at this silicon substrate and this with this, wherein should high interface seizure density material layer and this silicon substrate between interface seizure density 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one first positive voltage, apply one second positive voltage, and to make this first doped region be 0 volt, to utilize the bit of this memory cell one side of channel hot electron mode sequencing in this second doped region;
When erasing this memory cell, on this grid, apply one first negative voltage, apply one the 3rd positive voltage, and to make this first doped region be 0 volt, to utilize valence band the erase bit of this this side of memory cell of valence band hot hole mode in this second doped region.
6. the method for operation of memory cell as claimed in claim 5, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
7. the method for operation of memory cell as claimed in claim 5, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
8. the method for operation of memory cell as claimed in claim 5, wherein, this first positive voltage is greater than this second positive voltage.
9. the method for operation of a memory cell, be applicable to a memory cell, this memory cell has a silicon substrate, be positioned at one on this silicon substrate and catch layer, lay respectively at interior one first doped region and one second doped region of this silicon substrate of these seizure layer both sides, be positioned at the grid on this seizure layer, one first oxide layer between this grid and this seizure layer, catch that the density material layer is caught at a high interface between the layer and catch density material layer at this high interface and catch one second oxide layer between the layer at this silicon substrate and this with this, wherein should high interface seizure density material layer and this silicon substrate between interface seizure density 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one the 4th positive voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-this memory cell of Nuo De Chinese prescription formula sequencing;
When erasing this memory cell, on this grid, apply one second negative voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-Nuo De Chinese prescription formula this memory cell of erasing.
10. the method for operation of memory cell as claimed in claim 9, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
11. the method for operation of memory cell as claimed in claim 9, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
12. a memory cell structure comprises:
One silicon substrate;
One catches layer, is positioned on this silicon substrate;
One first doped region and one second doped region lay respectively in this silicon substrate of these seizure layer both sides;
One grid is positioned on this seizure layer;
One first dielectric layer is caught between the layer at this grid and this; And
One second dielectric layer is caught between the layer at this silicon substrate and this, and wherein density is caught 10 in the interface between this second dielectric layer and this silicon substrate
11～10
13Cm
-2EV
-1Between.
13. memory cell structure as claimed in claim 12, wherein, it is 10 that density is caught at the interface between this second dielectric layer and this silicon substrate
12Cm
-2EV
-1
14. memory cell structure as claimed in claim 12, wherein, this second dielectric layer comprises oxide layer.
15. memory cell structure as claimed in claim 12, wherein, this silicon substrate is a p type silicon substrate, and this first doped region and this second doped region are n type doped regions.
16. memory cell structure as claimed in claim 12, wherein, this first dielectric layer comprises oxide layer.
17. the method for operation of a memory cell, be applicable to a memory cell, this memory cell has a silicon substrate, catching layer, lay respectively at one first doped region and one second doped region in this silicon substrates of this seizures layer both sides on this silicon substrate, at the grid on this seizures layer, at one first dielectric layer between this grid and this seizure layer and at one second dielectric layer between this silicon substrate and this seizure layer, wherein the seizure of the interface between this second dielectric layer and this silicon substrate density is 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one first positive voltage, apply one second positive voltage, and to make this first doped region be 0 volt, to utilize the bit of this memory cell one side of channel hot electron mode sequencing in this second doped region;
When erasing this memory cell, on this grid, apply one first negative voltage, apply one the 3rd positive voltage, and to make this first doped region be 0 volt, to utilize valence band the erase bit of this side of this memory cell of valence band hot hole mode in this second doped region.
18. the method for operation of memory cell as claimed in claim 17, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
19. the method for operation of memory cell as claimed in claim 17, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
20. the method for operation of memory cell as claimed in claim 17, wherein, this first positive voltage is greater than this second positive voltage.
21. the method for operation of a memory cell, be applicable to a memory cell, this memory cell has a silicon substrate, catching layer, lay respectively at one first doped region and one second doped region in this silicon substrates of this seizures layer both sides on this silicon substrate, at the grid on this seizures layer, at one first dielectric layer between this grid and this seizure layer and at one second dielectric layer between this silicon substrate and this seizure layer, wherein the seizure of the interface between this second dielectric layer and this silicon substrate density is 10
11～10
13Cm
-2EV
-1Between, this method of operation comprises:
During this memory cell of sequencing, on this grid, apply one the 4th positive voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-this memory cell of Nuo De Chinese prescription formula sequencing;
When erasing this memory cell, on this grid, apply one second negative voltage, and to make this first doped region and this second doped region be 0 volt, to utilize Fu Le-Nuo De Chinese prescription formula this memory cell of erasing.
22. the method for operation of memory cell as claimed in claim 21, wherein, this first doped region is a source electrode, and this second doped region is drain electrode.
23. the method for operation of memory cell as claimed in claim 21, wherein, this first doped region is drain electrode, and this second doped region is a source electrode.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917214A (en) * | 1997-01-06 | 1999-06-29 | Mosel Vitelic, Inc. | Split gate flash memory unit |
| CN1577806A (en) * | 2003-06-27 | 2005-02-09 | 旺宏电子股份有限公司 | Non-volatile memory cell, and method for forming same |
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- 2007-03-15 CN CN2007100867793A patent/CN101267004B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5917214A (en) * | 1997-01-06 | 1999-06-29 | Mosel Vitelic, Inc. | Split gate flash memory unit |
| CN1577806A (en) * | 2003-06-27 | 2005-02-09 | 旺宏电子股份有限公司 | Non-volatile memory cell, and method for forming same |
Non-Patent Citations (1)
| Title |
|---|
| JP昭58-209165A 1983.12.06 |
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