CN101271886A - 高密度电路模块 - Google Patents

高密度电路模块 Download PDF

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CN101271886A
CN101271886A CNA2008100096140A CN200810009614A CN101271886A CN 101271886 A CN101271886 A CN 101271886A CN A2008100096140 A CNA2008100096140 A CN A2008100096140A CN 200810009614 A CN200810009614 A CN 200810009614A CN 101271886 A CN101271886 A CN 101271886A
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csp
flex
module
conductive layer
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CN100594608C (zh
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J·W·卡迪
J·维德尔
D·L·罗珀
J·D·维尔利
J·道登
J·布奇勒
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Printing Technology Corp
Data LLC
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Entorian Technologies Inc
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Abstract

本发明涉及高密度电路模块。本发明把芯片尺寸封装集成电路(CPS)层叠为保存板表面积的模块中。在按照本发明优选实施例设计的两高度CSP层叠或模块(10)中，层叠了成对的CSP(12、14)，一个CSP(12)设置在另一个(14)之上。两个CSP用一对挠性电路结构(30、32)连接。成对挠性电路结构(30、32)中的每个关于模块(10)下CSP(14)的各个相对侧端(20、22)局部卷绕。弯曲电路对(30、32)把上和下CSP(12、14)连接并在模块(10)和例如印刷布线板(PWB)的应用环境之间提供热和电通路的连接通路。在多种结构和提供用于高密度存储或高容量计算的模块中的CSP组合中应用本发明，产生了良好的效果。

Description

高密度电路模块
本申请是申请日为2002年10月25日、申请号为02826187.9、发明名称为“高密度电路模块”的发明专利申请的分案申请。
技术领域
本发明涉及集结集成电路，尤其涉及以芯片尺寸封装的层叠集成电路。
背景技术
许多技术用于层叠封装集成电路。某些方法需要特定的封装，而另一些技术层叠常规封装。在某些层叠中，封装集成电路的引线用于建立叠层，而在另一些系统中，例如轨道之类的附加结构提供封装之间所有或部分互连。在再一些技术中，使用带特定特性的挠性导体选择性互连封装集成电路。
近十年期间所应用的主要封装结构在塑料外包层中密封集成电路(IC)，塑料外包层一般具有矩形结构。包封的集成电路通过从塑料包封的端部周边发出的引线与应用环境连接。这种“引线封装”成为用于层叠封装集成电路技术最广为应用的组成部分。
引线封装在电子学中起到了重要的作用，而最小化电子部件和组件的努力推动了保持电路板表面积技术的发展。因为引线封装具有从封装周边发出的引线，故引线封装占据了不仅是最小量的电路板表面积。因此，引线封装的替代品最近获得了市场份额。
一般把一类替代封装定义为“芯片尺寸封装”或CSP。CSP一般指通过横过封装主表面排列的触点组(常常具体化为“焊点”或“焊球”)提供与集成电路连接的封装。替代从封装周边侧发出的引线，触点被放置在主表面上并一般从封装的平坦底表面发出。
CSP的目的是占据尽可能小的面积，优选大约为密封IC的面积。因此，CSP引线或触点一般没有延伸超过封装的轮廓周边。在封装侧缺少“引线”反映了多数层叠技术，设计这些层叠技术用于不适用于CSP层叠的引线封装。
CSP能够减小许多应用的尺寸和重量参数。例如，用于闪存和SRAM的微球栅阵列(μBGA)和带上或用于SRAM或EEPROM的格栅层压CSP上的引线接合已经应用在许多应用中。CSP是广泛的种类，包括从邻近芯片尺寸到管芯尺寸封装的各种封装，例如最近在提出的用于DSBGA的JEDEC标准95-1中介绍的管芯尺寸球栅阵列(DSBGA)。为了满足增加存储容量同时减少成本和形状因子的不断要求，最近发展了在CSP技术中集结集成电路的CSP技术。例如，Sharp、Hitachi、Mitsubishi和Intel最近从事被称为S-CSP技术规范用于闪存和SRAM的支持。但是，那些S-CSP技术规范介绍了在单个芯片尺寸封装内层叠多个管芯，并未提供用于层叠芯片尺寸封装的技术。在单个封装内层叠集成电路要求特定的技术，包括封装内部的更改和显著的花费，可能会有一连串弱点。
存在几种公知的技术用于层叠在芯片尺寸技术中铰链的封装。本发明的受让人发展了前述系统用于在节省空间拓扑中集结μBGA封装。本发明的受让人持有在RAMBUS环境中DIMM上层叠BGA封装的系统。
在本发明受让人享有的US专利No.6205654B1中，介绍了层叠球栅阵列封装的系统，其应用引线载体使可连接点延伸出封装。其它公知技术增加了层叠BGA封装IC的结构。另一些公知技术在DIMM上集结CSP，封装成角放置。这些技术提供了替换方式，然而需要附加成本和复杂性的拓扑。
Forthun的US专利No.6262895B1(“Forthun专利”)意图公开一种层叠芯片尺寸封装IC的技术。Forthun专利公开了表现为局部关于CSP卷绕的弯曲电路(flex circuit)的“封装”。弯曲电路被定义为在弯曲(flex)的上和下表面上具有焊盘阵列。
Forthun“封装”的弯曲电路具有在其上表面上的焊盘阵列和关于其下表面中心设置的焊盘阵列。在弯曲下表面上存在自中心下表面焊盘阵列相对面上的第三和第四阵列。为了产生Forthun封装，CSP接触位于弯曲电路上表面上的焊盘阵列。如Forthun专利中介绍的那样，在CSP下表面上的触点挤过在上表面焊盘中的“裂缝”并穿过弯曲从下表面阵列的焊盘突出，并由此从封装的底表面突出。由此，CSP触点用作封装的触点。弯曲的边关于CSP局部卷绕以邻近地把第三和第四焊盘阵列放置在CSP的上部主表面上从第三和第四焊盘阵列的组合产生用于连接另一个这样封装的第五焊盘阵列。由此，如Forthun公开中介绍的那样，用所述封装产生的CSP层叠模块将表现为在模块中关于每个CSP卷绕的弯曲电路。
层叠CSP的前述公知方法明显具有许多缺陷，包括复杂的结构布置和热或高频性能问题。一般密切关注芯片尺寸封装的可靠性。在这种可靠性评估期间，CSP器件常常表现出温度循环性能问题。一般在PWB上或其它平台上、仅偏离PWB从CSP下表面发出的焊球或焊点阵列的高度直接安装CSP。因此，在低高度焊球阵列的短杆臂中集中了由随时间的温度梯度产生的应力。与在单个CSP中温度循环性能有关的问题在现有技术CSP层叠方案中易于出现，在现有技术中层叠从PWB或应用平台仅偏离下CSP球栅阵列的高度。
热性能也是CSP叠层中的重要特征。为了增加由组成CSP产生的热的分散，在CSP叠层或模块中下CSP和上CSP之间的热梯度应最小化。不过，现有技术对CSP层叠的方案强调公开结构中的热梯度最小化。
因此需要层叠封装在芯片尺寸技术封装中的集成电路的技术和系统，其提供在更高频表现良好而不对叠层附加额外高度的热有效、可靠结构，而用已经知道和运用的材料和方法使产品成本合理。
发明内容
本发明把芯片尺寸封装集成电路(CPS)层叠为保存PWB或其它板表面积的模块中。在各种尺寸和结构的CSP封装中使用本发明，从带稍微大于所含管芯的轨迹的一般BGA到例如如DSBGA管芯尺寸封装的较小封装，产生了良好的效果。虽然本发明经常应用于包含一个管芯的芯片尺寸封装，其还可以应用于包含多于一个集成电路管芯的芯片尺寸封装。
在按照本发明优选实施例设计的两高度CSP叠层或模块中，层叠了两个CSP，一个CSP设置在另一个之上。两个CSP与成对的弯曲电路连接。每个成对弯曲电路关于模块下CSP的各个相对侧端局部卷绕。弯曲电路对把上和下CSP连接并在模块和例如印刷布线板(PWB)的应用环境之间提供热和电通路的连接通路。
在提供用于高密度存储或高容量计算模块中的CSP的多个结构和组合中使用发明，产生了良好的效果。
附图说明
图1是按照本发明优选实施例设计的模块10的立面图。
图2是按照本发明优选实施例设计的模块10的立面图。
图3以放大图描绘了在图2中标记“A”的区域。
图4是在本发明的优选实施例中示例连接的放大详图。
图5是在本发明的优选实施例中下弯曲触点周围示例区域的放大描述。
图6描绘了在本发明的优选实施例中应用的弯曲电路的第一外表面层。
图7描绘了在本发明的优选实施例中应用的弯曲电路的第一外表面层。
图8描绘了在本发明的优选实施例中应用的弯曲电路的第一导电层。
图9描绘了在本发明的优选实施例中应用的弯曲电路的第一导电层。
图10描绘了在本发明的优选实施例中应用的弯曲电路的中间层。
图11描绘了在本发明的优选实施例中应用的右侧弯曲电路的中间层。
图12描绘了本发明的优选实施例的弯曲电路的第二导电层。
图13描绘了本发明的优选实施例的弯曲电路的第二导电层。
图14描绘了在本发明的优选实施例中应用的弯曲电路的第二外层
图15反映了在本发明的优选实施例中应用的弯曲电路的第二外层
图16描绘了本发明的另一优选实施例。
图17说明用于DDR-II FBGA封装的JEDEC插脚输出。
图18说明在发明的另一优选实施例中模块10的插脚输出。
图19说明在发明的另一实施例中模块10的插脚输出。
图20描绘了发明优选实施例中应用的示例CSP的插脚输出。
图21描绘了在本发明的另一优选实施例中应用的弯曲电路的第二导电层。
图22描绘了在本发明的另一优选实施例中应用的弯曲电路的第二导电层。
具体实施方式
图1是按照本发明优选实施例设计的模块10的立面图。模块10包括上CSP12和下CSP14。每个CSP12和14具有上表面16和下表面18和相对侧面20和22。
本发明使用多种类型和结构的CSP封装，例如管芯尺寸的和接近芯片尺寸的以及现有技术中公知的各种球栅阵列封装。这里这些将共同公知作为芯片尺寸封装集成电路(CSP)，优选实施例将就CSP进行介绍，但是在示例图中使用的特定结构不作为限制。例如，图1和2的立面图描绘了本领域公知特定外形的CSP，应理解附图仅是示例性的。后面的附图示出本发明的实施例，其应用其它结构的CSP作为本发明可以应用的许多替换CSP结构另一个的实例。在从至少一个主表面发出可连接元件阵列技术中可用的广泛范围的CSP结构中使用本发明，产生了良好的效果。本发明有利地应用包含存储电路的CSP，而应用逻辑和计算电路产生了良好的效果，附加容量的同时不需要同量的PWB或其它板表面积消耗。
一般的CSP，例如球栅阵列(“BGA”)、微球栅阵列(“μBGA”)、和微间距球栅阵列(“FBGA”)封装具有可连接触点阵列，例如引线、焊点、焊球或以任意几种图形和间距从塑料壳的下表面18延伸的球。常常用焊球终止可连接触点的外部。图1示出沿着CSP12和14下表面18的CSP触点24。CSP触点24提供与在各个封装内的集成电路的连接。CSP触点24共同包括CSP阵列26，关于描绘的特定封装结构中的下CSP14示出了总体包括CSP阵列26的CSP阵列261和262。
在图1中，示出了弯曲电路(“弯曲”、“弯曲电路”或“挠性电路结构”)30和32局部关于下CSP14卷绕，弯曲30在下CSP14的侧面20局部卷绕，弯曲32关于下CSP14的侧面22局部卷绕。侧面20和22可以充当面，或者如果CSP特别薄，可以充当端部。可以使用任何具有多层内层连接能力的挠性或合适的基板作为本发明的弯曲电路。整个弯曲电路可以是挠性的，或者本领域技术人员将认识到，可以应用在某个区域挠性制造的PCB结构(以在下CSP14周围具有整合性在沿着CSP表面用于可平面性的其它区域具有刚性)作为本发明弯曲电路的替代。例如，可以应用公知为硬柔的结构。
部分弯曲电路30和32通过粘结剂34固定到下CSP14的上表面16，粘结剂34作为带粘结剂示出，可以是液体粘结剂或者可以放置在封装上分立位置中。粘结剂34优选为导热的。在模块10的装配中使用包括熔剂的粘结剂，产生了良好的效果。层34还可以是导热介质以促进模块10CSP之间的热流。
弯曲电路30和32可以是具有至少两层导电层的多层挠性电路结构。导电层优选是例如合金110的金属。将看到使用多层导电层提供了优点，本领域技术人员将认识到在模块10上建立分布电容来减小噪声或特别是在高频能够降低信号完整性的跳动效应。图1的模块10具有共同确定为模块阵列38的模块触点36。
图2示出按照发明优选实施例设计的模块10。图2说明使用在优选实施例中设置的底层填料40以辅助建立模块10结构区域保形。通过底层填料40提高模块的可平面性。底层填料40优选为导热的。在另一实施例中，如参考标号41所示可以放置热散布机或者热介质。在图2中可以识别在弯曲电路30和32导电层之一处的上弯曲触点42和下弯曲触点44。上弯曲触点42和下弯曲触点44是导电材料，优选为固体金属。下弯曲触点44共同为下弯曲触点阵列46。上弯曲触点42共同为上弯曲触点阵列48。在图2中仅可以识别某些上弯曲触点42和下弯曲触点44以保持图的清晰。应理解每个弯曲电路30和32具有上弯曲触点42和下弯曲触点44。下弯曲触点44应用下CSP14，上弯曲触点42应用上CSP12。图2具有标记“A”的区域，其随后在图3中以放大图示出。
图3以放大图描绘了图2中标记“A”的区域。图3说明实例CSP触点24和模块触点36之间通过下弯曲触点44的连接，从而说明从下CSP14到模块触点36的固体金属路径和由此到可连接模块的应用PWB的路径。本领域技术人员可以理解由此促进了从模块10的热转移。
继续参照图3，CSP触点24和模块触点36一起从应用平台例如PWB偏离模块10。CSP触点24和模块触点36的组合高度提供了比只有单个CSP触点24的高度长的矩臂。这提供了更长的矩臂，通过其能够分布随时间温度梯度应力(例如由温度循环代表)。
在图3示出弯曲30包括多层。弯曲30具有第一外表面50和第二外表面52。弯曲电路30至少具有在第一和第二外表面50和52内部的两层导电层。在弯曲30和32种可以多于两层导电层。在所述优选实施例中，第一导电层54和第二导电层58在第一和第二外表面50和52的内部。在第一导电层54和第二导电层58之间存在中间层56。可以存在多于一层的中间层，而优选为一层聚酰亚胺中间层。
如图3所绘并在随后附图中可以详细看出，在第二外表面52内部的第二导电层58层面处下弯曲触点44优选由金属构成。在优选实施例中，下弯曲触点44是固体金属并由例如合金110的金属合金构成。这产生了从下CSP14到应用板的固体金属通路，由此提供了用于分散在模块10中产生的热量的重要热通路。
图4是实例CSP触点24和实例模块触点36之间通过下弯曲触点44示例连接的放大详图，从而说明从下CSP14到模块触点36的固体金属通路，和由此到可连接模块10的应用PWB的通路。如图4所示，下弯曲触点44在第二导电层58处，第二导电层58分别在弯曲电路30的第一和第二外表面层50和52的内部。
图5是在优选实施例中在下弯曲触点44周围示例区域的放大描绘。在第一和第二外表面层50和52中分别开口60和62，以提供到存在于弯曲中第二导电层58层面的特定下弯曲触点44的路径。通过上CSP12的CSP触点24接触上弯曲触点42。下弯曲触点44和上弯曲触点42是在弯曲中第二导电层58层面处导电材料(优选例如合金110的金属)的特定区域。在第二导电层58中区分上弯曲触点42和下弯曲触点44，如在随后的附图中所示，并且上弯曲触点42和下弯曲触点44可以与第二导电层8的导电平面连接或者与其隔离。通过在第二导电层58处示出的界限间隙63在图5中描述了与第二导电层58区分下弯曲触点44。在上或下弯曲触点42或44不与第二导电层58完全隔离的地方，界限间隙不像例如由随后的图12中的下弯曲触点44C所示的那样完全环绕弯曲触点延伸。下CSP14的CSP触点24穿过经第一外表面层50、第一导电层54和中间层56的开口60与适当的下弯曲触点44接触。穿过第二外表面层52开口62，模块触点36穿过第二外表面层52与适当的下弯曲触点44接触。
在弯曲电路30和32中的第二导电层58层面处连接上CSP12和下CSP14的各个CSP触点24以使两个CSP的适当信号和电压触点互连。在弯曲电路30和32中第一导电层54层面处通过穿过中间层56的通孔来连接传输接地(VSS)信号的上CSP12和下CSP14的各个CSP触点24来连接个层面，随后将进一步详细说明结构。由此，连接CSP12和14。因此，当关于下CSP14放置弯曲电路30和32时，每个上和下CSP12和14的相应CSP触点24分别与上和下弯曲触点42和44接触。连接选定的上弯曲触点42和下弯曲触点44。因此，通过与下弯曲触点44接触，模块触点36与上和下CSP12和14接触。
在优选实施例中，模块触点36穿过在第二外层52中的开口62与下CSP触点44接触。在某些实施例中，如随后所示，模块10将出现具有比模块10的组成CSP触点数多的模块触点阵列38。在这个实施例中，某些模块触点36可以与下弯曲触点44接触，下弯曲触点44不与下CSP14的CSP触点24之一接触而与上CSP12的CSP触点24连接。这使得模块10表达了比组成CSP12和14表达的宽的数据路径。模块触点36还可以与下弯曲触点44接触，从而提供一位置，通过该位置当没有得到未用的CSP触点或便于该目的实现时模块中CSP不同层面可被使能。
在优选实施例中，第一导电层54用作接地平面，同时第二导电层58提供为信号传导层和电压传导层的功能。本领域技术人员将注意到，随着开口和等量互连中伴随的变化第一和第二导电层的功能可能相反
本领域技术人员将认识到，上和下CSP12和14的相应电压CSP触点24的互连提供上和下CSP间的热通路以辅助缓和模块10中的热梯度。通过经第一导电层54上和下CSP12和14的常见接地CSP触点24的连接进而促进了横过模块10的热梯度曲线的这种变平。本领域技术人员将注意到，在第一和第二导电层54和58之间存在至少一层中间层56，在优选实施例中该中间层为聚酰亚胺。在导电接地第一导电层54和信号/电压导电第二导电层58之间放置这种中间层组合提供了分布电容，该分布电容辅助缓解接地跳动现象以提高模块10的高频性能
在优选实施例中，图6描绘了弯曲30(即图1的左面)的第一外表面层50。该视图为从弯曲上从第一导电层54的透视图俯视到弯曲30。整个附图，位置标记“B”是对弯曲32以及横穿层弯曲层30的定向图。穿过第一外表面层50、第一导电层54和中间层56开口开口60。下CSP14的CSP触点24穿过第一外表面层50、第一导电层54和中间层56的开口60到达弯曲30的第二导电层58层面。在第二导电层58，下CSP14的选定的CSP触点24与选定的下弯曲触点44接触。如将参照随后的附图12所说明的那样下弯曲触点44在优选实施例中提供几种类型的连接。当装配模块10时，弯曲30的一部分将关于下CSP14的侧面20卷绕以在下CSP14的上表面16上放置端部62。
在优选实施例中，图7描绘了弯曲32(即图1的右面)的第一外表面层50。视图为从弯曲上从第一导电层54的透视图俯视到弯曲32。位置标记“B”相对图6和7的视图定向。观察图6和7可以理解每个视图的参考标记“B”放置得比同一层成对视图的另一观察任何角部彼此要近。如图7所示，穿过第一外表面层50、第一导电层54和中间层56开口60。下CSP14的CSP触点24穿过第一外表面层50、第一导电层54和中间层56的开口60到达弯曲30的第二导电层58的层面。在第二导电层58，下CSP14的选定的CSP触点24与下弯曲触点44接触。如将参照随后的附图12所说明的那样下弯曲触点44在优选实施例中提供几种类型的连接。当装配模块10时，弯曲32的一部分将关于下CSP14的侧面22卷绕以在下CSP14的上表面16上放置端部64。
图8描绘了弯曲30的第一导电层54。开口60继续弯曲30中的开孔，下CSP14的CSP触点通过该开口到达第二导电层58，由此到达在第二导电层58层面的选定的下弯曲触点44。
本领域技术人员将认识到因为弯曲30关于下CSP14的侧面20局部卷绕，在下CSP14的上表面16上设置的部分弯曲30上第一导电层54变成从上CSP12透视图的弯曲30的最下导电层。在所述实施例中，提供接地(VSS)连接的上CSP12的那些CSP触点24与第一导电层54连接。但是第一导电层54位于第二导电层58下面在下CSP14上卷绕的部分弯曲30，。因此，必须提供一些方法连接上弯曲触点42和第一导电层54，上CSP12的接地传输CSP触点24与该上弯曲触点42连接。因此，在所述优选实施例中，与上CSP12的接地传输CSP触点24接触的那些上弯曲触点42具有规定穿过中间层56到达第一导电层54路线的通孔。在图8中把那些与第一导电层54相遇的通孔的位置表示为通孔66。这些通孔可以是“焊盘上”或与其所连接的弯曲触点一致。本领域技术人员将注意到在图8中表示的通孔66和在所述优选实施例的第二导电层58的随后附图中表示的通孔66之间的匹配。在优选实施例中，在从图8到图12一致位置中的通孔66是一个通孔。为了简化视图，在附图中所绘通孔比制造实施例中直径上显示较大。本领域技术人员将认识到，可以通过通孔(在焊盘上或焊盘外)，几种公知技术例如镀膜孔或固体线或布线的任意一种而不必是字面意思上的通孔，提供设置导电层之间的连接。
在图8中还示出了焊盘外通孔74。在选定的开口60附近而不与其一致的位置在第一导电层54上设置焊盘外通孔74。与把选定上弯曲触点42和第一导电层54连接的通孔66不同，焊盘外通孔74使选定下弯曲触点44与第一导电层54连接。在上弯曲触点42附近，第二导电层58在通过上弯曲触点42(即上CSP12)与模块10连接的CSP和第一导电层54之间。因此，在接地传输上弯曲触点42和第一导电层54之间的通孔可以直接附着于选定的上弯曲触点42，接地信号通过选定的上弯曲触点42传输。相反，在下弯曲触点44附近，第一导电层54在通过下弯曲触点44(即下CSP14)与模块10连接的CSP和第二导电层58之间。因此，在接地传输下弯曲触点44和第一导电层54之间的通路通过在偏离位置所示的焊盘外通孔74偏离选定的下弯曲触点44。
图9说明弯曲32的第一导电层54。应用位置参考标记“B”相对定向图8和9。在图9中表示了开口60、通孔66和焊盘外通孔74。图9还示出了启动通孔68和70和启动轨迹72。启动通孔70使焊盘外在该优选实施例中与下CSP12(即N/C)的未用CSP触点对应的选定下弯曲触点44连接。在该位置的模块触点36把用于上CSP12的启动信号(C/S)通过选定的下弯曲触点44(其在第二导电层58的层面)传输到焊盘外启动通孔70，焊盘外启动通孔70把启动信号传输到第一导电层54由此传输到启动轨迹72。启动轨迹72进而把启动信号传输到启动通孔68，启动通孔68在用上CSP12的C/S引脚制造的触点处的第二导电层58层面通过中间层56延伸到选定的上弯曲触点42。由此，独立地启动了上和下CSP12和14。
图10描绘了弯曲30的中间层56。在中间表面56中开口示出了开口60。下CSP14的CSP触点24穿过在中间层58中的开口60到达在第二导电层58层面的下弯曲触点44。本领域技术人员将注意到，在所述优选实施例中，开口60直径上比第一外层50中它们的表现要窄。通孔66、焊盘外通孔74和启动通孔68和70穿过中间层56，在第一和第二导电层54和58层面分别连接选定导电区域。图11描绘了弯曲32的中间层56，示出了开口60、通孔66、焊盘外通孔74和穿过中间层56的启动通孔68和70。
图12描绘了本发明优选实施例的弯曲30的第二导电层58。描绘了多种类型的上弯曲触点42、各种类型的下弯曲触点44、信号轨迹76和VDD面78以及前面介绍的通孔66和焊盘外通孔74。整个附图12和13中，仅表示了示例特定特征以使附图清晰。弯曲触点44A用信号轨迹76与对应的选定上弯曲触点42A连接。为了增强附图的清晰度，在图12中仅照字面意思表示了示例的各个弯曲触点44A和42A。如所示的那样，在该优选实施例中，信号轨迹76表现通路路径，其在对应的弯曲触点42A和44A之间确定提供基本相等的信号长度。如所示的那样，轨迹76与表示为VDD面78的第二导电层58的较大表面区分离。VDD面78可以是一个或多个描绘的部分，优选为一个部分。下弯曲触点44C提供与VDD面78的连接。在优选实施例中，上弯曲触点42C和下弯曲触点44C分别使上CSP12和下CSP14与VDD面78连接。通过焊盘外通孔74与第一导电层54连接的下弯曲触点44表示为下弯曲触点44B。为了增强附图的清晰度，在图12中仅照字面意思表示了示例的各个下弯曲触点44B。通过通孔66与第一导电层54连接的上弯曲触点42表示为上弯曲触点42B。
图13描绘了本发明优选实施例右侧弯曲32的第二导电层58。描绘了各种类型的上弯曲触点42、各种类型的下弯曲触点44、信号轨迹76和VDD面78以及前面介绍的通孔66、焊盘外74和启动通孔70和68。图13说明通过轨迹76与下弯曲触点44A连接的上弯曲触点42A。VDD面78在第二导电层58的层面提供了电压面。下弯曲触点44C和上弯曲触点42C分别使下CSP14和上CSP12与VDD面78连接。用在前介绍的启动通孔70示出下弯曲触点44D。对应的上弯曲触点42D通过启动通孔70和68与下弯曲触点44D连接，启动通孔70和68通过在弯曲32第一导电层54层面的在前介绍的启动轨迹72彼此连接。
图14描绘了弯曲30的第二外层52。表示了开口62。本领域技术人员将认识到模块触点36穿过开口62与适当的下弯曲触点44接触。当弯曲30关于下CSP14的侧面20局部卷绕时，第二外层52的一部分变成自上CSP12透视图的弯曲30最上层。上CSP12的CSP触点24穿过开口64到达第二导电层58并与位于该层面的适当上弯曲触点42接触。图15反映了弯曲32的第二外层52并展现了开口64和62。模块触点36穿过开口62接触适当的下弯曲触点44。上CSP12的CSP触点24穿过开口64到达第二导电层58并与位于该层面的适当上弯曲触点42接触。
图16描绘了本发明的另一优选实施例，示出了模块10。本领域技术人员将认识到在图16中所述实施例与图12中的不同在于存在模块触点36E。模块触点36E提供了模块10数据路径的一部分并可以提供用于组成CSP不同启动的设备。在广泛数据路径供应中没有应用的模块触点36E可以提供接触点以提供启动信号来不同地启动上CSP12或下CSP14。
在广泛数据路径模块10中，组成上CSP12和下CSP14的数据路径的组合提供模块10，模块10表达为两个高模块10中组成CSP数据路径宽度两倍的模块数据路径。组合优选方法是相联系的，可以应用其它组合以组合在模块触点36和36E阵列上的CSP12和14的数据路径
作为实例，提供图17、18和19说明在本发明的替换实施例中使用添加的模块触点36E提供比在组成CSP12和14中存在的用于模块10的更宽数据路径。图17说明用于DDR-II FBGA封装的引脚输出。图18说明通过模块10的模块触点36和36E设置的引脚输出，表达了8位宽数据路径。按照本发明设计了模块10，在示例实施例中，模块10包括在定时中遵循DDR-II的上CSP12和下CSP14，其每个在数据路径中仅为4位宽。将认识到，在图18中所绘的模块10表达了8位宽数据路径。例如，图18描绘了在上CSP12(“顶”)和下CSP14(“底”)之间电源中不同的DQ引脚以聚集成8位。图19说明通过模块10的模块触点36和36E提供的引脚输出，表达了16位宽数据路径。模块10是按照本发明设计的，并且在该示例实施例中由在定时中遵循DDR-II的上CSP12和下CSP14构成，但其每个在数据路径中仅为8位。本领域技术人员将认识到宽度数据路径实施例可以应用在本领域中可得到的多种CSP的任意一种，并且这种CSP不需要为遵循DDR的。
图20说明设置为CSP并且在本发明中可用的存储电路的一般引脚输出。由编号的列和照字母顺序的行的JEDEC惯例表示各个阵列位置。未占用中心区域(例如A3-A6；B3-B6等)。在按字母数字顺序表示的位置，例如如实例CSP触点24所示的A3，存在CSP触点24。图21描绘了在发明另一实施例中弯曲30的第二金属层58，其中模块10表达了比任一组成CSP12和14所表达宽的数据路径。下弯曲触点44E不接触下CSP14的CSP触点24，而是接触模块触点36E，从而用选定模块触点36提供了用于为2n位宽的模块10的数据路径，其中CSP12和14的数据路径具有n位宽度。如图21所示，下弯曲触点44E与上弯曲触点42E连接。如在前的图14所示，开口62穿过第二外层52。在图21中示出的第二导电层58的另一个优选实施例中，在弯曲电路30的第二外层52中模块触点36和36E穿过开口62与适当的下弯曲触点44接触。
图22说明在本发明另一实施例中的弯曲32的第二金属层58，其中模块10表达了比组成CSP12和14任一个所表达要宽的数据路径。下弯曲触点44E不接触下CSP14的CSP触点24，而是接触模块触点36E，从而用选定的模块触点36提供了用于为2n位宽的模块10的数据路径，其中CSP12和14的数据路径具有n位宽度。如图22所示，下弯曲触点44E与上弯曲触点42E连接。如在前的图14所示，开口62穿过第二外层52。在图22中示出的第二导电层58的另一个优选实施例中，模块触点36和36E穿过弯曲电路32的第二外层52中的开口62与适当的下弯曲触点44接触。
特别是在图21和22所述的实施例中，模块触点36E接触弯曲触点44E和44EE。本领域技术人员将认识到，在所述实施例中下弯曲触点44E数量为八(8)，存在另一个在图21中示为参考标记44EE表示的下弯曲触点。通过模块触点36E之一接触下弯曲触点44EE以在上和下CSP之间提供不同启动。本领域技术人员将认识到下弯曲触点44E与对应的上弯曲触点42E连接。传输数据的上CSP12的CSP触点24与上弯曲触点42E接触。因此，组合上CSP12和下CSP14的数据路径在模块10上提供宽的数据路径。用图21和22所述的连接，弯曲电路30和32的下弯曲触点44E传输到模块触点36E、上CSP12的数据路径，同时其它下弯曲触点44把下CSP14的数据路径传输到模块触点36，从而提供给模块10上CSP12和下CSP14数据路径组合的模块数据路径。在图21和22所述的特定实施例中，模块10表达了16位数据路径，CSP12和CSP14每个表达了8位数据路径。
虽然详细地介绍了本发明，本发明可以体现为多种具体形式对本领域技术人员是显而易见的，并且不脱离本发明的精神和范围可以做出各种变型、替代和变更。所介绍的实施例仅是说明性的而非限制性的，因此由所附权利要求表明发明的范围。

Claims (16)

1.一种高密度电路模块，包括：
包括导电层和外层的弯曲电路，其中导电层具有区分的第一和第二弯曲触点，而外层具有模块触点开口；
具有触点的第一CSP，第一CSP的触点连接到弯曲电路的第一弯曲触点；
具有触点的第二CSP，第一CSP在第二CSP上设置，而第二CSP的触点连接到弯曲电路的第二弯曲触点；以及
模块触点组经过模块触点开口以接触第二弯曲触点。
2.权利要求1的高密度电路模块，其中，在第一和第二CSP之间有导热材料。
3.权利要求2的高密度电路模块，其中，该导热材料是一种导热粘结剂。
4.权利要求1的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点与第二弯曲触点中选定的弯曲触点连接。
5.一种高密度电路模块，包括：
包括导电层和外层的弯曲电路，该外层具有模块触点开口而该导电层具有区分的第一和第二弯曲触点，第二弯曲触点具有第一和第二组触点；
具有触点的第一CSP，第一CSP的触点连接到弯曲电路的第一弯曲触点；
具有触点的第二CSP，第一CSP在第二CSP上设置，而第二CSP的触点连接到第二弯曲触点的第一组触点；
第一组模块触点经过模块触点开口以接触第二弯曲触点的第一组触点；以及
第二组模块触点经过模块触点开口以接触第二弯曲触点的第二组触点。
6.权利要求5的高密度电路模块，其中，在第一和第二CSP之间有导热材料。
7.权利要求6的高密度电路模块，其中，该导热材料是一种导热粘结剂。
8.权利要求5的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点与第二弯曲触点中选定的弯曲触点连接。
9.一种高密度电路模块，包括：
包括第一和第二导电层的弯曲电路，在所述导电层之间存在中间层，第二导电层具有区分的第一和第二弯曲触点；
具有触点的第一CSP，第一CSP的触点连接到弯曲电路的第一弯曲触点；
具有触点的第二CSP，第一CSP在第二CSP上设置，而第二CSP的触点连接到该弯曲电路的第二弯曲触点；以及
第一组模块触点与第二弯曲触点接触。
10.权利要求9的高密度电路模块，其中，在第一和第二CSP之间有导热材料。
11.权利要求10的高密度电路模块，其中，该导热材料是一种导热粘结剂。
12.权利要求9的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点与第二弯曲触点中选定的弯曲触点连接。
13.权利要求9的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点以及第二弯曲触点中选定的弯曲触点都与第一导电层连接
14.权利要求13的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点以及第二弯曲触点中选定的弯曲触点都用通孔与第一导电层连接。
15.权利要求14的高密度电路模块，其中，第一弯曲触点中选定的弯曲触点用焊盘上通孔与第一导电层连接。
16.权利要求15的高密度电路模块，其中，第二弯曲触点中选定的弯曲触点用焊盘外通孔与第一导电层连接。
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US6576992B1 (en) 2003-06-10
US20030137048A1 (en) 2003-07-24
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