CN101276795B - Semiconductor encapsulation construction - Google Patents
Semiconductor encapsulation construction Download PDFInfo
- Publication number
- CN101276795B CN101276795B CN 200810091215 CN200810091215A CN101276795B CN 101276795 B CN101276795 B CN 101276795B CN 200810091215 CN200810091215 CN 200810091215 CN 200810091215 A CN200810091215 A CN 200810091215A CN 101276795 B CN101276795 B CN 101276795B
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- chip
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- packaging structure
- semiconductor packaging
- active radiator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor package structure, comprising a load carrier, a chip, a reinforcing member, a thermal fin and an active radiator. The chip and the reinforcing member are arranged on the load carrier. The thermal fin is arranged on the reinforcing member and comprises a perforated opening. The active radiator is arranged on the chip and located in the perforated opening. The semiconductor package structure of the invention can simultaneously comprises the active radiator and the passive radiator with the active radiator being not covered by the passive radiator, for directly discharging the heat quantity of the chip out from the semiconductor package structure via the active radiator in order to realize rapid heat dispersion.
Description
Technical field
The present invention relates to a kind of packaging structure, relate more specifically to a kind of semiconductor packaging structure, its passive type radiator can not cover active radiator, in order to the heat of chip is directly discharged outside this semiconductor packaging structure via this active radiator, and the weight of this passive type radiator can not be pressed on this chip, so can alleviate the pressure of this chip.
Background technology
Strong day by day along with lighter more complex electronic demand, the speed and the complexity of chip are relatively more and more higher.Semiconductor chip need provide and go up more pin relatively, in order to input and output signal.Ball grid array packaging structure (Ball Grid Array Package) be a kind of for wide with and the packaging structure of tool high pin number.Moreover along with the increase of component density on the semiconductor chip, the heat that it produced is also many more, and the heat that therefore effectively distributes semiconductor chip and produced is another important viewpoint.
With reference to figure 1, it shows typical flip-chip ball grid array packaging structure 10.This packaging structure 10 mainly comprises a chip 30, a substrate 40, a fin 12, a reinforcement (stiffener) 20.This chip 30 has active surperficial 32 and the back side 34, and has active surperficial 32 a plurality of projections 36 that are disposed at this chip 30.This substrate 40 is in order to carrying this chip 30, and has the projection 36 that many circuit (not shown) electrically connect this chip 30.This reinforcement 20 is adhered to the upper surface 26 of this substrate 40 by one first viscose glue 42.This fin 12 is adhered on this reinforcement 20 by one second viscose glue 44.One heat conduction material 46 is disposed between this back side 34 and this fin 10 of this chip 30, in order to the auxiliary heat that is produced when this chip 30 is operated that distributes.A plurality of soldered balls 22 are disposed at the lower surface 24 of this substrate 40.
Yet fin 12 is the passive heat radiation device, but not active radiator.In other words, this fin 12 is the passive heat radiations of nature, but not by intake to force active heat removal.Though this active radiator needs intake, the radiating efficiency of this active radiator is much larger than the radiating efficiency of passive heat radiation device.
The applying date is No. the 093138692nd, the TaiWan, China number of patent application on December 14th, 2004, and its applicant and this case are same applicant: Riyeguang Semiconductor Manufacturing Co., Ltd.With reference to figure 2, this patent application case discloses a kind of semiconductor packaging structure 100, and it comprises a carrier 110, a chip 120 and a thermoelectric cooling module 130.This chip 120 is disposed on this carrier 110, and is electrically connected at this carrier 110 by projection 180.This thermoelectric cooling module 130 is disposed on this chip 120, and is electrically connected at this carrier 110 by projection 190.This semiconductor packaging structure 100 comprises a packing colloid 140 in addition, in order to this chip 120 and this thermoelectric cooling module 130 are fixed on this carrier 110.A plurality of soldered balls 160 are disposed on this carrier 110.
This thermoelectric cooling module 130 has first and second surface 132,134.When these thermoelectric cooling module 130 energisings, the temperature of this first surface 132 can be lower than the temperature of this second surface 134.In other words, during these thermoelectric cooling module 130 intakes, this first surface 132 is the lower heat-absorbent surface of temperature, and this second surface 134 is the higher radiating surface of temperature.Because the first surface 132 of this thermoelectric cooling module 130 is contacted with this chip 120, so the heat that this thermoelectric cooling module 130 can be produced this chip 120 is sent to this second surface 134 from this first surface 132, to reach the effect of quick heat radiating.This semiconductor packaging structure 100 comprises a passive heat radiation device 150 in addition, and its covering and contact this thermoelectric cooling module 130 is in order to discharge the heat of the second surface 134 of this thermoelectric cooling module 130 outside this semiconductor packaging structure 100.
Yet, this thermoelectric cooling module 130 is covered by this passive heat radiation device 150, therefore the heat of the second surface 134 of this thermoelectric cooling module 130 can't directly be discharged outside this semiconductor packaging structure 100, but discharges outside this semiconductor packaging structure 100 indirectly via this passive heat radiation device 150.Moreover the weight of this passive heat radiation device 150 is pressed on this chip 120, so will cause the pressure of this chip 120.
Therefore, just having to provide a kind of semiconductor packaging structure, can solve aforesaid problem.
Summary of the invention
A purpose of the present invention is to provide a kind of semiconductor packaging structure, can comprise this active radiator and this passive heat radiation device simultaneously, and this active radiator is not covered by this passive heat radiation device.
Another object of the present invention is to provide a kind of semiconductor packaging structure, the weight of its passive heat radiation device can not be pressed on this chip.
For reaching above-mentioned purpose, the invention provides a kind of semiconductor packaging structure, comprise a carrier, a chip, a reinforcement, a fin and an active radiator.This chip configuration is on this carrier.This reinforcement is disposed on this carrier.This passive heat radiation device is disposed on this reinforcement, and comprises one and run through opening.This active radiator is disposed on this chip, and is positioned at this and runs through opening.This fin is the passive heat radiation device.
Semiconductor packaging structure of the present invention can comprise this active radiator and this passive heat radiation device simultaneously, this active radiator is not covered by this passive heat radiation device, in order to the heat of this chip is directly discharged outside this semiconductor packaging structure via this active radiator, to reach the effect of quick heat radiating.
The invention provides another kind of semiconductor packaging structure, comprise a radiating fin, one second heat-conducting interface material and one the 3rd heat-conducting interface material.
The weight of the passive heat radiation device of semiconductor packaging structure of the present invention (such as fin or radiating fin) can not be pressed on this chip, so can alleviate the pressure of this chip.In addition, during this passive heat radiation device pressurized, the pressure of this passive heat radiation device can not be passed to this chip.
In order to allow above-mentioned and other purposes of the present invention, feature and the advantage can be more obvious, hereinafter will cooperate appended diagram, be described in detail below.
Description of drawings
Fig. 1 is the generalized section of the flip-chip ball grid array packaging structure of prior art.
Fig. 2 is the generalized section of the semiconductor packaging structure of prior art.
Fig. 3 a and Fig. 3 b are the overlooking and generalized section of semiconductor packaging structure of the first embodiment of the present invention.
Fig. 4 is the generalized section of the semiconductor packaging structure of another embodiment of the present invention, and it shows the manufacturing that is formed in one of fin and this reinforcement.
Fig. 5 is the generalized section of the semiconductor packaging structure of the second embodiment of the present invention.
Fig. 6 is the generalized section of the semiconductor packaging structure of the third embodiment of the present invention.
Description of reference numerals
10 packaging structures, 12 fin
20 stiffeners, 22 soldered balls
24 lower surfaces, 26 upper surfaces
30 chips, 32 active surfaces
34 back sides, 36 projections
40 substrates, 42 first viscose glues
44 second viscose glues, 46 heat conduction materials
100 packaging structures, 110 carriers
120 chips, 130 thermoelectric cooling modules
132 surperficial 134 surfaces
140 packing colloids, 150 passive heat radiation devices
160 soldered balls, 180 projections
190 projections, 200 packaging structures
211 bottom surfaces, 212 fin
213 end faces 214 run through opening
220 stiffeners, 222 soldered balls
224 lower surfaces, 226 upper surfaces
230 chips, 232 active surfaces
234 back sides, 233 bottom surfaces
235 end faces, 236 projections
240 carriers, 242 first viscose glues
244 second viscose glues, 246 heat-conducting interface material
250 active radiators, 251 leads
300 packaging structures, 360 radiating fins
362 heat-conducting interface material, 364 heat-conducting interface material
400 packaging structures, 435 viscose glues
436 bonding wires, 451 leads
The D distance
Embodiment
With reference to figure 3a and Fig. 3 b, it shows the semiconductor packaging structure 200 of the first embodiment of the present invention.This semiconductor packaging structure 200 comprises a carrier 240, a chip 230, a reinforcement 220, a fin 212 and an active radiator 250.Active surperficial 232 of this chip 230 is disposed at the upper surface 226 of this carrier 240 (such as substrate or circuit substrate).One conducting element, such as a plurality of projections 236 be positioned at this active surperficial 232.This carrier 240 has many circuit (not shown) to be electrically connected at active surperficial 232 of this chip 230 by those projections 236.A plurality of soldered balls 222 are disposed at the lower surface 224 of this substrate 240.
This reinforcement 220 is disposed on this carrier 240.In the present embodiment, this reinforcement 220 can be adhered on this carrier 240 by one first viscose glue 242.This reinforcement 220 is around this chip 230.This fin 212 has an end face 213 and a bottom surface 211, and this end face 213 is with respect to this bottom surface 211.This fin 212 is disposed on this reinforcement 220, can be adhered on this reinforcement 220 by one second viscose glue 244 such as the bottom surface 211 of this fin 212.This first viscose glue 242 and this second viscose glue 244 can be the material with thermal conductivity and stickiness.The heat that this chip 230 is produced is sent to this fin 212 via this carrier 240, this first viscose glue 242, this reinforcement 220 and this second viscose glue 244.This fin 212 is a kind of passive heat radiation device, is the passive heat radiation of nature.In another embodiment, this fin 212 and this reinforcement 220 manufacturing (as shown in Figure 4) that is formed in one.This reinforcement 220 becomes the part of this fin 212, and is fixed on this carrier 240 by adhesion or welding procedure.
This active radiator 250 is disposed on the back side 234 of this chip 230, and be positioned at this fin 212 run through opening 214.One first heat-conducting interface material (thermal interface material) 246 is disposed between this active radiator 250 and this chip 230, in order to this active radiator 250 is fixed on this chip 230.This first heat-conducting interface material 246 can have the material of thermal conductivity and viscosity.
This active radiator 250 is forced initiatively with these chip 230 heat radiations by intake.This active radiator 250 can be a thermoelectric cooling module (thermo-electric cooler).It is made that this thermoelectric cooling module can be thermoelectric materials such as N type semiconductor or P type semiconductor.In the present embodiment, the thermoelectric cooling module of this active radiator 250 can be electrically connected at this carrier 240 (shown in Fig. 3 b) by lead 251, in order to intake to this thermoelectric cooling module.This thermoelectric cooling module has bottom surface and end face 233,235.When this thermoelectric cooling module energising, the temperature of this bottom surface 233 can be lower than the temperature of this end face 235.In other words, during this thermoelectric cooling module intake, this bottom surface 233 is the lower heat-absorbent surface of temperature, and this end face 235 is the higher radiating surface of temperature.Because the bottom surface 233 of this thermoelectric cooling module is contacted with this chip 230, therefore this thermoelectric cooling module heat that this chip 230 can be produced is sent to this end face 235 from this bottom surface 233, in order to the heat of the end face 235 of this thermoelectric cooling module is directly discharged outside this semiconductor packaging structure 200.
Moreover the end face 213 of this fin 212 is higher than the end face 235 of this active radiator 250, that is has a preset distance D between the end face 235 of the end face 213 of this fin 212 and this active radiator 250.Owing to have this preset distance D between the end face 213 of this fin 212 and the end face 235 of this active radiator 250, during therefore as if these fin 212 pressurizeds, then the pressure of this fin 212 is to be passed to this carrier 240, and can not be passed to this active radiator 250, and then can not be passed to this chip 230.
Semiconductor packaging structure of the present invention can comprise this active radiator and this passive heat radiation device simultaneously, this active radiator is not covered by this passive heat radiation device, in order to the heat at the back side of this chip is directly discharged outside this semiconductor packaging structure via this active radiator, to reach the effect of quick heat radiating.In addition, during as if this passive heat radiation device (such as fin) pressurized, the pressure of this passive heat radiation device can not be passed to the back side of this chip.
With reference to figure 5, it shows the semiconductor packaging structure 300 of the second embodiment of the present invention.The semiconductor packaging structure 300 of this second embodiment is similar to the semiconductor packaging structure 200 of this first embodiment substantially, and similar elements indicates identical label.Both differences be in, this semiconductor packaging structure 300 comprises a radiating fin 360, one second heat-conducting interface material 362 and one the 3rd heat-conducting interface material 364 in addition.This second heat-conducting interface material 362 is disposed between this fin 212 and this radiating fin 360, in order to this radiating fin 360 is fixed on this fin 212.This second heat-conducting interface material 362 can have the material of thermal conductivity and viscosity.The 3rd heat-conducting interface material 364 is disposed between this active radiator 250 and this radiating fin 360, is sent to this radiating fin 360 in order to the heat with this active radiator 250.The 3rd heat-conducting interface material 364 can be the material with thermal conductivity and viscosity, such as thermal grease (thermal adhesive) or tin cream (solder paste).This radiating fin 360 also is a kind of passive heat radiation device, is the passive heat radiation of nature.
The end face 213 of this fin 212 is higher than the end face 235 of this active radiator 250, that is has a preset distance D between the end face 235 of the end face 213 of this fin 212 and this active radiator 250.Owing to have this preset distance D between the end face 213 of this fin 212 and the end face 235 of this active radiator 250, that is this preset distance D can be used as the buffering area between this active radiator 250 and this radiating fin 360, therefore the weight of this radiating fin 360 can not be pressed on this active radiator 250, but is pressed on this fin 212.Because this chip 230 is positioned at this active radiator 250 belows, so the weight of this radiating fin 360 also can not be pressed on this chip 230, so can alleviate the pressure of this chip 230.Moreover, since this active radiator 250 be positioned at this fin 212 run through opening 214, so the weight of this fin 212 also can not be pressed on this active radiator 250, and then the weight of this fin 212 also can not be pressed on this chip 230.In addition, during these radiating fin 360 pressurizeds, the pressure of this radiating fin 360 can not be passed to this active radiator 250, but is passed to this fin 212.Therefore, the pressure of this radiating fin 360 can not be passed to this chip 230.
The weight of the passive heat radiation device of semiconductor packaging structure of the present invention (such as fin or radiating fin) can not be pressed on this chip, so can alleviate the pressure of this chip.In addition, during this passive heat radiation device pressurized, the pressure of this passive heat radiation device can not be passed to this chip.
With reference to figure 6, it shows the semiconductor packaging structure 400 of the third embodiment of the present invention.The semiconductor packaging structure 400 of the 3rd embodiment is similar to the semiconductor packaging structure 200 of this first embodiment substantially, and similar elements indicates identical label.Both differences be in, the back side 234 of the chip 230 of this semiconductor packaging structure 400 is disposed at the upper surface 226 of this carrier 240 by viscose glue 435.One conducting element is such as many bonding wires 436, in order to this carrier 240 is electrically connected at active surperficial 232 of this chip 230.This active radiator 250 be disposed at this chip 230 active surperficial 234 on, and be positioned at this fin 212 run through opening 214.The thermoelectric cooling module of this active radiator 250 can be electrically connected at this chip 230 by lead 451, in order to intake to this thermoelectric cooling module.
Semiconductor packaging structure of the present invention also can comprise this active radiator and this passive heat radiation device simultaneously, this active radiator is not covered by this passive heat radiation device, in order to the heat on the active surface of this chip is directly discharged outside this semiconductor packaging structure via this active radiator, to reach the effect of quick heat radiating.In addition, during as if this passive heat radiation device (such as fin) pressurized, the pressure of this passive heat radiation device can not be passed to the active surface of this chip.
Though the present invention discloses with previous embodiment, so it is not in order to qualification the present invention, any persons of ordinary skill in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various changes and modification.Therefore protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (10)
1. semiconductor packaging structure comprises:
One carrier;
One chip is disposed on this carrier;
One reinforcement is disposed on this carrier;
One fin is disposed on this reinforcement, and comprises one and run through opening; And
One active radiator is disposed on this chip, and is positioned at this and runs through opening.
2. according to the semiconductor packaging structure of claim 1, wherein this fin and this active radiator have an end face respectively, and the end face of this fin is higher than the end face of this active radiator.
3. according to the semiconductor packaging structure of claim 2, wherein has a preset distance between the end face of the end face of this fin and this active radiator.
4. according to the semiconductor packaging structure of claim 1, other comprises:
One first heat-conducting interface material is disposed between this active radiator and this chip.
5. according to the semiconductor packaging structure of claim 1, other comprises:
One radiating fin is fixed on this fin.
6. according to the semiconductor packaging structure of claim 1, wherein this active radiator is a thermoelectric cooling module.
7. according to the semiconductor packaging structure of claim 1, wherein this active radiator is electrically connected at one in this carrier or this chip.
8. according to the semiconductor packaging structure of claim 1, wherein this reinforcement is around this chip.
9. according to the semiconductor packaging structure of claim 1, other comprises:
One first viscose glue is in order to be adhered to this reinforcement on this carrier; And
One second viscose glue is in order to be adhered to this fin on this reinforcement.
10. according to the semiconductor packaging structure of claim 1, wherein this fin and this reinforcement manufacturing that is formed in one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810091215 CN101276795B (en) | 2008-04-21 | 2008-04-21 | Semiconductor encapsulation construction |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810091215 CN101276795B (en) | 2008-04-21 | 2008-04-21 | Semiconductor encapsulation construction |
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| Publication Number | Publication Date |
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| CN101276795A CN101276795A (en) | 2008-10-01 |
| CN101276795B true CN101276795B (en) | 2010-04-07 |
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| CN 200810091215 Active CN101276795B (en) | 2008-04-21 | 2008-04-21 | Semiconductor encapsulation construction |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103117275B (en) | 2013-01-31 | 2015-08-19 | 华为技术有限公司 | A kind of chip-packaging structure and chip packaging method |
| US10083920B1 (en) * | 2018-02-01 | 2018-09-25 | Google Llc | Package stiffener for protecting semiconductor die |
| CN113257761A (en) * | 2021-02-24 | 2021-08-13 | 北京时代民芯科技有限公司 | Active heat dissipation structure of flip chip device and interconnection method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909056A (en) * | 1997-06-03 | 1999-06-01 | Lsi Logic Corporation | High performance heat spreader for flip chip packages |
| CN1959966A (en) * | 2005-09-27 | 2007-05-09 | 艾格瑞系统有限公司 | Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink |
| CN1971889A (en) * | 2005-11-25 | 2007-05-30 | 鸿富锦精密工业（深圳）有限公司 | Heat radiator |
-
2008
- 2008-04-21 CN CN 200810091215 patent/CN101276795B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5909056A (en) * | 1997-06-03 | 1999-06-01 | Lsi Logic Corporation | High performance heat spreader for flip chip packages |
| CN1959966A (en) * | 2005-09-27 | 2007-05-09 | 艾格瑞系统有限公司 | Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink |
| CN1971889A (en) * | 2005-11-25 | 2007-05-30 | 鸿富锦精密工业（深圳）有限公司 | Heat radiator |
Non-Patent Citations (4)
| Title |
|---|
| JP特开2002－118214A 2002.04.19 |
| JP特开2005－243693A 2005.09.08 |
| JP特开2007－12725A 2007.01.18 |
| JP特开平11－150203A 1999.06.02 |
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| CN101276795A (en) | 2008-10-01 |
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