CN101281930B - Optical signal transfer element - Google Patents
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- CN101281930B CN101281930B CN2007100958129A CN200710095812A CN101281930B CN 101281930 B CN101281930 B CN 101281930B CN 2007100958129 A CN2007100958129 A CN 2007100958129A CN 200710095812 A CN200710095812 A CN 200710095812A CN 101281930 B CN101281930 B CN 101281930B
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Abstract
The invention provides a nano channel flash memory, which includes: a grid structure formed on a substrate; a drain electrode and a source electrode formed on two sides of the grid structure; plural carriers capture structure formed on side wall of the grid structure; a nano channel equipped at bottom of the grid structure for connecting the drain electrode and the source electrode, wherein the grid structure includes a high-dielectric grid dielectric layer. The nano channel flash memory employs a nano carbon-tube as a semi-conductive structure to benefit nano-stage memory components and increase operation capability, further more, a multi-site flash memory is provided to increase components density.
Description
Technical field
The present invention is particularly to manufacture method and the structure of a kind of nano channel flash memory (Nano-Channel Memory) relevant for a kind of semiconductor subassembly.
Background technology
The electric formula programmable read only memory (EEPROM) of erasing is the extensive memory module of employing of the institute of information electronic product now, the slower shortcoming of access speed is arranged originally, yet along with the progress of manufacturing process technology, developed access speed EEPROM faster in recent years, generally be referred to as flash memory.Basically, typical EEPROM is constituted with suspension joint gridistor structure, when writing data, impose a high voltage in the control grid, by so-called Fowler-Nordheim tunneling effect, make electronics pass tunnel oxide and arrive in the suspension joint grid, improve its critical voltage (threshold voltage) from the drain region; When erasing data, then impose a high voltage in source area, make the aforementioned electronics that is injected into the suspension joint grid pass tunnel oxide and flow into source area, make it reply original critical voltage.
Over past ten years, in the field of non-volatile (non-volatile) flash memory, how many technology promptly utilize the mode of electronics to reach repetitive read-write and the function of erase (erase) in research and development, and high power capacity, low power consumption etc. also all are the targets that industrial circle makes great efforts to research and develop.Wherein, in the flash memory (Flash Memory), be with the unit of a single memory cell (cell) as flash memory, it not only can reach function of reading with the mode of electronics, even the space (sector or page) of a sheet of flash memory of erasing in can be at one time, so flash memory not only possesses reading speed advantage is faster arranged, also have the absolute predominance of low power consumption, therefore, flash memory is one of very important assembly in the present semiconductor industry.
Desire to carry out sequencing when action when existing flash memory, apply high voltage on the control grid, electronics promptly passes grid oxic horizon from the source electrode of silicon base and enters floating grid.When existing flash memory desires to erase when action, apply low-voltage or do not execute voltage on the son control grid, apply high voltage in the drain electrode of silicon base, electronics promptly passes the source electrode that grid oxic horizon is got back to from floating grid.Hence one can see that, and existing flash memory once can carry out the sequencing of one group of data or erase.But when assembly is little during to nano-scale, showing based on optics and quantum effect, photoetching cost fast rise and pattern-making are difficult for then, cause the carrier characteristic wayward and influence component characteristic.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of multi-bit memory cell and manufacture method thereof, can increase the figure place of deal with data, but improve the deal with data amount of flash memory and its nanometer.
According to above-mentioned purpose, the invention provides a kind of nano channel flash memory (memory), comprising: multiple grid structure (multiple gate structure) comprises floating grid (floating gate) and control grid (control gate) is formed on the substrate (substrate); Drain electrode (drain electrode) and source electrode (sourceelectrode) are formed at the both sides of this multiple grid; Nano channel (nano-channel) connects this drain electrode and source electrode and is positioned at the downside of this multiple grid.Wherein this multiple grid is stacked gate (stacked gate) or grid dividing structure (split gate), and the multiple grid structure comprises high dielectric gate utmost point dielectric layer (high-k gatedielectric), and wherein this high dielectric gate utmost point dielectric layer comprises (SiO
2), (HfO
2), (ZrO
2), (TiO
2), (HfTiO), (HfAIO), (La
2O
3) or (LaAIO).Nano channel must be made for adopting the nano-sized carbon pipe.
A kind of nano channel flash memory comprises that grid structure is formed on the substrate; Drain electrode and source electrode are formed at the both sides of this grid structure; Plural number carrier arresting structure (carrier trapping mechanism) is formed at the sidewall of this grid structure; Nano channel connects this drain electrode and source electrode and is positioned at the downside of this grid structure.Wherein this grid structure comprises high dielectric gate utmost point dielectric layer, and high dielectric gate utmost point dielectric layer comprises (SiO
2), (HfO
2), (ZrO
2), (TiO
2), (HfTiO), (HfAIO), (La
2O
3) or (LaAIO).
The present invention also proposes a kind of nano channel flash memory and comprises: grid structure is formed on the substrate; Drain electrode and source electrode are formed at the both sides of this grid structure; Nano channel connects this drain electrode and source electrode and is positioned at the downside of this grid structure; First conductive layer is formed on the surface that is positioned at the substrate irrigation canals and ditches, connects this drain electrode; Insulating barrier, it is positioned at this first conductive layer surface; Second conductive layer is formed at this surface of insulating layer.Grid structure comprises high dielectric gate utmost point dielectric, and wherein this high dielectric gate utmost point dielectric layer comprises (SiO
2), (HfO
2), (ZrO
2), (TiO
2), (HfTiO), (HfAIO), (La
2O
3) or (LaAIO).
In addition, the present invention discloses a kind of nano channel flash memory, comprising: at least two grid structures are formed on the substrate; At least two drain electrodes and the corresponding respectively both sides that are formed at this at least two grid structure of source electrode; Nano channel is formed at a downside of this at least two grid structure, connects the drain electrode and the source electrode of this correspondence.Wherein this grid structure comprises high dielectric gate utmost point dielectric layer.High dielectric gate utmost point dielectric layer comprises (SiO
2), (HfO
2), (ZrO
2), (TiO
2), (HfTiO), (HfAIO), (La
2O
3) or (LaAIO).The plan structure of said modules comprises that plural character line (bit line) is disposed on the substrate; Complex digital language line (word line) is staggered into about becoming the checkerboard configuration with it; At least one nano channel area configurations is in not staggered subregion.Wherein this word language line comprises high dielectric gate utmost point dielectric layer and is formed at its below.Based on utilizing the nano channel and the zone of nano channel not, according to the conducting whether therebetween of its carrier, be set at numeral one (digital one) or digital zero (digital zero), therefore can be utilized the nano channel read-only memory that designs and produces of the present invention.
The present invention proposes a kind of TFT of nano channel in addition, and it is characterized in that comprising that applicable to LCD (LCD) grid structure is formed on the substrate; Insulating barrier is formed on this grid; Nano channel, be disposed on this insulating barrier and haply with this grid contraposition; Drain electrode and source electrode are connected with this nano channel, are positioned on this insulating barrier.Wherein this nano channel is a CNT (carbon nano-tube), and wherein this substrate can be glass substrate or other material that is fit to, and drain electrode comprises silicon, metal or alloy with the source electrode material.
The present invention adopts CNT (carbon nano-tube) to be beneficial to make the nanoscale memory module as half guide structure, promotes operating characteristics.The present invention more proposes the multi bits flash memory, with lifting subassembly density.
Description of drawings
Fig. 1 shows nano channel flash memory schematic diagram of the present invention.
Fig. 2 shows nano channel flash memory schematic diagram of the present invention.
Fig. 3 shows nano channel multi bits flash memory schematic diagram of the present invention.
Fig. 4 shows nano channel flash memory schematic diagram of the present invention.
Fig. 5 shows on the nano channel read-only memory of the present invention and looks schematic diagram.
Fig. 6 shows nano channel read-only memory schematic cross-section of the present invention.
Fig. 7 shows nano channel of the present invention and optical diode assembly schematic cross-section.
Fig. 8 shows nano channel TFT schematic cross-section of the present invention.
Fig. 9 shows nano channel flash memory schematic diagram of the present invention.
Figure 10 shows nano channel flash memory schematic diagram of the present invention.
Figure 11 shows nano channel flash memory schematic diagram of the present invention.
The primary clustering symbol description:
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Please refer to the tangent plane schematic diagram that Fig. 1 and Fig. 2 show non-volatile flash memory of the present invention, shown in flash memory as illustration, non-in order to limit the present invention.At first, please refer to Fig. 1, in forming insulating barrier 26 and control grid 28 between gate dielectric 22, floating grid 24, grid in regular turn at semiconductor-based the end 20.Wherein, to can be for example be the silicon or the GaAs based end at the semiconductor-based end 20; The material of insulating barrier 26 between grid, for example be oxide layer (silicon dioxide), nitration case etc.; It for example is doped polysilicon layer (doped polysilicon) or mix crystal silicon layer (epi-silicon layer), metal level or alloy-layer of heap of stone that the grid material can be.It is etching cover curtain (etching mask) that stacked gate can be utilized lithographic fabrication processes (lithography) patterning photoresist layer, and etching storehouse rete is removed the patterning photoresist layer then to form the grid structure of a storehouse.
Described gate dielectric can adopt the thermal oxidation manufacturing process or chemical vapour deposition technique (CVD) is made, and it can be a high-k insulating layer for example is silicon dioxide (SiO2) or hafnium oxide oxide layers such as (HfO2), the also applicable (SiO of other high dielectric layer
2), (HfO
2), (ZrO
2), (TiO
2), (HfTiO), (HfAIO), (La
2O
3) or (LaAIO) etc.Is the cover curtain with the gate stack structure, the substrate step (doping or implanting) of mixing to semiconductor is to form source (S/D) 30, as shown in Figure 1 on the semiconductor-based end of grid side.Then, silicide step is aimed in the semiconductor substrate voluntarily, on the surface of grid, source-drain electrode area, to form metal silicide 31 to promote conductivity; Wherein, metal silicide 31 for example is TiSi2 or CoSi2 or NiSi.Fig. 1 and the difference person of Fig. 2 institute are the stacked gate of comparing Fig. 1, Figure 2 shows that grid dividing structure, so its control grid and floating grid are the difference patterning, and this is for generally knowing this skill person as can be known, and control grid and floating grid are offset a distance, and have only part to overlap.The person of noting, but all embodiment of this case are modification space wall (spacer) or change the form or the doping section (profile) of ion doping also, as having LDD doping, halo-implant, pocketimplant etc., based on this non-pattern characteristics, so do not give unnecessary details.In addition, Figure 9 shows that another flash memory, with the difference person of Fig. 2 embodiment institute be after making floating gate, implement the oxidation manufacturing process, on floating grid, make one similar oxidation structure (FOX; Field oxide) 29, therefore the floating grid edge is formed wedge angle and be beneficial to the gathering carrier, when erasing, quicken erasing speed.
Plural number nano channel 32 is disposed under the grid oxic horizon 22, between source/drain regions (S/D) 30.In other words, source/drain regions (S/D) 30 connects the two ends of nano channel 32 respectively.Note that illustrated dimensions is not according to actual fabrication, nano channel is in fact corresponding less.Preferred embodiment can be CNT (carbon nano-tube), can utilize one to 50 layer of carbon structure to make.For example, diameter can be between the 1-2 nanometer, and length can be 10-100 nanometer or shorter.It has preferable thermal conductance and the service speed of lifting subassembly compared to silicon, and its power consumption is lower.Note that above-mentioned source/drain regions (S/D) 30 also can adopt deposition, sputtering way to form metal material or conductive material making and not adopt the implanting ions mode, is beneficial to cooperate the making of nano channel.Adopting different state bias voltage, as write, erase, read, bias voltage such as programming.Above-mentioned bias voltage can make carrier pass through nano channel tunnelling grid oxic horizon, makes carrier inject this floating grid or shifts out this floating grid, and must carry out the storage or the program of erasing.Each embodiment can comprise clearance wall 35 or shallow trench isolation 33, with Figure 10 as illustration.
The manufacture method of CNT (carbon nano-tube) can adopt and heat carbon containing organic compound formation carbon atom, feeds reaction system as using the methane body, and contact substrate high temperature begins to decompose carbon atom and is subjected to nm of gold influence growth.Or adopt the nano-pore substrate, cooperate air-flow to add methane with hydrocarbon gas-phase decomposition method and feed the porous plate making.CNT (carbon nano-tube) has semi-conductive characteristic, can promote the semiconductor subassembly characteristic and be beneficial to the making of nanometer microminiaturization assembly, and when operation, carrier therebetween flows by CNT (carbon nano-tube).The manufacture method of CNT (carbon nano-tube) can be consulted J.J Chiu et al., Advanced Material15,1361,2003.According to demand, can select metallization CNT (carbon nano-tube) (metallic carbon nanotubes) or semiconduction CNT (carbon nano-tube) (semiconductive carbon nanotubes for use.Both differences are atomic arrangement differences.The document of other relative production CNT (carbon nano-tube) can be joined United States Patent (USP) 7,192, and 642,7,183,228,7,161,286,6,811,957.
Figure 3 shows that another enforcement is sharp, be depicted as multi bits flash memory (multi-bits memory), one control grid, 28 control two carriers (carrier) arresting structures 25, carrier arresting structure 25 utilizes defective (defects) to be caught carrier, and is defined as numerical digit one (digital one) or numerical digit zero (digitalzero).Control grid 28 controls two carrier arresting structures 24 are isolated with insulating barrier 26.Compliance forms an insulating barrier 28 on the surface of insulating barrier 26, for example is nitration case.Insulating barrier 28 is carried out the anisotropic etching, form a clearance wall 28 to make two carrier arresting structures 25 with sidewall at grid 28.Wherein, the method for anisotropic etching (anisotropic etching) for example be reactive ion etching (reactiveion etching, RIE) or plasma etching (plasma etching).Then, form source/drain regions (S/D) 30.In like manner, before making the control grid, CNT (carbon nano-tube) elder generation shape is made.It is positioned at the two ends of source/drain regions (S/D) 30.All enforcement profits of this case all can be aimed at silicide step voluntarily to the semiconductor substrate, to form metal silicide on the surface of grid, source-drain electrode area S/D, in order to the usefulness of follow-up source/drain electrode Yu gate pole conducting.Wherein, metal silicide for example is TiSi2 or CoSi2 or NiSi.
Below explanation bias voltage and the current source of utilizing of the present invention writes multi-bit memory cell.At first, on grid 28, apply a bias voltage, on the drain region, apply a drain electrode and write voltage, and apply the constant current source of 1nA to a 1mA ampere in source area.The hot carrier stream of a channel can occur, because the channel under source-drain electrode area and the grid is kept a distance, hot carrier will inject and be stored in the clearance wall of drain side at below the clearance wall between grid 28 and drain region the semiconductor-based end.Therefore as can be known, utilize the function of the formed clearance wall 25 of nitration case, the carrier that is similar to existing flash memory stores grid, can store the carrier from source electrode, but it adopts the defect capture carrier, the structure difference.Extended meeting is defined by being encoded to " 1 " behind the clearance wall of drain region side, and extended meeting is defined by being encoded to " 0 " after not storing the clearance wall of source area side of carrier.In like manner, can write the arresting structure of another side.Therefore, as long as control drain electrode writes the source-drain electrode area position that voltage and source electrode constant current source are applied, what can determine easily that multi-bit memory cell " XY " will define is encoded to " 00 " or " 01 " or " 10 " or " 10 " or " 11 ".In like manner, also it can be erased.As on grid 28, applying back bias voltage, apply the voltage of just erasing in the drain region.Therefore the clearance wall of drain region side can be written into again and before be stored to the different different in nature carrier of clearance wall, and the carrier that before had been written into can be neutralized by different in nature carrier, or attracts the carrier of original storage and the coding that it was defined is erased.Figure 11 shows that carrier arresting structure 27 is positioned at the below of control gate 28, it is preferably the stack architecture of ONO, ON.
Figure 4 shows that having nano channel 32 is disposed at memory module between drain electrode and source electrode, the drain coupled of flash memory is to according to the Charge Storage body of conductive layer/insulating barrier/conductive coating structure.Lift an example, this flash memory has a channel shaped and is formed within the substrate, and from outer rim to interior first conductive layer, 34/ insulating barrier, 36/ second conductive layer 38 that is at least in regular turn, carrier must be insulated layer 36 and catch.First conductive layer 34 is connected with drain electrode.CNT (carbon nano-tube) has semi-conductive characteristic, is disposed between drain electrode and source electrode, and when operation, carrier is to promote the semiconductor subassembly service speed and to be beneficial to the assembly microminiaturization by CNT (carbon nano-tube).In like manner, described conductive film layer can not be made in the groove.But being made in the groove can lifting subassembly density and preferable and smooth appearance is provided.Insulating barrier can be adopted silicon dioxide, NO (nitride/oxide), ONO (oxide/nitride/oxide), ferroelectric material, lead titanate-zirconate, tantalum bismuthic acid strontium material.
Figure 5 shows that read-only memory of the present invention (read only memory), it comprises bit line 52 and is disposed on the substrate 50, and bit line adopts to be made in implanting ions (ion implant) flush type and is commonly referred to as buried bit line in the substrate usually.Word language line (grid) 54 is staggered into checkerboard with it, and plural nano channel zone 56 is disposed at the subregion that does not interlock, as the semiconduction zone.Its sectional view can be consulted Fig. 6, comprises two class components and is disposed on the substrate 50, and oxide layer 58 is positioned under the grid 54, and the bed course of selection (liner layer) 60 can form along gate surface.Clearance wall 62 can be made in gate lateral wall according to known method.Shown in figure, grid below comprises nano channel 32, and another is nano channel not.The assembly that possesses nano channel is able to conducting electric current between drain electrode, source electrode, otherwise then denys, utilize this mode in addition the digital information of definitions component be numeral one or digital zero.The present invention is provided the nanoscale read-only memory.
Light signal transfer assembly (light signal transfer device) shown in Figure 7, its grid structure comprises oxide layer 72, grid 74 are formed on the substrate 70, grid structure can comprise clearance wall 76 and be formed at its sidewall, drain-source doped region 78 correspondences are formed in the substrate 70, substrate tool isolated area 71 is made to adopt a shallow trench technology or an oxidation technology.Optical diode (photodiode) doped region 80 is made in the substrate and is connected with drain-source doped region 78, in order to receive the light of incident.Present embodiment comprises CNT (carbon nano-tube) 32 and is made in the grid downside and is positioned at 78 of drain-source doped regions, and the carrier path is provided when operation.Based on this embodiment, the dopant dose of optical diode doped region 80 is about the phosphorus of 1E12-1E14/ square centimeter, and implant energy is about, 50-180keV.This region surface can cloth plants that dosage is about the 1E15-1E16/ square centimeter, implant energy is about the ion of 5-40keV to make optical diode doped region surface n+doping, can make electric hole diffusion length shorter, and then prevent dark current (darkcurrent) in this interval.Above-mentioned dosage, energy and the dopant profile of mixing all variablely is beneficial to be suitable for his kenel semiconductor.Above optical diode, will cover the number insulating barrier as 82,84,86 as illustration and conductive pattern 88,90 as illustration, non-in order to limit the present invention.On the insulating barrier, form a lenticule and enter optical diode doped region 80 in order to the guiding incident light.This example helps to reduce dark current, helps the assembly microminiaturization and promotes operating characteristics and increases pixel.In addition, it is fixing supposing to provide the photodiode and the area of transfer assembly, utilizes nano channel transfer assembly can dwindle its area occupied, and photodiode area is increased, and then strengthen absorption photon area, be collection with the increase light signal, and the lifting subassembly performance.
In like manner; Figure 8 shows that a display unit, wherein comprise back polaroid 100, back glass substrate 102, back transparency electrode 104, TFT106, liquid crystal 108, preceding transparency electrode 110, front glass substrate 112, colored filter 114, cover glass 116 and preceding polaroid 118.Wherein above-mentioned TFT106 is formed on the substrate 10, and a grid 12 is patterned on the substrate, subsequently an insulating barrier 14 cover gate 12.Nano channel 16 is disposed on the above-mentioned insulating barrier 14, is beneficial to microminiaturization with grid 12 contrapositions haply, promotes resolution and service speed.The two end portions of drain/source 18 rough covering nano channels 16 is connected with it, and drain/source 18 can adopt silicon layer or metal, alloy-layer to make.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing to change and retouching, thus protection scope of the present invention when with claim the person of being defined be as the criterion.
Claims (5)
1. a light signal is transferred element, and it is characterized in that it comprises: grid structure is formed on the substrate; Drain electrode is formed in the described substrate with the source dopant zone and is positioned at the both sides of described grid structure; The optical diode doped region, it is formed in the described substrate and is positioned at the side in described drain electrode and source dopant zone; CNT (carbon nano-tube), it connects described drain electrode and source dopant zone, and is positioned at the downside of described grid structure, and wherein said CNT (carbon nano-tube) can be dwindled the area occupied in described light signal transfer element, and the optical diode area is increased, and then strengthen the collection that absorbs photon area increase light signal.
2. light signal transfer element as claimed in claim 1 is characterized in that, described light signal transfer element more comprises insulating barrier, and this insulating barrier is positioned at described optical diode doped region top.
3. light signal transfer element as claimed in claim 2 is characterized in that, described light signal transfer element more comprises lenticule, and this lenticule is positioned at described insulating barrier top, enters described optical diode doped region in order to the guiding incident light.
4. light signal transfer element as claimed in claim 1 is characterized in that described optical diode doped region dopant dose is 1E12-1E14/cm
2Phosphorus, implant energy is 50-180keV.
5. light signal transfer element as claimed in claim 1 is characterized in that, it is 1E15-1E16/cm that described optical diode doped region surface cloth is planted dosage
2, implant energy be the ion of 5-40keV making optical diode doped region surface n+dopings, shortening hole-diffusion length and then prevent dark current.
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|---|---|---|---|
| CN2007100958129A CN101281930B (en) | 2007-04-04 | 2007-04-04 | Optical signal transfer element |
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|---|---|---|---|
| CN2007100958129A CN101281930B (en) | 2007-04-04 | 2007-04-04 | Optical signal transfer element |
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| CN101281930B true CN101281930B (en) | 2011-09-28 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1256986A2 (en) * | 2001-05-10 | 2002-11-13 | Samsung Electronics Co., Ltd. | Single electron memory device and method for manufacturing the same |
| US6888739B2 (en) * | 2002-06-21 | 2005-05-03 | Micron Technology Inc. | Nanocrystal write once read only memory for archival storage |
| CN1839481A (en) * | 2003-08-21 | 2006-09-27 | 哈恩-迈特纳研究所柏林有限公司 | Vertical nanotransistor, method for producing the same and memory assembly |
| US7119395B2 (en) * | 2003-08-11 | 2006-10-10 | Infineon Technologies Ag | Memory cell with nanocrystals or nanodots |
-
2007
- 2007-04-04 CN CN2007100958129A patent/CN101281930B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1256986A2 (en) * | 2001-05-10 | 2002-11-13 | Samsung Electronics Co., Ltd. | Single electron memory device and method for manufacturing the same |
| US6888739B2 (en) * | 2002-06-21 | 2005-05-03 | Micron Technology Inc. | Nanocrystal write once read only memory for archival storage |
| US7119395B2 (en) * | 2003-08-11 | 2006-10-10 | Infineon Technologies Ag | Memory cell with nanocrystals or nanodots |
| CN1839481A (en) * | 2003-08-21 | 2006-09-27 | 哈恩-迈特纳研究所柏林有限公司 | Vertical nanotransistor, method for producing the same and memory assembly |
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