CN101308834A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

Info

Publication number
CN101308834A
CN101308834A CNA2008100840386A CN200810084038A CN101308834A CN 101308834 A CN101308834 A CN 101308834A CN A2008100840386 A CNA2008100840386 A CN A2008100840386A CN 200810084038 A CN200810084038 A CN 200810084038A CN 101308834 A CN101308834 A CN 101308834A
Authority
CN
China
Prior art keywords
substrate
integrated circuit
shallow trench
trench isolation
circuit structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2008100840386A
Other languages
English (en)
Other versions
CN101308834B (zh
Inventor
陈承先
郭正铮
卿恺明
陈志华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN101308834A publication Critical patent/CN101308834A/zh
Application granted granted Critical
Publication of CN101308834B publication Critical patent/CN101308834B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明涉及一种集成电路结构，包括衬底、位于衬底之中的从一端逐渐变窄的穿透硅通道、由衬底上表面延伸进入衬底的硬掩膜区，其中此硬掩膜围绕穿透硅通道的上方部分、位于衬底上的介电层、以及由介电层的上表面向穿透硅通道延伸的金属柱，其中金属柱包含与穿透硅通道的填充材料相同的材料。

Description

集成电路结构
技术领域
本发明涉及集成电路结构，且特别涉及一种具有外形从一端逐渐变窄的穿透硅通道(Through-Silicon Via)的集成电路结构及其制造方法。
背景技术
由于电子元件(例如晶体管、二极管、电阻及电容等)的集成密度持续增加，使得集成电路发明与半导体产业持续不断地快速成长。其中，集成密度的改善最主要是源自于反复不断地降低最小关键尺寸，以允许更多元件被集成在一个特定的芯片区域中。
集成密度的改善基本上是二维的范畴，集成电路元件所占据的空间，基本上位于半导体晶片的表面。虽然光刻工艺的惊人发展，已经对二维集成电路制造提供了一定程度的改善，然而集成密度在二维中所能达到的改进程度仍然存在本质上的限制。其中一个限制条件来自于制造这些元件所需的最小尺寸。当要将更多元件纳入单一芯片时，就必须需要更复杂的设计。
另一个限制条件则来自于，当元件数量增加时，连接元件之间的内连线的数目和长度也大幅度增加。当内连线的数目和长度大幅度增加时，电路阻容延迟(RC Delay)和能量消耗也会随之增加。
解决上述限制条件的方案中，以三维集成电路和叠层芯片最常被使用。穿透硅通道在三维集成电路和叠层芯片之中，用来连接芯片。图1和图2示出一种穿透硅通道的制造方法。请参照图1，首先提供可在其上方形成集成电路(未示出)的硅衬底2。接着形成多个可以用来在其中形成金属线和过孔的介电层6，其中介电层6是一层一层地堆叠在硅衬底2上。接着使用并图案化光刻胶8。形成开口10穿过介电层6，并将硅衬底2暴露出来。接着通过开口10蚀刻硅衬底2，以形成如图2所示出的开口12。再于开口10和12的侧壁和底部形成黏着层及/或扩散阻挡层(未示出)。然后通过电镀填充铜(未示出)以形成一穿透硅通道。
传统穿透硅通道的形成工艺仍有多种缺点。由于开口10和12的深度比起其宽度显得相当深，因此黏着层和扩散阻挡层覆盖开口10和12的侧壁和底部的能力相对变差。再者想要形成无孔洞的穿透硅通道也相当的难。因此必须降低用来将铜填充入开口10和12的电镀电流，以减少在穿透硅通道中产生孔洞的机会，然而生产量也因此下降。
为了解决此问题，开口10和12，尤其是开口12较佳具有上宽下窄，且从一端逐渐变窄的外形，其中此形式可通过调整蚀刻剂的配方以增加横向蚀刻的方式来达到。然而此方式会在介电层6下方产生侧蚀缺口(Undercut)14。而侧蚀缺口14会在后续所形成的扩散阻挡层和种子铜层中产生裂口，因而对后续的铜电镀工艺产生负面影响。
因此有需要提供一种穿透硅通道结构及其制造方法，可同时具备从一端逐渐变窄外形的穿透硅通道，又可以克服传统穿透硅通道的缺点。
发明内容
因此本发明所要解决的技术问题在于提供一种集成电路结构，该集成电路结构具有外形从一端逐渐变窄的穿透硅通道，可以克服传统穿透硅通道的缺点。
为了实现上述目的，根据本发明的一个实施例，提供一种集成电路结构，包括衬底、位于衬底之中从一端逐渐变窄的穿透硅通道、由衬底的上表面延伸进入衬底内部的硬掩膜区，其中此硬掩膜围绕穿透硅通道的上方部分、位于衬底上的介电层、以及由介电层的上表面向穿透硅通道延伸的金属柱(metalpost)，其中金属柱包含与穿透硅通道的填充材料相同的材料。
为了实现上述目的，根据本发明的另一个实施例，提供一种集成电路结构，包括衬底、由衬底的上表面延伸至衬底之中的浅沟槽绝缘区，且浅沟槽绝缘区形成一个环、位于浅沟槽绝缘区上方的多晶硅环、位于衬底及多晶硅环上方的低介电系数介电层、以及由低介电系数介电层上表面延伸入衬底的导电结构，其中导电结构包括位于低介电系数介电层中的第一部分，以及贯穿多晶硅环与浅沟槽绝缘区所形成的环的第二部分。
为了实现上述目的，根据本发明的又一个实施例，提供一种形成集成电路结构的方法，包括提供一衬底；形成硬掩膜，使其由衬底上表面延伸进入衬底；在硬掩膜层上形成蚀刻终止层；在衬底和蚀刻终止层上形成低介电系数的介电层；以及形成导电结构，使其由低介电系数介电层的上表面延伸进入衬底，其中导电结构包括位于低介电系数介电层中的第一部分，以及贯穿蚀刻终止层与硬掩膜层的第二部分。
为了实现上述目的，根据本发明的又一个实施例，提供一种形成集成电路结构的方法，包括提供一衬底；形成由衬底的上表面延伸至衬底之中的浅沟槽绝缘区，且浅沟槽绝缘区围绕衬底的一个上方部分；在衬底和浅沟槽绝缘区上方形成一平板，其中此平板覆盖被浅沟槽绝缘区所围绕的衬底的上方部分；在衬底、浅沟槽绝缘区以及平板上形成介电层；使用平板作为蚀刻终止层，在介电层中形成开口，通过此开口将平板的内在部分暴露出来；以及通过开口蚀刻此平板。
根据上述实施例，本发明具有优势的技术特征包含从一端逐渐变窄的穿透硅通道，同时降低侧蚀缺口现象，并改善扩散阻挡层的侧壁覆盖情况。
为让本发明的上述和其它目的、特征、优点与实施例能更明显易懂，下面结合附图详细说明。
附图说明
图1和图2示出一种制造传统穿透硅通道的工艺结构剖面图；
图3A至图9是根据本发明的一实施例的一种穿透硅通道的工艺结构剖面图及俯视图。
【主要器件符号说明】
2：硅衬底          6：介电层
10：开口           12：开口
14：侧蚀缺口       20：衬底
22：集成电路       24：浅沟槽绝缘区
25：浅沟槽绝缘区   26：开口
28：多晶硅平板     30：内连结构
32：内层介电层     34：金属层间介电层
36：钝化层         40：光刻胶
42：开口           43：虚线
44：穿透硅通道开口           46：侧蚀缺口
48：浅沟槽绝缘区暴露于外的余留部分
52：侧蚀缺口                 60：扩散阻挡层
64：穿透硅通道               66：金属柱
D1：开口的直径               D2：多晶硅平板的直径
D3：浅沟槽绝缘区的外径       D4：开口的直径
ΔD：D1和D2的差              T1：浅沟槽绝缘区的厚度
T2：多晶硅平板的厚度         K1：衬底被蚀刻的深度
K2：浅沟槽绝缘区被蚀刻的深度
β：侧壁的倾斜角度          α：侧壁的倾斜角度
具体实施方式
以下内容是以一较佳实施例详述本发明的制造与使用。值得注意的是，本发明所提出的是一些可行的发明概念，可在不同的特殊实施例中得到体现。而以下所述的实施例只是描述一种制造与使用本发明的特定方式，并非用以限制本发明的范围。
下述实施例提供一种改进的穿透硅通道及其制造方法。先描述制造本发明的较佳实施例的中间步骤，再探讨不同实施例之间的差异。在本发明的所有附图与说明实施例中，相似的图标号码用以标示相似的元件。
请参照图3A，提供一衬底20，较佳为硅衬底。衬底20也可以由其它包含III族、VI族以及/或者V族元素的半导体材料所构成。另外衬底20可以由块状半导体(Bulk Semiconductor)、应变半导体(Strained Semiconductor)以及类似的材料所构成。集成电路22，以晶体管作为代表，则形成于衬底20的表面。
浅沟槽绝缘区24形成于衬底20之中，较佳是在衬底20中蚀刻浅沟槽，再使用绝缘体填充浅沟槽。典型的绝缘体包括高密度等离子体氧化硅。在本发明的一个实施之中，用来绝缘有源器件的浅沟槽绝缘区24和浅沟槽绝缘区25同时形成。在另外一个实施例之中，浅沟槽绝缘区24和浅沟槽绝缘区25分别形成，因此浅沟槽绝缘区24的最佳厚度T1与浅沟槽绝缘区25的厚度不同。在本实施例之中，厚度T1基本上小于1μm，较佳介于0.3μm至0.4μm之间。相关领域的技术人员应理解，上述尺寸仅代表其中一个示例，相关工艺技术的尺寸可依不同需要而增减。为了简化起见，集成电路22和浅沟槽绝缘区25并未在以下的附图中再做赘述。
请参照图3B，图3B示出图3A的部分结构的俯视图。在本发明的较佳实施例之中，浅沟槽绝缘区24形成一个环绕开口26的环。其中开口26的直径D1取决于穿透硅通道的预设尺寸。在本实施例之中，直径D1基本上介于201μm至301μm之间。在其它实施例中，开口26可以是其它形状，例如方形。而在说明书全文中，直径D1也可以视为开口26的宽度。
请再参照图3A，在衬底20和浅沟槽绝缘区24上形成多晶硅平板28，并且覆盖开口26。其中多晶硅平板28的厚度T2较佳是基本上小于1μm，而更佳则是基本上介于0.3μm至0.4μm之间。
多晶硅平板28较佳是覆盖于开口26之上。因此多晶硅平板28较佳是一个具有直径D2大于开口26的直径D1的圆形平板。另外直径D2小于浅沟槽绝缘区24的外径D3，但是直径D2也可能大于外径D3。直径D1和D2的差ΔD基本上大于10μm。
请参照图4A，形成内连结构30。内连结构30包括形成并覆盖在集成电路22上的蚀刻终止层(未示出)、衬底20、浅沟槽绝缘区24以及多晶硅平板28。内层介电层32则形成于蚀刻终止层上。其中金属层间介电层34较佳是由多层堆叠于内层介电层32上方的低介电系数介电层所构成。而金属线与过孔(未示出)则形成在金属层间介电层34之中。钝化层36形成于金属层间介电层34之上。另外蚀刻终止层(未示出)可以形成在两个金属层间介电层34之间。由于内连结构30的形成工艺为本领域的公知技术，因此不在此赘述。
光刻胶40形成在内连结构30上，以图案化内连结构30而形成开口42。开口42延伸贯穿内层介电层32、金属层间介电层34和钝化层36，并将多晶硅平板28暴露于外。在开口42的形成步骤中，多晶硅平板28作为蚀刻终止层。在本发明的一个实施例之中，开口42可以通过各向异性蚀刻达到基本上笔直。在其它实施例之中，开口42可以具有从一端逐渐变窄的外形，如虚线43所示。其中倾斜角度β较佳基本上小于89°，而更佳则基本上介于87°至88°之间。而此种从一端逐渐变窄的外形可通过使用部分各向异性蚀刻及部分各向同性蚀刻来形成。
请参照图4B，图4B示出图4A的结构的俯视图。开口42较佳具有与开口26相同的形状。在本发明的较佳实施例中，开口26是圆形，因此开口42的俯视图也是圆形。开口42的直径D4较佳大于开口26的直径D1，但小于多晶硅平板28的直径D2。直径D4更佳是基本上大于直径D1约10μm。
请参照图5，在检测到多晶硅平板28已暴露出来后，蚀刻工艺转而对多晶硅平板28进行蚀刻，以暴露出衬底20和浅沟槽绝缘区24。接着继续对暴露出来的衬底20进行蚀刻，以形成如图6所示的穿透硅通道开口44。其中对衬底20和浅沟槽绝缘区24所进行的蚀刻，可以在单一步骤中进行，也可以分别进行。上述蚀刻工艺，在衬底20(及多晶硅平板28)和浅沟槽绝缘区24之间具有较高的蚀刻选择性，较佳基本上为80比1。另外可调整用来蚀刻衬底20的蚀刻剂的配方，以保持或增加其蚀刻选择性。
在本实施例之中，蚀刻选择性基本上为80比1，意即是当衬底被蚀刻80μm时浅沟槽绝缘区24只被蚀刻1μm。如图5所示，由于一部分的浅沟槽绝缘区24通过开口42暴露出来，因此如图6所示，在蚀刻衬底20的时候，浅沟槽绝缘区24暴露出来的部分也会被蚀刻。然而对浅沟槽绝缘区24所进行的蚀刻速率远小于对衬底20所进行的蚀刻速率。因此，浅沟槽绝缘区24暴露于外的部分可以视为一种硬掩膜层，用来防止位于衬底20下方的位置被蚀刻。由于具有较高的蚀刻选择性，衬底20被蚀刻的深度K1与浅沟槽绝缘区24被蚀刻的深度K2两者的比例接近上述蚀刻选择性的比值。
值得注意的是，在浅沟槽绝缘区24下方有可能产生侧蚀缺口46。然而采用基本上各向异性的蚀刻工艺可降低侧蚀缺口46的宽度W。同时多晶硅平板28也可能产生侧蚀缺口52。不过由于多晶硅平板28较薄因此限制了侧蚀缺口52的宽度。另外，由于多晶硅平板28的直径D2仅稍大于开口42的宽度D4(如图4B所示)，即使多晶硅平板28被完全蚀刻，位于多晶硅平板28中的侧蚀缺口52宽度也非常小。
请参照图7，随着蚀刻步骤的继续进行，浅沟槽绝缘区24暴露于外的余留部分48最后会被蚀穿，因此衬底20原先受到浅沟槽绝缘区24的余留部分48保护的部分会被暴露于蚀刻步骤中。在本实施例中，由于浅沟槽绝缘区24的厚度T1基本上为0.3μm，而蚀刻选择性为80比1。当浅沟槽绝缘区24被完全蚀穿时，穿透硅通道开口44的深度K1大约为80×0.3μm，大约等于24μm。若在浅沟槽绝缘区24被完全蚀穿之后，仍继续对衬底20进行蚀刻，穿透硅通道开口44的深度K1将会增加。与此同时，衬底20被遮盖的部分也会被逐渐蚀刻，结果使得穿透硅通道开口44最后具有由上而下逐渐变窄的外形。穿透硅通道开口44的侧壁的倾斜角度α较佳基本上介于87°到88°之间。而倾斜角度α可通过改变宽度(直径)D1、D2和D4以及改变蚀刻剂配方的方式来进行调整。相关领域的技术人员可通过实验找到最佳的参数值。
当浅沟槽绝缘区24的余留部分48(请参照图6)被基本上完全蚀刻之后，先前所形成的侧蚀缺口46会被消除，而完全并入穿透硅通道开口44。这将大幅地降低整体结构中侧蚀缺口的宽度。结果形成穿透硅通道开口44逐渐变窄的预设外形，并大幅改善侧蚀缺口的现象。当穿透硅通道开口44形成之后，即移除光刻胶40。
请参照图8，图8示出填充开口42和穿透硅通道开口44之后的结构剖面图。较佳先形成扩散阻挡层60，以覆盖于开口42和穿透硅通道开口44的侧壁以及穿透硅通道开口44的底部。然后在扩散阻挡层60上形成较佳为含铜的种子层(未示出)。其中扩散阻挡层60采用物理气相沉积技术形成，种子层也可以采用物理气相沉积或电镀技术来构成。由于穿透硅通道开口44具有从一端逐渐变窄的外形，并且降低了侧蚀缺口的现象，因此有助于使扩散阻挡层60和种子层的覆盖更为平均(与开口42和穿透硅通道开口44更加共形)。
接着，较佳采用电镀技术，以铜填充开口42和穿透硅通道开口44剩余未填满的部分。因而在衬底20之中形成穿透硅通道64，同时在内层介电层32、金属层间介电层34和钝化层36中形成金属柱66。由于扩散阻挡层60和种子层的覆盖较为平均，因此较多的电镀电流可被传导到穿透硅通道开口44较低的部分，因此大幅降低穿透硅通道64中形成孔洞的机会。
如图9所示，将衬底20的背面抛光，以露出穿透硅通道64然后进行封装工艺。
请再参照图3A，根据上述实施例所教示的内容，平板28可由非多晶硅材料所构成，以提供平板28和浅沟槽绝缘区24、内层介电层32、金属层间介电层34及钝化层36等介电结构之间较大的蚀刻选择性。形成平板28的典型材料包括氮化硅薄膜及复合金属硅化物。
虽然本发明已以较佳实施例揭露如上，然其并非用以限定本发明，任何相关技术领域的普通技术人员，在不脱离本发明的精神和范围内，当可作各种的改变与变形，因此本发明的保护范围当以后附的权利要求书所界定的为准。

Claims (14)

1、一种集成电路结构，包括：
衬底；
穿透硅通道，位于该衬底之内，其中该穿透硅通道从一端逐渐变窄；
硬掩膜，由该衬底的上表面延伸进入该衬底，其中该硬掩膜环绕该穿透硅通道的上方部分；
多个介电层，位于该衬底上方；以及
金属柱，由该介电层的上表面延伸至该穿透硅通道，其中该金属柱包括与该穿透硅通道的填充材料相同的材料。
2、根据权利要求1所述的集成电路结构，其特征在于，还包括环形的蚀刻终止层，位于该介电层与该硬掩膜之间，其中该蚀刻终止层仅环绕该金属柱的下方部分。
3、根据权利要求2所述的集成电路结构，其特征在于，该蚀刻终止层是多晶硅层，且该衬底是硅衬底。
4、根据权利要求1所述的集成电路结构，其特征在于，该硬掩膜的厚度小于该穿透硅通道的高度。
5、根据权利要求1所述的集成电路结构，其特征在于，该硬掩膜的厚度小于1μm。
6、根据权利要求1所述的集成电路结构，其特征在于，该穿透硅通道的侧壁具有小于90°的倾斜角度。
7、根据权利要求1所述的集成电路结构，其特征在于，还包括一浅沟槽绝缘区，用来绝缘多个有源器件，其中该硬掩膜与该浅沟槽绝缘区具有相同的厚度，并且由相同材料所构成。
8、根据权利要求1所述的集成电路结构，其特征在于，该金属柱的侧壁从一端逐渐变窄，且该金属柱上方部分的宽度大于该金属柱下方部分的宽度。
9、一种集成电路结构，包括：
衬底；
浅沟槽绝缘区，由该衬底的上表面向该衬底内部延伸，且该浅沟槽绝缘区形成一环；
多晶硅环，位于该浅沟槽绝缘区上；
多个低介电系数介电层，位于该衬底与该多晶硅环之上；以及
导电结构，由该低介电系数介电层的上表面延伸进入该衬底，其中该导电结构包括位于该低介电系数介电层之中的第一部分，以及贯穿该多晶硅环和该浅沟槽绝缘区所形成的环的第二部分。
10、根据权利要求9所述的集成电路结构，其特征在于，该第二部分的外形从一端逐渐变窄，且该第二部分的上方部分的宽度大于该第二部分的下方部分的宽度。
11、根据权利要求9所述的集成电路结构，其特征在于，该导电结构的该第二部分具有一高度，该高度大于该浅沟槽绝缘区的厚度。
12、根据权利要求9所述的集成电路结构，其特征在于，该浅沟槽绝缘区的厚度小于1μm，且该多晶硅环的厚度小于1μm。
13、根据权利要求9所述的集成电路结构，其特征在于，该多晶硅环的内侧侧壁与该浅沟槽绝缘区的内侧侧壁连续相连。
14、根据权利要求9所述的集成电路结构，其特征在于，该多晶硅环和该浅沟槽绝缘区均是圆环。
CN2008100840386A 2007-05-16 2008-03-18 集成电路结构 Active CN101308834B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/803,783 2007-05-16
US11/803,783 US7564115B2 (en) 2007-05-16 2007-05-16 Tapered through-silicon via structure

Publications (2)

Publication Number Publication Date
CN101308834A true CN101308834A (zh) 2008-11-19
CN101308834B CN101308834B (zh) 2012-01-04

Family

ID=40026661

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2008100840386A Active CN101308834B (zh) 2007-05-16 2008-03-18 集成电路结构

Country Status (2)

Country Link
US (2) US7564115B2 (zh)
CN (1) CN101308834B (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102693910A (zh) * 2011-03-23 2012-09-26 上海华虹Nec电子有限公司 沟槽的干法刻蚀方法
CN102832200A (zh) * 2011-06-15 2012-12-19 台湾积体电路制造股份有限公司 半导体结构及其形成方法
CN101783329B (zh) * 2009-01-13 2013-08-14 台湾积体电路制造股份有限公司 半导体元件及其制法
CN103262232A (zh) * 2010-11-12 2013-08-21 吉林克斯公司 具有经改善可靠度的直通硅晶穿孔
CN104067383A (zh) * 2012-01-13 2014-09-24 高通股份有限公司 将贯穿基板通孔集成到集成电路的中段工序层中
TWI456729B (zh) * 2011-11-29 2014-10-11 Advanced Semiconductor Eng 具有屏蔽導通柱之半導體元件及其製造方法
CN102598254B (zh) * 2009-10-23 2015-04-15 新思科技有限公司 用于硅通孔的esd/天线二极管

Families Citing this family (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090093113A1 (en) * 2007-10-03 2009-04-09 John Flake Electrochemical etching of through silicon vias
US8299605B2 (en) 2007-11-14 2012-10-30 International Business Machines Corporation Carbon nanotube structures for enhancement of thermal dissipation from semiconductor modules
KR101374338B1 (ko) * 2007-11-14 2014-03-14 삼성전자주식회사 관통 전극을 갖는 반도체 장치 및 그 제조방법
US8227902B2 (en) * 2007-11-26 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Structures for preventing cross-talk between through-silicon vias and integrated circuits
US7859114B2 (en) * 2008-07-29 2010-12-28 International Business Machines Corporation IC chip and design structure with through wafer vias dishing correction
US8166651B2 (en) 2008-07-29 2012-05-01 International Business Machines Corporation Through wafer vias with dishing correction methods
KR101002680B1 (ko) 2008-10-21 2010-12-21 삼성전기주식회사 반도체 패키지 및 그 제조 방법
US20100127344A1 (en) * 2008-11-21 2010-05-27 Texas Instruments Incorporated Contact over isolator
US7923369B2 (en) * 2008-11-25 2011-04-12 Freescale Semiconductor, Inc. Through-via and method of forming
US7825024B2 (en) * 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7985655B2 (en) * 2008-11-25 2011-07-26 Freescale Semiconductor, Inc. Through-via and method of forming
US8053902B2 (en) * 2008-12-02 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for protecting dielectric layers from degradation
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US20100171197A1 (en) 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US8704375B2 (en) * 2009-02-04 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier structures and methods for through substrate vias
TWI447881B (zh) * 2009-03-09 2014-08-01 United Microelectronics Corp 矽貫通電極結構及其製法
US9406561B2 (en) * 2009-04-20 2016-08-02 International Business Machines Corporation Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
US8791549B2 (en) 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
DE102009049102B4 (de) 2009-10-13 2012-10-04 Austriamicrosystems Ag Halbleiterbauelement mit Durchkontaktierung und Verfahren zur Herstellung einer Durchkontaktierung in einem Halbleiterbauelement
JP5532394B2 (ja) 2009-10-15 2014-06-25 セイコーエプソン株式会社 半導体装置及び回路基板並びに電子機器
US8242604B2 (en) * 2009-10-28 2012-08-14 International Business Machines Corporation Coaxial through-silicon via
US8466059B2 (en) 2010-03-30 2013-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for stacked dies
US9293366B2 (en) 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US8603917B2 (en) * 2010-10-28 2013-12-10 Agency For Science, Technology And Research Method of processing a wafer
US9190371B2 (en) 2010-12-21 2015-11-17 Moon J. Kim Self-organizing network with chip package having multiple interconnection configurations
US8410580B2 (en) * 2011-01-12 2013-04-02 Freescale Semiconductor Inc. Device having conductive substrate via with catch-pad etch-stop
TWI456726B (zh) 2011-01-24 2014-10-11 Ind Tech Res Inst 內連線結構、具有該內連線結構的裝置與線路結構、及防護內連線結構電磁干擾（ｅｍｉ）的方法
US8987140B2 (en) 2011-04-25 2015-03-24 Applied Materials, Inc. Methods for etching through-silicon vias with tunable profile angles
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8519516B1 (en) * 2012-03-12 2013-08-27 Micron Technology, Inc. Semiconductor constructions
KR101934045B1 (ko) 2012-03-22 2019-01-02 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9105628B1 (en) 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US9269664B2 (en) * 2012-04-10 2016-02-23 Mediatek Inc. Semiconductor package with through silicon via interconnect and method for fabricating the same
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US9577035B2 (en) * 2012-08-24 2017-02-21 Newport Fab, Llc Isolated through silicon vias in RF technologies
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US9799592B2 (en) * 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9406588B2 (en) 2013-11-11 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US10340203B2 (en) 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same
US9646918B2 (en) * 2014-08-14 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9431351B2 (en) 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9659863B2 (en) 2014-12-01 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, multi-die packages, and methods of manufacture thereof
US9318376B1 (en) 2014-12-15 2016-04-19 Freescale Semiconductor, Inc. Through substrate via with diffused conductive component
US9502272B2 (en) 2014-12-29 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods of packaging semiconductor devices
US10319701B2 (en) 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
US9601410B2 (en) 2015-01-07 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9633958B2 (en) 2015-01-30 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad surface damage reduction in a formation of digital pattern generator
US10163709B2 (en) 2015-02-13 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US10340258B2 (en) 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9536865B1 (en) 2015-07-23 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection joints having variable volumes in package structures and methods of formation thereof
US9570431B1 (en) 2015-07-28 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer for integrated packages
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US9691695B2 (en) 2015-08-31 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure
US10644229B2 (en) 2015-09-18 2020-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory cell and fabricating the same
US10269682B2 (en) 2015-10-09 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cooling devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9659878B2 (en) 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US10163856B2 (en) 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9911623B2 (en) 2015-12-15 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Via connection to a partially filled trench
US10121812B2 (en) * 2015-12-29 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked substrate structure with inter-tier interconnection
US9589941B1 (en) 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
US9741669B2 (en) 2016-01-26 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Forming large chips through stitching
US10050018B2 (en) 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US9842829B2 (en) 2016-04-29 2017-12-12 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US9859258B2 (en) 2016-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10147704B2 (en) 2016-05-17 2018-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing thereof
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US9881903B2 (en) 2016-05-31 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with epoxy flux residue
US9875982B2 (en) 2016-06-01 2018-01-23 Taiwan Semiconductor Manufacturing Company Ltd Semiconductor device and manufacturing method thereof
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US10115675B2 (en) 2016-06-28 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Packaged semiconductor device and method of fabricating a packaged semiconductor device
US10685911B2 (en) 2016-06-30 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9941186B2 (en) 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
US20180005887A1 (en) * 2016-06-30 2018-01-04 International Business Machines Corporation Through-silicon via with injection molded fill
US10163805B2 (en) 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9893046B2 (en) 2016-07-08 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Thinning process using metal-assisted chemical etching
US9875972B1 (en) 2016-07-14 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9870975B1 (en) 2016-07-14 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package with thermal dissipation structure and method for forming the same
US10269732B2 (en) 2016-07-20 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info package with integrated antennas or inductors
US10332841B2 (en) 2016-07-20 2019-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming the same
US10157885B2 (en) 2016-07-29 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having magnetic bonding between substrates
US10720360B2 (en) 2016-07-29 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die singulation and structures formed thereby
KR102652854B1 (ko) * 2016-08-17 2024-04-02 삼성전자주식회사 반도체 소자 및 그 제조 방법
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US10535632B2 (en) 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US10049981B2 (en) 2016-09-08 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Through via structure, semiconductor device and manufacturing method thereof
US10170429B2 (en) 2016-11-28 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming package structure including intermetallic compound
US10153320B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of forming the same
US10153218B2 (en) 2016-11-29 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10879183B2 (en) 2018-06-22 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11172142B2 (en) 2018-09-25 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor for sensing LED light with reduced flickering
US11201122B2 (en) 2018-09-27 2021-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating semiconductor device with reduced warpage and better trench filling performance
US10923397B2 (en) 2018-11-29 2021-02-16 Globalfoundries Inc. Through-substrate via structures in semiconductor devices
US11133304B2 (en) 2019-11-27 2021-09-28 Taiwan Semiconductor Manufacturing Co., Ltd. Packaging scheme involving metal-insulator-metal capacitor
KR20220010852A (ko) 2020-07-20 2022-01-27 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US11355464B2 (en) * 2020-11-10 2022-06-07 Nanya Technology Corporation Semiconductor device structure with bottle-shaped through silicon via and method for forming the same
US11817373B2 (en) * 2021-03-26 2023-11-14 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and method of making

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5545581A (en) * 1994-12-06 1996-08-13 International Business Machines Corporation Plug strap process utilizing selective nitride and oxide etches
TW412845B (en) * 1997-10-13 2000-11-21 Fujitsu Ltd Semiconductor device having a fuse and a fabrication process thereof
US6448657B1 (en) * 1999-04-21 2002-09-10 Applied Materials, Inc. Structure for reducing junction spiking through a wall surface of an overetched contact via
US6399474B1 (en) * 2000-06-28 2002-06-04 Advanced Micro Devices, Inc. Method and apparatus for precoining BGA type packages prior to electrical characterization
US6835977B2 (en) * 2002-03-05 2004-12-28 United Microelectronics Corp. Variable capactor structure
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7271482B2 (en) * 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7264986B2 (en) * 2005-09-30 2007-09-04 Freescale Semiconductor, Inc. Microelectronic assembly and method for forming the same
US7799678B2 (en) * 2008-01-30 2010-09-21 Freescale Semiconductor, Inc. Method for forming a through silicon via layout

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101783329B (zh) * 2009-01-13 2013-08-14 台湾积体电路制造股份有限公司 半导体元件及其制法
CN102598254B (zh) * 2009-10-23 2015-04-15 新思科技有限公司 用于硅通孔的esd/天线二极管
CN103262232A (zh) * 2010-11-12 2013-08-21 吉林克斯公司 具有经改善可靠度的直通硅晶穿孔
CN103262232B (zh) * 2010-11-12 2015-12-09 吉林克斯公司 具有经改善可靠度的直通硅晶穿孔
CN102693910A (zh) * 2011-03-23 2012-09-26 上海华虹Nec电子有限公司 沟槽的干法刻蚀方法
CN102832200A (zh) * 2011-06-15 2012-12-19 台湾积体电路制造股份有限公司 半导体结构及其形成方法
TWI456729B (zh) * 2011-11-29 2014-10-11 Advanced Semiconductor Eng 具有屏蔽導通柱之半導體元件及其製造方法
CN104067383A (zh) * 2012-01-13 2014-09-24 高通股份有限公司 将贯穿基板通孔集成到集成电路的中段工序层中
CN104067383B (zh) * 2012-01-13 2017-04-12 高通股份有限公司 将贯穿基板通孔集成到集成电路的中段工序层中

Also Published As

Publication number Publication date
US20080283959A1 (en) 2008-11-20
US20090269905A1 (en) 2009-10-29
US7564115B2 (en) 2009-07-21
US7816227B2 (en) 2010-10-19
CN101308834B (zh) 2012-01-04

Similar Documents

Publication Publication Date Title
CN101308834B (zh) 集成电路结构
CN105280610B (zh) 3dic互连器件及其形成方法
US7772123B2 (en) Through substrate via semiconductor components
US7943470B2 (en) Chip-stacked semiconductor device and manufacturing method thereof
US6211561B1 (en) Interconnect structure and method employing air gaps between metal lines and between metal layers
JP5802515B2 (ja) 半導体装置及びその製造方法
US20070134819A1 (en) Semiconductor device and method of manufacturing the same
US8741768B2 (en) Method for reducing dielectric overetch when making contact to conductive features
US9953857B2 (en) Semiconductor device with buried local interconnects
US20160064362A1 (en) Semiconductor Device Package and Methods of Packaging Thereof
US20050239279A1 (en) Integrated circuits including spacers that extend beneath a conductive line and methods of fabricating the same
US8431485B2 (en) Manufacturing method for a buried circuit structure
US8674404B2 (en) Additional metal routing in semiconductor devices
US20230387237A1 (en) Semiconductor devices
CN116779530A (zh) 半导体结构及其制作方法
CN110707068A (zh) 半导体互连结构及其制备方法
CN115083999A (zh) 半导体结构及半导体结构的制作方法
US6776622B2 (en) Conductive contact structure and process for producing the same
EP4084053B1 (en) Semiconductor structure and its method for manufacturing
US20230178422A1 (en) Liner-less via contact
TWI761223B (zh) 動態隨機存取記憶體及其製造方法
CN104078416A (zh) 硅通孔布局结构、硅通孔互联结构的形成方法
CN111384001A (zh) 一种半导体器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant