CN101393871B - 层积半导体芯片的半导体装置制造方法 - Google Patents

层积半导体芯片的半导体装置制造方法 Download PDF

Info

Publication number
CN101393871B
CN101393871B CN2008101455117A CN200810145511A CN101393871B CN 101393871 B CN101393871 B CN 101393871B CN 2008101455117 A CN2008101455117 A CN 2008101455117A CN 200810145511 A CN200810145511 A CN 200810145511A CN 101393871 B CN101393871 B CN 101393871B
Authority
CN
China
Prior art keywords
film
forms
electrode
semiconductor device
dielectric film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2008101455117A
Other languages
English (en)
Other versions
CN101393871A (zh
Inventor
臼井良辅
水原秀树
中村岳史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN101393871A publication Critical patent/CN101393871A/zh
Application granted granted Critical
Publication of CN101393871B publication Critical patent/CN101393871B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step

Abstract

一种层积半导体芯片的半导体装置及其制造方法。其在电极膜表面形成粘合膜，再在其上形成覆盖膜。粘合膜的构成材料使用镍、铬、钼、钨、铝及这些金属的合金等。覆盖膜的材料使用金、银、白金及这些金属的合金等。

Description

层积半导体芯片的半导体装置制造方法
本申请为三洋电机株式会社于2004年9月30日向中国专利局提交的题为“层积半导体芯片的半导体装置及其制造方法”的申请号为200410083359.6的中国专利申请的分案申请。 
技术领域
本发明涉及搭载半导体芯片的半导体装置及其制造方法。
背景技术
在手机、PDA、DVC、DSC这样的便携式电子设备加速高功能化中，要使这样的产品被市场接受必须使将其小型、轻量化，为此，对高集成系统LSI的要求越来越高。另一方面对这些电子设备又要求使用更加便利，对用于设备中的LSI要求高功能、高性能化。因此，随着LSI芯片的高集成化，其I/O数量增加，也增强了对封装件自身小型化的要求，为同时满足上述这两方面的要求，而强烈要求开发出适用于半导体部件的高密度衬底安装的半导体封装件。为满足这样的要求，开发被称为CSP(Chip Size Package)的各种封装技术。
这样封装件例如可知BGA(Ball Grid Array)。在BAG中，在封装用衬底上安装半导体芯片，在将其树脂模制后，在相反侧的面上以区域状(エリア状)形成作为外部端子的焊锡球。在BGA中，由于安装区域以面形成，故可较容易地将封装件小型化。另外，即使在电路衬底侧也不必对应狭缝，也不需要高精度的安装技术，故当使用BGA时，即使在封装件成本稍微高时，也可以降低整体的安装成本。
图1是表示例如特开平7-183426号公报中公开的一般BGA的结构示意图。BGA100具有介由粘接层108将LSI芯片102搭载在玻璃环氧树脂衬底106上的结构。LSI芯片102用密封树脂110进行模制。利用金属线104将LSI芯片102和玻璃环氧树脂衬底106电连接。在玻璃环氧树脂衬底106的背面以阵列状排列焊球112。介由该焊球112将BGA100安装在印刷线路 板上。
在这样的封装件中，半导体芯片和配线层利用引线结合方式或倒装法连接。即，在配线层的最上部设置由金属膜成的垫片电极，利用规定的导电部件即金属线或焊锡等将该垫片电极和半导体芯片的垫片电极连接。降低该连接位置的电阻和稳定地提高连接强度，在提高合格品率及元件可靠性基础上成为又一重要技术课题。
专利文献
特开平7-183426号公报
通过封装件形成工艺有时不能充分得到该连接部分的电阻或强度。本发明者根据研究确定，特别是在配线层上形成元件的工序中，当采用含有等离子处理工序时，常常产生引线结合等的不合格现象。
本发明是鉴于上述问题点而开发的，其目的在于，抑制半导体封装件的半导体芯片和配线层的连接不良，提高元件可靠性及合格品率。
发明内容
关于引起半导体芯片和配线层的连接不良的主要原因，本发明者进行了专心的研讨。其结果可知，在配线层上部搭载元件的工序中，若实施使等离子处理等金属表面改性的工序，垫片电极表面改性，连接强度降低。本发明是基于此研发的。
即，本发明提供一种半导体装置的制造方法，其特征在于，包括如下工序：准备含有导电路的基件；形成覆盖基件至少一部分的绝缘膜，同时在基件的表面或绝缘膜的表面形成连接导电路的垫片电极；在绝缘膜的表面及垫片电极的表面露出的状态下进行等离子处理。形成垫片电极的工序包含如下工序：在绝缘膜上形成电极膜的工序；以覆盖电极膜的方式形成粘合膜的工序；以覆盖粘合膜的方式形成覆盖膜的工序。
另外，本发明提供一种半导体装置的制造方法，其特征在于，包括如下工序：准备含有导电路的基件的工序；形成覆盖基件至少一部分的绝缘膜，同时在基件的表面或绝缘膜的表面形成连接导电路的垫片电极的工序；在绝缘膜上形成元件的工序；在绝缘膜的表面、垫片电极和元件的表面露出的状态下进行等离子处理的工序。形成垫片电极的工序包含如下工序：在绝缘膜上形成电极膜的工序；以覆盖电极膜的方式形成粘合膜的工序；以覆盖粘合 膜的方式形成覆盖膜的工序。
根据本发明，由于在垫片电极表面设有导电性保护膜，故可抑制垫片电极表面的劣化。
在该半导体装置的制造方法中，所述元件至少为半导体芯片或无源元件。
另外，该半导体装置的制造方法中，通过进行等离子处理，在绝缘膜的表面形成微小突起群。
另外，该半导体装置的制造方法中，通过进行所述等离子处理，在元件的表面形成微小突起群。
根据本发明，利用该等离子处理也可以形成在绝缘膜表面形成微小突起群的结构。通过等离子处理绝缘膜表面提高和形成于其上部的膜的粘接性，但相反，存在着垫片电极表面发生劣化、半导体芯片和配线层接触不良的问题。根据上述结构，由于可通过导电性保护膜来抑制垫片电极表面的劣化，故可解决上述问题。
附图说明
图1是现有技术的封装件的结构图；
图2是ISB(注册商标)的结构图；
图3A、图3B是BGA及ISB(注册商标)的制造工序图；
图4是实施例的半导体装置的结构图；
图5A、图5B、图5C是实施例的半导体装置的制造方法的图；
图6A、图6B是实施例的半导体装置的制造方法的图；
图7A、图7B、图7C是实施例的半导体装置的制造方法的图。
具体实施方式
以下，说明本发明的实施方式，首先说明实施例采用的ISB结构。ISB(Integrated System in Board；注册商标)是根据本申请开发的特有的封装件。在以半导体裸片为核芯的电路封装件中，ISB是具有铜形成的配线图案的同时不使用支承电路元件的芯子(基件)的特有的无芯系统内装式封装件。
图2是表示ISB的一例的结构示意图。在此，为便于理解ISB的整体结构，仅表示一个配线层，但实际上是多个配线层层积的结构。该ISB是通过由铜图案205构成的配线将LSI裸片201、Tr裸片202及片状CR203连接的 结构。LSI裸片201通过金属结合线204导通引出电极和配线。在LSI裸片201的正下方设置导电膏206，介由该导电膏将ISB安装在印刷线路板上。ISB整体由用环氧树脂等构成的树脂封装层207密封。另外，该图中表示的是具有单层配线层的结构，也可采用多层配线结构。
图3是现有CSP和本发明ISB的制造工序对比图。图3A是表示现有CSP的制造工序。首先，在衬底上形成框架，在各框架划分的元件形成区域安装芯片。然后，对各元件通过热硬性树脂设置密封层，然后，利用模型冲切成各个元件。在最终工序的冲切中，模制树脂及衬底一起切断，存在切断面具有表面起毛等问题。另外，由于完成冲切后大量产生下脚料，存在不利于环保的问题。
另一方面，图3B是ISB制造工序图。首先，在金属箔上设置框架，在各模块形成区域形成配线图案，在其上搭载LSI等电路元件。然后，在每个模块上施行封装，沿划线区域进行切割，得到制品。由于在封装完成后划线工序前除去形成基底的金属箔，故在划线工序的切割中，仅切断树脂层。因此，可抑制切断面起毛，提高切割的准确性。
在采用ISB的结构时，得到如下优点。
(i)由于可采用无芯安装，故可实现晶体管、IC、LSI的小型、薄型化。
(ii)由于可由晶体管电路形成(回路形成)系统LSI，乃至电路形成片型电容和电阻，将其封装，故可实现高度SIP(System in Package)。
(iii)由于可组合现有的半导体芯片，故可在短时间内开发系统LSI。
(iv)在单层ISB结构中，半导体裸片被直接安装在正下方的铜材料上，可得到良好的放热性。
(v)由于电路配线是铜材料而没有芯件，故形成低电容率的电路配线，可在高数据传输或高频电路中发挥优良的特性。
(vi)由于电极埋入封装层内部，故可抑制电极材料产生粒子污染。
(vii)由于封装尺寸自由，当将每个下脚料和64引脚的SQFP封装件比较时，为大约1/10的量，故可降低对环境的影响。
(viii)可实现从搭载部件的印刷电路衬底向功能型电路衬底的新概念系统结构。
(ix)由于IBS的图案设计和印刷电路衬底的图案设计一样地容易，故设备制造厂的工程师可自行设计。
以下，参照附图说明本发明的实施方式。
以下，以具有上述的ISB结构的半导体装置为例说明本发明的最优实施方式。图4是表示本实施例的半导体装置的剖面结构图。该半导体装置，把由层间绝缘膜405、层间绝缘膜406及铜构成的配线407构成的多个配线层形成层积层，由最上层形成抗焊料剂层408的多层配线结构体和其表面形成的元件410a及电路元件410b形成。在多层配线结构体的背面设置焊锡球420。元件410a和电路元件410b由模制树脂415模制。
垫片电极460和配线407电连接。通过金线470将垫片电极460和元件410a引线结合，以倒装法将垫片电极460和元件410b连接。垫片电极460由铜膜和由在其表面形成的导电材料构成的等离子保护膜构成。后述等离子保护膜的结构。
构成抗焊料剂层408、层间绝缘膜405及模制树脂415的材料可分别单独选择树脂材料，例如，BT树脂等蜜胺电介质、液晶聚合物、环氧树脂、PPE树脂、聚酰亚胺树脂、酚醛树脂、聚酰胺双马来酰亚胺等热硬性树脂。其中，最好使用高频特性优良的液晶聚合物、环氧树脂、BT树脂等蜜胺电介质。也可以和这些树脂一起适量地添加填充物或添加剂。
其次，参照图5～图7说明图4所示的半导体装置的制造方法。首先，如图5A所示，在金属箔400上的规定表面上设置通孔404，并在其位置有选择地形成导电覆膜402。具体地说，在由光致抗蚀剂401覆盖金属箔400后，利用电解镀敷法在金属箔400的露出面上形成导电覆膜402。导电覆膜402的膜厚为例如1～10μm程度。由于该导电覆膜402最终成为半导体装置的背面电极，故最好使用与焊锡等焊材的粘接性优良的金或银形成。
如图5B所示，在金属箔400上形成第一层配线图案。首先，化学研磨金属箔400，进行表面的清洗和表面粗化。其次，在金属箔400上由热硬性树脂覆盖导电覆膜402的整个面，并使其加热硬化，形成具有平坦表面的膜。然后，在该膜中形成到达导电覆膜402的直径100μm左右的通孔。作为设置通孔的方法，在本实施例中使用激光加工，但也可以使用机械加工、药液的化学蚀刻加工、等离子的干蚀法等。之后，在利用激光照射除去蚀刻渣滓后，整面形成填埋通孔404的铜涂敷层。然后，以光致抗蚀剂401为掩膜，蚀刻铜涂敷层，形成由铜构成的配线407。例如，可在从抗蚀剂露出的位置喷涂化学蚀刻液，蚀刻除去不要的铜箔，形成配线图案。
如上所述，通过反复顺次进行形成层间绝缘膜405、通孔、铜涂敷层及铜涂敷层的图案的工序，如图5C所示，形成层积配线407及由层间绝缘膜405、406构成的配线层的多层配线结构。
然后，如图6A所示，形成垫片电极460和在该垫片电极460的形成区域具有开口部的抗焊料剂层408，并在抗焊料剂层408上形成元件410a及电路元件410b。抗焊料剂层408由焊锡等耐热性优良的绝缘材料构成。例如，可使用环氧树脂等。元件410a及电路元件410b可使用晶体管、二极管、IC芯片等半导体芯片或片状电容、片状电阻等无源元件。另外，也可以安装CPS、BGA等倒装的半导体元件。在本实施例中，元件410a是半导体裸片(晶体管芯片)，电路元件410b是片状电容。这些被固定在光致抗蚀剂层408上。
参照图7说明图6A所示结构的形成工序。首先，在层间绝缘膜406上形成铜膜后，进行图案形成，形成电极膜462。然后，采用选择涂敷法在电极膜462的表面形成粘合膜464，在其上还形成覆盖膜466。粘合膜464的材料例如镍、铬、钼、钨、铝及这些金属的合金等。覆盖膜466的材料例如金、银、铂及这些金属的合金等。每个膜是单层多层皆可。其次，在层间绝缘膜406的表面粘贴光致抗蚀剂片，通过热压形成光致抗蚀剂层408。然后，进行曝光及显影，使形成电极膜462的位置开口。在电极膜462侧壁和光致抗蚀剂层408开口部内壁之间设置缝隙部。另外，在本实施例中，使用环氧树脂片形成环氧树脂的光致抗蚀剂层408，但不限于此，也可以使用各种材料。
在电极膜462为铜或铜铝合金时，作为最好的粘合膜464和覆盖膜466组合，例如由镍构成的粘合膜464及由金构成的覆盖膜466。在本实施例中使用该组合。
这样，在电极膜462上形成垫片电极460，该垫片电极460形成以层积粘合膜464→覆盖膜466这样的顺序形成的等离子保护膜。在该结构中，覆盖膜466有助于提高等离子的耐性，粘合膜464有助于提高覆盖膜466和电极膜462的粘接性。如上所述，可得到图6A所示的结构。
然后，在图6A的状态下进行等离子处理。等离子照射的条件对应使用的树脂材料适宜设定，以形成上述的微小突起。另外，最好不对衬底施加偏压。例如，为如下条件。
偏压：不施加
等离子气体：氩气10～20sccm、氧气0～10sccm
通过该等离子照射净化配线407的表面，将光致抗蚀剂层408的表面改性，同时将由聚酰亚胺保护膜构成的元件410的表面改性，在这些表面上形成微小突起。在光致抗蚀剂层408的表面及元件410的表面形成平均直径1～10nm、数密度1×103μm-2左右的微小突起群。
其次，如图6B所示，在使用金属线470将元件410a和垫片电极460引线结合后，利用模制树脂415将这些进行模制。图6B表示模制的状态。半导体元件的模制相对设于金属箔400上的多个模块使用模型同时进行。该工序可通过传递模、注入模、浇注或浸渍来实现。作为树脂材料，环氧树脂等热硬性树脂可通过传递模或浇注来实现，聚酰亚胺树脂、聚苯硫化物等热塑性树脂可通过注入模来实现。
然后，从图6B的状态除去金属箔400，在背面形成焊锡球。金属箔400的除去可通过研磨、研削、蚀刻、激光金属蒸发等进行。在本实施例中采用以下方法。即，利用研磨装置或研削装置将金属箔400的整个面研削50μm左右，并利用化学湿蚀除去残留的金属箔400。另外，也可以利用湿蚀除去整个金属箔400。通过这样的工序，在和搭载半导体元件侧相对的一侧的面上形成露出第一层配线407的背面的结构。由此，由本实施例得到的模块的背面形成得平坦，在安装半导体装置时，利用焊锡等表面张力就这样水平移动，得到可容易地自调整这样工艺上的优点。
其次，在通过除去金属箔400露出的导电覆膜402上覆盖焊锡等导电材料，形成焊锡球420，通过切割完成图4所示的半导体装置。然后，通过切割切断晶片，得到半导体装置芯片。直至进行到上述的金属箔400的除去工序，金属箔400形成支承衬底。金属箔400也可以在配线407形成时的电镀工序中用作电极。另外，在将模制树脂415模制时，向模型搬运安装的作业性良好。
本实施例的半导体模块在图6A的工序中，进行氩等离子处理，将光致抗蚀剂层408表面及元件410表面改性，形成微小突起。因此，这些和模制树脂415之间的界面粘接性明显得以改善，提高合格品率及元件可靠性。
另外，由于即使进行这样的等离子处理，垫片电极460的表面也不劣化，故可抑制引线结合工序中的半导体芯片和配线层的连接不良等产生，实现高 的可靠性和良好的合格品率。
以上，参照附图叙述了本发明的实施方式，这些是本发明的示例，但也可以采用上述以外的各种结构。

Claims (5)

1.一种半导体装置的制造方法，其特征在于，包括如下工序：准备含有导电路的基件的工序；形成覆盖所述基件至少一部分的绝缘膜，同时在所述基件的表面或所述绝缘膜的表面形成连接所述导电路的垫片电极的工序；在所述绝缘膜的表面及所述垫片电极的表面露出的状态下进行等离子处理的工序，
形成所述垫片电极的工序包含如下工序：在所述绝缘膜上形成电极膜的工序；以覆盖所述电极膜的方式形成粘合膜的工序；以覆盖所述粘合膜的方式形成覆盖膜的工序。
2.一种半导体装置的制造方法，其特征在于，包括如下工序：准备含有导电路的基件的工序；形成覆盖所述基件至少一部分的绝缘膜，同时在所述基件的表面或所述绝缘膜的表面形成连接所述导电路的垫片电极的工序；在所述绝缘膜上形成元件的工序；在所述绝缘膜的表面、所述垫片电极和所述元件的表面露出的状态下进行等离子处理的工序，
形成所述垫片电极的工序包含如下工序：在所述绝缘膜上形成电极膜的工序；以覆盖所述电极膜的方式形成粘合膜的工序；以覆盖所述粘合膜的方式形成覆盖膜的工序。
3.如权利要求2所述的半导体装置的制造方法，其特征在于，所述元件至少为半导体芯片或无源元件。
4.如权利要求1或2所述的半导体装置的制造方法，其特征在于，通过进行所述等离子处理，在所述绝缘膜的表面形成微小突起群。
5.如权利要求2所述的半导体装置的制造方法，其特征在于，通过进行所述等离子处理，在所述元件的表面形成微小突起群。
CN2008101455117A 2003-09-30 2004-09-30 层积半导体芯片的半导体装置制造方法 Expired - Fee Related CN101393871B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003339123A JP3877717B2 (ja) 2003-09-30 2003-09-30 半導体装置およびその製造方法
JP339123/03 2003-09-30

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100833596A Division CN100421249C (zh) 2003-09-30 2004-09-30 层积半导体芯片的半导体装置及其制造方法

Publications (2)

Publication Number Publication Date
CN101393871A CN101393871A (zh) 2009-03-25
CN101393871B true CN101393871B (zh) 2011-07-13

Family

ID=34373339

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2008101455117A Expired - Fee Related CN101393871B (zh) 2003-09-30 2004-09-30 层积半导体芯片的半导体装置制造方法
CNB2004100833596A Expired - Fee Related CN100421249C (zh) 2003-09-30 2004-09-30 层积半导体芯片的半导体装置及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CNB2004100833596A Expired - Fee Related CN100421249C (zh) 2003-09-30 2004-09-30 层积半导体芯片的半导体装置及其制造方法

Country Status (5)

Country Link
US (3) US7405484B2 (zh)
JP (1) JP3877717B2 (zh)
KR (1) KR100644311B1 (zh)
CN (2) CN101393871B (zh)
TW (1) TWI248140B (zh)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6905914B1 (en) 2002-11-08 2005-06-14 Amkor Technology, Inc. Wafer level package and fabrication method
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
SG142140A1 (en) 2003-06-27 2008-05-28 Semiconductor Energy Lab Display device and method of manufacturing thereof
TWI358776B (en) * 2003-11-08 2012-02-21 Chippac Inc Flip chip interconnection pad layout
US8853001B2 (en) * 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8574959B2 (en) 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
TWI478254B (zh) 2003-11-10 2015-03-21 Chippac Inc 引線上凸塊之倒裝晶片互連
US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8350384B2 (en) 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
TWI262041B (en) * 2003-11-14 2006-09-11 Hitachi Chemical Co Ltd Formation method of metal layer on resin layer, printed wiring board, and production method thereof
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
KR20070107154A (ko) 2005-03-25 2007-11-06 스태츠 칩팩, 엘티디. 기판상에 좁은 상호접속 사이트를 갖는 플립 칩 상호접속체
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20060255473A1 (en) * 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP2007067147A (ja) * 2005-08-31 2007-03-15 Shinko Electric Ind Co Ltd プリント配線基板およびその製造方法
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
CN1997271B (zh) * 2006-01-06 2010-07-21 聚鼎科技股份有限公司 散热装置和其制作方法
CN101079460B (zh) * 2006-05-23 2010-05-12 台达电子工业股份有限公司 发光装置
CN101079461B (zh) * 2006-05-23 2010-05-12 台达电子工业股份有限公司 发光装置
US7902660B1 (en) * 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
JP4876272B2 (ja) * 2008-04-02 2012-02-15 サムソン エレクトロ−メカニックス カンパニーリミテッド． 印刷回路基板及びその製造方法
US7897502B2 (en) 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US7786839B2 (en) * 2008-12-28 2010-08-31 Pratt & Whitney Rocketdyne, Inc. Passive electrical components with inorganic dielectric coating layer
US8659172B2 (en) 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US8198186B2 (en) 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US8127979B1 (en) * 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US8693203B2 (en) 2011-01-14 2014-04-08 Harris Corporation Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices
US8472207B2 (en) * 2011-01-14 2013-06-25 Harris Corporation Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods
JP2012156309A (ja) * 2011-01-26 2012-08-16 Nitto Denko Corp 配線回路基板およびその製造方法ならびに燃料電池
JP6046406B2 (ja) * 2011-07-26 2016-12-14 ローム アンド ハース エレクトロニック マテリアルズ エルエルシーＲｏｈｍ ａｎｄ Ｈａａｓ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌｓ ＬＬＣ 高温耐性銀コート基体
KR101175909B1 (ko) * 2011-07-27 2012-08-22 삼성전기주식회사 인쇄회로기판의 표면처리 방법 및 인쇄회로기판
US20130033671A1 (en) * 2011-08-04 2013-02-07 Endicott Interconnect Technologies, Inc. Liquid crystal polymer (lcp) surface layer adhesion enhancement
CN104112732A (zh) * 2013-08-19 2014-10-22 广东美的集团芜湖制冷设备有限公司 集成电路模块及其制造方法
JP2015076576A (ja) * 2013-10-11 2015-04-20 パナソニックＩｐマネジメント株式会社 電気装置、電気装置の製造方法
JP2022071925A (ja) * 2020-10-29 2022-05-17 ローム株式会社 半導体装置および半導体装置の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908094A (en) * 1986-04-14 1990-03-13 International Business Machines Corporation Method for laminating organic materials via surface modification
US6046500A (en) * 1996-10-31 2000-04-04 International Business Machines Corporation Method of controlling the spread of an adhesive on a circuitized organic substrate

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3918149A (en) * 1974-06-28 1975-11-11 Intel Corp Al/Si metallization process
US4894115A (en) * 1989-02-14 1990-01-16 General Electric Company Laser beam scanning method for forming via holes in polymer materials
JP3457348B2 (ja) * 1993-01-15 2003-10-14 株式会社東芝 半導体装置の製造方法
US5485038A (en) * 1993-07-15 1996-01-16 Hughes Aircraft Company Microelectronic circuit substrate structure including photoimageable epoxy dielectric layers
JP2698827B2 (ja) * 1993-11-05 1998-01-19 カシオ計算機株式会社 バンプ電極を備えた半導体装置の製造方法
KR970000214B1 (ko) 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
JP3444053B2 (ja) * 1995-10-13 2003-09-08 ソニー株式会社 薄膜半導体装置
JP2843315B1 (ja) * 1997-07-11 1999-01-06 株式会社日立製作所 半導体装置およびその製造方法
JP2000039451A (ja) 1998-07-22 2000-02-08 Hoya Corp バーンインボード用多層配線基板及びその製造方法
US6225661B1 (en) * 1998-09-02 2001-05-01 Advanced Micro Devices, Inc. MOS transistor with stepped gate insulator
JP2000216297A (ja) 1999-01-21 2000-08-04 Hitachi Ltd 半導体装置およびその製造方法
US6593658B2 (en) * 1999-09-09 2003-07-15 Siliconware Precision Industries, Co., Ltd. Chip package capable of reducing moisture penetration
US6406991B2 (en) * 1999-12-27 2002-06-18 Hoya Corporation Method of manufacturing a contact element and a multi-layered wiring substrate, and wafer batch contact board
TW515012B (en) * 2000-09-08 2002-12-21 Matsushita Electric Ind Co Ltd Plasma-processing apparatus, plasma-processing method, and chip mounted method
JP2002085803A (ja) 2000-09-20 2002-03-26 Kato Seisakusho:Kk ゲーム機
JP2002270640A (ja) * 2001-03-08 2002-09-20 Hitachi Ltd 半導体パッケージ及びその製造方法
JP3560563B2 (ja) 2001-05-08 2004-09-02 シャープ株式会社 半導体装置及びその製造方法
JP2003007921A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置およびその製造方法
US6869831B2 (en) * 2001-09-14 2005-03-22 Texas Instruments Incorporated Adhesion by plasma conditioning of semiconductor chip surfaces
US6921860B2 (en) * 2003-03-18 2005-07-26 Micron Technology, Inc. Microelectronic component assemblies having exposed contacts
US6853060B1 (en) * 2003-04-22 2005-02-08 Amkor Technology, Inc. Semiconductor package using a printed circuit board and a method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908094A (en) * 1986-04-14 1990-03-13 International Business Machines Corporation Method for laminating organic materials via surface modification
US6046500A (en) * 1996-10-31 2000-04-04 International Business Machines Corporation Method of controlling the spread of an adhesive on a circuitized organic substrate

Also Published As

Publication number Publication date
US20080311737A1 (en) 2008-12-18
JP2005109067A (ja) 2005-04-21
CN100421249C (zh) 2008-09-24
CN101393871A (zh) 2009-03-25
US20110263121A1 (en) 2011-10-27
CN1604320A (zh) 2005-04-06
JP3877717B2 (ja) 2007-02-07
US7939373B2 (en) 2011-05-10
KR20050031963A (ko) 2005-04-06
TW200522228A (en) 2005-07-01
US7405484B2 (en) 2008-07-29
TWI248140B (en) 2006-01-21
KR100644311B1 (ko) 2006-11-23
US20050067686A1 (en) 2005-03-31

Similar Documents

Publication Publication Date Title
CN101393871B (zh) 层积半导体芯片的半导体装置制造方法
CN101843181B (zh) 内置元件电路板
US6624511B2 (en) Hybrid integrated circuit device
US7705456B2 (en) Semiconductor package substrate
JP4020874B2 (ja) 半導体装置およびその製造方法
US7262499B2 (en) Semiconductor packages
CN101286463B (zh) 半导体装置及其制造方法
US8018311B2 (en) Microminiature power converter
CN100452342C (zh) 制造内置器件的基板的方法
US20060049516A1 (en) Nickel/gold pad structure of semiconductor package and fabrication method thereof
CN100446224C (zh) 配线基体部件及其制造方法
CN106328604A (zh) 芯片封装
CN101026143A (zh) 用于柔性板上倒装芯片应用的柔性电路衬底
US20040256742A1 (en) Semiconductor module and method of manufacturing the same
CN101373748B (zh) 晶圆级封装结构及其制作方法
JP2005056221A (ja) 半導体モジュール及びその製造方法
TWI277191B (en) Method for manufacturing leadless package substrate
CN1604321A (zh) 层积半导体芯片的半导体装置及其制造方法
CN100530574C (zh) 半导体模块及其制造方法
JP4413206B2 (ja) 半導体装置およびその製造方法
TWI231025B (en) Method for plating metal layer over pads on substrate for semiconductor package
TW200536095A (en) Ball grid array package structure, heat slug structure, and laser mark rework method
JP2003100985A (ja) 回路モジュール
KR20040086778A (ko) 반도체 모듈 및 그 제조 방법
JP2006245070A (ja) 回路装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110713

Termination date: 20140930

EXPY Termination of patent right or utility model