CN101414601A - Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins - Google Patents
Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins Download PDFInfo
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- CN101414601A CN101414601A CN 200710162855 CN200710162855A CN101414601A CN 101414601 A CN101414601 A CN 101414601A CN 200710162855 CN200710162855 CN 200710162855 CN 200710162855 A CN200710162855 A CN 200710162855A CN 101414601 A CN101414601 A CN 101414601A
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- gluing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a semiconductor package stacking combination structure for protecting soldered joints among outer leads. The structure mainly comprises a plurality of mutually stacked semiconductor packaging parts and non-conducting gluing. Each semiconductor packaging part comprises at least one wafer, a plurality of outer leads of a lead frame and a colloid, and the outer leads are exposed at the side edges of the colloid, wherein, end faces of a plurality of outer leads of an upper-layer semiconductor packaging part are soldered on one segment of the corresponding outer leads of a lower-layer semiconductor packaging part. The non-conducting gluing is formed on the end faces of the outer leads of the upper-layer semiconductor packaging part along the side edges of the colloid of the lower-layer semiconductor packaging part so as to partially or fully clad the soldered joints among the outer leads of the upper-layer semiconductor packaging part and the lower-layer semiconductor packaging part. The semiconductor package stacking combination structure can help achieve the stress dispersion of the soldered joints among the outer leads and avoid short circuits.
Description
Technical field
The present invention relates to a kind of lead frame base semiconductor encapsulation stacking combined construct (leadframe-based POP device); particularly relate to and a kind ofly avoid being subjected to adhesive body and lead frame thermal expansion coefficient difference and cause the solder joint fracture to take place; electrically short circuit can also be prevented between pin, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins that adhesive body and lead frame thermal expansion coefficient difference act on the stress of welding spot between external pins can also be absorbed in addition.
Background technology
The high-tech electronic product is constantly released electronic product more humane, with better function in recent years, causes product that light, thin, short, little further trend is arranged.Therefore, a kind of combination form of semiconductor element is a plurality of semiconductor package parts to be made vertical 3D pile up to meet the requirement that small-sized surperficial bonding area and high density components are provided with, and is referred to as semiconductor encapsulation stacking combined construct (lead frame-based POPdevice).Wherein, as chip carrier, cost is minimum with lead frame for stackable semiconductor encapsulated element, and it is to weld and pile up with the outer pin that extends element (adhesive body) to link together, use the serial connection that reaches circuit, but welding spot between external pins there is phenomenon of rupture easily.
See also Figure 1 and Figure 2, Fig. 1 is the front-view schematic diagram that has known semiconductor encapsulation stacking combined construct now, and Fig. 2 is the local schematic side view that has known semiconductor encapsulation stacking combined construct now.Existing known semiconductor encapsulation stacking combined construct 100 mainly comprises one first semiconductor package part 110 and at least one second semiconductor package part 120 that is stacked on this first semiconductor package part 110.This first semiconductor package part 110 is all the lead frame substrate with this second semiconductor package part 120, wafer of encapsulation can be flash memory (flash memory in it, flash memory is a fast flash memory bank) or the Dynamic Random Access Memory (memory of double data speed (DDR), memory body is a storage medium, memory, internal memories etc. below all are called memory body), to increase the memory body capacity or to increase application function.This first semiconductor package part 110 includes a plurality of first outer pin 113 of one first adhesive body 111, one first wafer 112 and a lead frame.Wherein, those first outer pins 113 can utilize scolder 150 surface engagement to circuit boards 140.Common lead frame product can be TSOP, QFP, TQFP or the like.
This second semiconductor package part 120 includes a plurality of second outer pin 123 of one second adhesive body 121, one second wafer 122 and a lead frame.Wherein, the second outer pin 123 of second semiconductor package part 120 is to expose to this second adhesive body 121, be about I shape pin, it is for straight and general and on this second adhesive body 121 sign face is vertical, and is connected to a section of the first outer pin 113 of first semiconductor package part 110 with welding substance 130.Because solder joint (being the position of welding substance 130) forms for independent between those first outer pins 113 and those the second outer pins 123, fracture easily in temperature cycling test (temperature cycling test).Through the test with research, the fracture cause of welding spot between external pins by the thermal coefficient of expansion of element material do not match (CTE mismatch) caused.Though different material suppliers has different material characters with different models, but still for example, this first semiconductor package part 110 is about 10ppm/ ℃ when being lower than glass transition temperature (Tg) with the adhesive body 111 of this second semiconductor package part 120 and 121 thermal coefficient of expansion, be about 36ppm/ ℃ when being higher than glass transition temperature (Tg), wherein the glass transition temperature of adhesive body generally is about 120 ℃; And the material of general lead frame (promptly outer pin 113 and 123) is the metal or alloy material, is example with iron-nickel alloy Alloy 42, and its thermal coefficient of expansion is about 4.3ppm/ ℃.Therefore, when the temperature of semiconductor encapsulation stacking combined construct 100 high more, adhesive body 111 and 121 volume thermal expansion amount are big more, big more with outer pin 113 and 123 expansion difference in stretch amount, the contact interface between the adhesive body 111 and 121 has produced the stress (as shown in Figure 1) of pullling those second pins 123.So the part solder joint of those second pins 123 bears the lateral edges pin of excessive concentrated stress, particularly those second pins 123, can have the problem of solder joint fracture.
This shows that above-mentioned conventional semiconductor packages stack combination construction obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.For solving the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of semiconductor encapsulation stacking combined construct of protection welding spot between external pins of new structure, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that above-mentioned conventional semiconductor packages stack combination construction exists; the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge; and the utilization of cooperation scientific principle; actively studied innovation; semiconductor encapsulation stacking combined construct in the hope of the protection welding spot between external pins of founding a kind of new structure; can improve general conventional semiconductor packages stack combination construction, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is; overcome the defective that the conventional semiconductor packages stack combination construction exists; and provide a kind of semiconductor encapsulation stacking combined construct of protection welding spot between external pins of new structure; technical problem to be solved is that its stress that can make welding spot between external pins is disperseed, and then can avoid being subjected to the generation that the difference of the thermal coefficient of expansion of adhesive body and lead frame causes solder joint to rupture.In addition, can prevent electrically short circuit between the pin, be very suitable for practicality.
Another object of the present invention is to; a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins is provided; technical problem to be solved is to make its difference that can absorb the thermal coefficient of expansion of adhesive body and lead frame act on the stress of welding spot between external pins, thereby is suitable for practicality more.
An also purpose of the present invention is; a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins is provided; technical problem to be solved be make its can the clad welded material at welding spot between external pins; help to conduct heat; and can at high temperature keep electric connection between the outer pin, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins according to the present invention's proposition, it comprises: one first semiconductor package part, comprise one first adhesive body, at least one first wafer of this first adhesive body and a plurality of first outer pin of a lead frame of being sealed in, wherein those first outer pins are to be extended and exposed by the side of this first adhesive body; At least one second semiconductor package part, it is engaged on this first semiconductor package part, this second semiconductor package part comprises one second adhesive body, at least one second wafer of this second adhesive body and a plurality of second outer pin of a lead frame of being sealed in, and wherein those second outer pins are to be extended and exposed by the side of this second adhesive body; Welding substance, it is the end face of those second outer pins of welding and a section of corresponding those first outer pins; And the dielectric gluing, it is along the first adhesive body side of this first semiconductor package part and be formed at the end face of those pins outside second of second semiconductor package part, to connect those second outer pins and to coat this welding substance.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing are for low modulus, to absorb the stress between those first outer pins and those the second outer pins.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing is to be heat conductive silica gel.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said second adhesive body are superimposed this first adhesive bodies that is contacted with.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing are that part seals this welding substance.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing is to seal this welding substance fully.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing is to be lumps.
The semiconductor encapsulation stacking combined construct of aforesaid protection welding spot between external pins, wherein said dielectric gluing are to be the adhesive tape shape.
The present invention compared with prior art has tangible advantage and beneficial effect.As known from the above; for achieving the above object; according to a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins of the present invention, mainly comprise one first semiconductor package part, at least one second semiconductor package part, welding substance and non-conductive gluing.This first semiconductor package part comprises one first adhesive body, at least one first wafer of this first adhesive body and a plurality of first outer pin of a lead frame of being sealed in, and wherein those first outer pins are to be extended and exposed by the side of this first adhesive body.This second semiconductor package part is to be engaged on this first semiconductor package part, this second semiconductor package part comprises one second adhesive body, at least one second wafer of this second adhesive body and a plurality of second outer pin of a lead frame of being sealed in, and wherein those second outer pins are to be extended and exposed by the side of this second adhesive body.This welding substance is the end face of those second outer pins of welding and a section of corresponding those first outer pins.This non-conductive gluing is the end face that is formed at those pins outside second of second semiconductor package part along the first adhesive body side of this first semiconductor package part, to connect those second outer pins and to coat this welding substance.Use the stress that can reach welding spot between external pins and disperse, and can prevent short circuit.
In aforesaid semiconductor encapsulation stacking combined construct, this dielectric gluing is to can be low modulus, to absorb the stress between those first outer pins and those the second outer pins.In aforesaid semiconductor encapsulation stacking combined construct, this dielectric gluing can be heat conductive silica gel.In aforesaid semiconductor encapsulation stacking combined construct, this second adhesive body can superimposedly be contacted with this first adhesive body.In aforesaid semiconductor encapsulation stacking combined construct, this dielectric gluing can partially or completely seal this welding substance.In aforesaid semiconductor encapsulation stacking combined construct, this dielectric gluing can be lumps or adhesive tape shape.
By technique scheme, the present invention protects the semiconductor encapsulation stacking combined construct of welding spot between external pins to have following advantage and beneficial effect at least:
1, the present invention can make the stress of welding spot between external pins disperse, and then can avoid being subjected to the generation that the difference of the thermal coefficient of expansion of adhesive body and lead frame causes solder joint to rupture.In addition, can also prevent electrically short circuit between the pin, be very suitable for practicality.
2, in addition, the difference that the present invention can absorb the thermal coefficient of expansion of adhesive body and lead frame acts on the stress of welding spot between external pins, is suitable for practicality more.
3 moreover, the present invention can the clad welded material at welding spot between external pins, help to conduct heat, and can at high temperature keep the electric connection between the outer pin, thereby be suitable for practicality more.
In sum, the present invention is relevant a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins, mainly comprises a plurality of semiconductor package parts that pile up mutually and non-conductive gluing.Each semiconductor package part comprise plural number outer pin and an adhesive body of at least one wafer, a lead frame, and those outer pins is the sides that expose to those adhesive bodies.Wherein, the end face of a plurality of outer pins of the semiconductor package part on a upper strata is welded onto a section of the corresponding outer pin of lower floor's semiconductor package part.This non-conductive gluing is the outer pin end face that is formed at the upper strata semiconductor package part along the adhesive body side of lower floor's semiconductor package part, with the solder joint between the outer pin of part or all of coating levels semiconductor package part.Using the present invention can reach the stress dispersion of welding spot between external pins and can prevent short circuit.The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and the outstanding effect that has enhancement than the conventional semiconductor packages stack combination construction, thereby being suitable for practicality more, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs. is described in detail as follows.
Description of drawings
Fig. 1 is the front-view schematic diagram that has known semiconductor encapsulation stacking combined construct now.
Fig. 2 is the local schematic side view that has known semiconductor encapsulation stacking combined construct now.
Fig. 3 is according to a specific embodiment of the present invention, a kind of schematic cross-section of protecting the semiconductor encapsulation stacking combined construct of welding spot between external pins.
Fig. 4 is according to a specific embodiment of the present invention, the local schematic side view of this semiconductor encapsulation stacking combined construct.
Fig. 5 is according to a specific embodiment of the present invention, illustrates the different partial cross section's enlarged diagrams that coat kenel of dielectric gluing of this semiconductor encapsulation stacking combined construct.
Fig. 6 is according to a specific embodiment of the present invention, the local schematic side view of the semiconductor encapsulation stacking combined construct of another kind of protection welding spot between external pins.
100: 110: the first semiconductor package parts of semiconductor encapsulation stacking combined construct
112: the first wafers of 111: the first adhesive bodies
120: the second semiconductor package parts of 113: the first outer pins
122: the second wafers of 121: the second adhesive bodies
123: the second outer pins 130: welding substance
140: circuit board 150: scolder
200: 210: the first semiconductor package parts of semiconductor encapsulation stacking combined construct
212: the first wafers of 211: the first adhesive bodies
213: the first outer pins 214: outer pin section
216: the first weld pads of 215: the first bonding wires
217: sticking 220: the second semiconductor package parts of brilliant glue
222: the second wafers of 221: the second adhesive bodies
224: the second outer pin end faces of 223: the second outer pins
226: the second weld pads of 225: the second bonding wires
227: sticking brilliant glue 230: welding substance
240: dielectric gluing 240A: dielectric gluing
240B: dielectric gluing 240C: dielectric gluing
240 ': dielectric gluing 250: circuit board
260: scolder
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; below in conjunction with accompanying drawing and preferred embodiment; its embodiment of semiconductor encapsulation stacking combined construct, structure, feature and the effect thereof of the protection welding spot between external pins that foundation the present invention is proposed, describe in detail as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to present in the following detailed description that cooperates with reference to graphic preferred embodiment.By the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to get one more deeply and concrete understanding to the present invention, yet appended graphic only provide with reference to the usefulness of explanation, be not to be used for the present invention is limited.
Seeing also Fig. 3 and shown in Figure 4, is a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins that the present invention's one specific embodiment is disclosed.Fig. 3 is a kind of schematic cross-section of protecting the semiconductor encapsulation stacking combined construct of welding spot between external pins, and Fig. 4 is the local schematic side view of this semiconductor encapsulation stacking combined construct.The semiconductor encapsulation stacking combined construct 200 of the protection welding spot between external pins of the present invention's one concrete preferred embodiment mainly comprises one first semiconductor package part 210, at least one second semiconductor package part 220, welding substance 230 and dielectric gluing 240.
The first above-mentioned semiconductor package part 210 and this second semiconductor package part 220 is to can be single-chip encapsulation or the encapsulation of polycrystalline sheet.As shown in Figure 3, in the present embodiment, this first semiconductor package part 210 and this second semiconductor package part 220 are all the thin little outline packages (TSOP) of single-chip.
The first above-mentioned semiconductor package part 210 comprises that one first adhesive body 211, is sealed in first wafer 212 of this first adhesive body 211 and a plurality of first outer pin 213 of a lead frame;
This first wafer 212, its active surface is provided with one first weld pad 216, and can by sticking brilliant glue 217 active surface of this first wafer 212 is adhered to this lead frame those first outer pins 213 by the lower surface of sealing section, in addition first bonding wire 215 that forms with a plurality of routings is as electrical connecting element, this first weld pad 216 of this first wafer 212 is electrically connected to this lead frame those first outer pins 213 by the upper surface of sealing section.This first adhesive body 211 is formed in sealing (encapsulate) step, with seal this first wafer 212, those first bonding wires 215 and those first outer pins 213 by the sealing section.
Those first outer pins 213 are to be extended and exposed by the side of this first adhesive body 211.In the present embodiment, those first outer pins 213 are for sea-gull pin (gull lead), in order to surface engagement to a circuit board 250, usually with scolder 260 welding.And this circuit board 250 can be motherboard, memory body module support plate, display card support plate, memory card substrate or mobile communication plate or the like.
The second above-mentioned semiconductor package part 220 is engaged on this first semiconductor package part 210, uses and does the encapsulation stacking combination, finishes the TSOP stacked structure of multilayer.This second semiconductor package part 220 comprises one second adhesive body 221, at least one second wafer 222 of this second adhesive body 221 and a plurality of second outer pin 223 of a lead frame of being sealed in; Wherein:
Those second outer pins 223 are to be extended and exposed by the side of this second adhesive body 221.Preferable, those second outer pins 223 can be the I type pin of vertical kenel, so that the end face 224 of those second outer pins 223 can utilize this welding substance 230 to be soldered to a section 214 (enlarged drawing as shown in Figure 3) of those first outer pins 213.
As shown in Figure 3, in one embodiment, second semiconductor package part 220 more comprises at least one sticking brilliant glue 227 and a plurality of second bonding wires 225.
Should sticking brilliant glue 227, be second outer pin 223 or the wafer holder (scheme do not draw) of this second wafer 222 of cementation in this lead frame.
Those second bonding wires 225 are a plurality of second weld pads 226 of electrically connecting this second wafer 222 to correspondence second outside pin 223.
Outside the pin that all has the side extension, the encapsulation kenel of this second semiconductor package part 220 can be identical or inequality with this first semiconductor package part 210.
Usually this first wafer 212 can be memory chip with this second wafer 222, and as fast flash memory bank or Dynamic Random Access Memory, using raising memory body capacity can not increase the surface engagement area again.
This first adhesive body 211 and this second adhesive body 221, can be epoxy mould envelope compound (EpoxyMolding Compound, EMC).In addition, the bottom surface of this second adhesive body 221 is the end faces that can superimposedly be contacted with this first adhesive body 211, to dwindle stacked height.
In addition, above-mentioned welding substance 230 is the end face 224 of those second outer pins 223 of welding and a section 214 of corresponding those first outer pins 213, uses to electrically connect those second outer pins 213 and those second outer pins 223.But this welding substance 230 is the melting welding conducting metal, as tin lead or unleaded solder.
Seeing also Fig. 3, and in conjunction with consulting dielectric gluing 240 shown in Figure 4, above-mentioned, is the end face 224 that is formed at those pins 223 outside second of second semiconductor package part 220 along first adhesive body, 211 sides of this first semiconductor package part 210.In the present embodiment, this dielectric gluing 240 can be lumps, to connect those second outer pins 223 and to coat this welding substance 230, use and disperse that solder joint (i.e. the position of this welding substance 230) is subjected to the stress of thermal expansion coefficient difference between those outer pins 213,223, and can reach the effect that the solder joint that prevents outer pin ruptures.Wherein, above-mentioned thermal expansion coefficient difference is meant those the outer pins 213,223 of lead frame and the thermal expansion coefficient difference of adhesive body 211,221.
In the present embodiment, this dielectric gluing 240 also can partly seal the outside of this welding substance 230.Yet, the viscosity of dielectric gluing and the amount of spreading are for can adjust to change over suitable coating area and wrapped shapes, see also shown in Figure 5, be according to a specific embodiment of the present invention, illustrate the different partial cross section's enlarged diagrams that coat kenel of dielectric gluing of this semiconductor encapsulation stacking combined construct.In different embodiment, a kind of dielectric gluing 240A also can partly seal the inboard (shown in the A of Fig. 5) of this welding substance 230; A kind of dielectric gluing 240B also can seal this welding substance 230 fully and have thin cladding thickness (shown in the B of Fig. 5); A kind of dielectric gluing 240C also can seal this welding substance 230 fully and have thicker cladding thickness (shown in the C of Fig. 5).
Preferably, this dielectric gluing 240 can be low modulus, to absorb the stress between those first outer pins 213 and those the second outer pins 223, make it can absorb bigger stress, and improved the impact resistance of this semiconductor encapsulation stacking combined construct 200, anti-dropping, heat resistanceheat resistant cyclicity and thermal-shock resistance.Therefore, this semiconductor encapsulation stacking combined construct 200 can not have the problem of welding spot between external pins fracture, and can improve reliability of products.More specifically, this dielectric gluing 240 can be heat conductive silica gel, and its conductive coefficient should be equivalent to even be higher than the conductive coefficient of this first adhesive body 211 or this second adhesive body 221, to help heat radiation.
Seeing also shown in Figure 6ly, is according to the present invention's one specific embodiment, the local schematic side view of the semiconductor encapsulation stacking combined construct of another kind of protection welding spot between external pins.The semiconductor encapsulation stacking combined construct 200 of this protection welding spot between external pins mainly comprises one first semiconductor package part 210, at least one second semiconductor package part 220, welding substance 230 and non-conductive gluing 240 '.Except the shape of non-conductive gluing 240 ' and the foregoing description were slightly different, other element can generally be identical, so continue to use identical label.
This first semiconductor package part 210 comprises one in order to first adhesive body 211 of sealing wafer and a plurality of first outer pin 213 of a lead frame, can utilize scolder 260 to be welded on the circuit board 250.
This second semiconductor package part 220 is to be engaged on this first semiconductor package part 210, and this second semiconductor package part 220 comprises one in order to second adhesive body 221 of sealing wafer and a plurality of second outer pin 223 of a lead frame.
This welding substance 230 is the end face of those second outer pins 223 of welding and a section of corresponding those first outer pins 213.
This non-conductive gluing 240 ', be along first adhesive body, 211 sides of this first semiconductor package part 210 and be formed at the end face of those pins 223 outside second of second semiconductor package part 220, to connect those second outer pins 223 and to coat this welding substance 230.Use the stress dispersion that reaches welding spot between external pins and prevent short circuit.Preferable, this non-conductive gluing 240 ' is to be the adhesive tape shape, with the different second outer pins 223 of non-conductive serial connection, and can reach the effect that stress is scattered in different outer pins.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (8)
1, a kind of semiconductor encapsulation stacking combined construct of protecting welding spot between external pins is characterized in that it comprises:
One first semiconductor package part comprises one first adhesive body, at least one first wafer of this first adhesive body and a plurality of first outer pin of a lead frame of being sealed in, and wherein those first outer pins are to be extended and exposed by the side of this first adhesive body;
At least one second semiconductor package part, it is engaged on this first semiconductor package part, this second semiconductor package part comprises one second adhesive body, at least one second wafer of this second adhesive body and a plurality of second outer pin of a lead frame of being sealed in, and wherein those second outer pins are to be extended and exposed by the side of this second adhesive body;
Welding substance, it is the end face of those second outer pins of welding and a section of corresponding those first outer pins; And
The dielectric gluing, it is along the first adhesive body side of this first semiconductor package part and be formed at the end face of those pins outside second of second semiconductor package part, to connect those second outer pins and to coat this welding substance.
2, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said dielectric gluing is for low modulus, to absorb the stress between those first outer pins and those the second outer pins.
3, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 2 is characterized in that wherein said dielectric gluing is to be heat conductive silica gel.
4, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said second adhesive body is superimposed this first adhesive body that is contacted with.
5, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said dielectric gluing is that part seals this welding substance.
6, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said dielectric gluing is to seal this welding substance fully.
7, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said dielectric gluing is to be lumps.
8, the semiconductor encapsulation stacking combined construct of protection welding spot between external pins according to claim 1 is characterized in that wherein said dielectric gluing is to be the adhesive tape shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710162855 CN101414601B (en) | 2007-10-16 | 2007-10-16 | Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710162855 CN101414601B (en) | 2007-10-16 | 2007-10-16 | Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins |
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| Publication Number | Publication Date |
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| CN101414601A true CN101414601A (en) | 2009-04-22 |
| CN101414601B CN101414601B (en) | 2010-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103517551A (en) * | 2012-06-15 | 2014-01-15 | 德尔福技术有限公司 | Surface mount interconnection system and method for modular circuit board |
| CN104952857A (en) * | 2015-06-30 | 2015-09-30 | 南通富士通微电子股份有限公司 | Carrier-free semiconductor PoP (package on package) structure |
| CN111725592A (en) * | 2019-03-20 | 2020-09-29 | 华为技术有限公司 | Phase shifter, antenna and base station |
| CN115169276A (en) * | 2022-07-22 | 2022-10-11 | 北京云枢创新软件技术有限公司 | Pin area matching method based on stacking module |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6165819A (en) * | 1992-10-20 | 2000-12-26 | Fujitsu Limited | Semiconductor device, method of producing semiconductor device and semiconductor device mounting structure |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| DE19833713C1 (en) * | 1998-07-27 | 2000-05-04 | Siemens Ag | Laminate or stacked package arrangement based on at least two integrated circuits |
-
2007
- 2007-10-16 CN CN 200710162855 patent/CN101414601B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103517551A (en) * | 2012-06-15 | 2014-01-15 | 德尔福技术有限公司 | Surface mount interconnection system and method for modular circuit board |
| CN104952857A (en) * | 2015-06-30 | 2015-09-30 | 南通富士通微电子股份有限公司 | Carrier-free semiconductor PoP (package on package) structure |
| CN104952857B (en) * | 2015-06-30 | 2017-12-26 | 通富微电子股份有限公司 | A kind of DNAcarrier free semiconductor laminated encapsulating structure |
| CN111725592A (en) * | 2019-03-20 | 2020-09-29 | 华为技术有限公司 | Phase shifter, antenna and base station |
| CN111725592B (en) * | 2019-03-20 | 2022-10-18 | 华为技术有限公司 | Phase shifter, antenna and base station |
| CN115169276A (en) * | 2022-07-22 | 2022-10-11 | 北京云枢创新软件技术有限公司 | Pin area matching method based on stacking module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101414601B (en) | 2010-09-29 |
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