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Número de publicaciónCN101414601 B
Tipo de publicaciónConcesión
Número de solicitudCN 200710162855
Fecha de publicación29 Sep 2010
Fecha de presentación16 Oct 2007
Fecha de prioridad16 Oct 2007
También publicado comoCN101414601A
Número de publicación200710162855.4, CN 101414601 B, CN 101414601B, CN 200710162855, CN-B-101414601, CN101414601 B, CN101414601B, CN200710162855, CN200710162855.4
Inventores范文正, 陈正斌
Solicitante力成科技股份有限公司
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos:  SIPO, Espacenet
Semiconductor encapsulation stacking combined construct for protecting welding spot between external pins
CN 101414601 B
Resumen
The invention relates to a semiconductor package stacking combination structure for protecting soldered joints among outer leads. The structure mainly comprises a plurality of mutually stacked semiconductor packaging parts and non-conducting gluing. Each semiconductor packaging part comprises at least one wafer, a plurality of outer leads of a lead frame and a colloid, and the outer leads are exposed at the side edges of the colloid, wherein, end faces of a plurality of outer leads of an upper-layer semiconductor packaging part are soldered on one segment of the corresponding outer leads of alower-layer semiconductor packaging part. The non-conducting gluing is formed on the end faces of the outer leads of the upper-layer semiconductor packaging part along the side edges of the colloid of the lower-layer semiconductor packaging part so as to partially or fully clad the soldered joints among the outer leads of the upper-layer semiconductor packaging part and the lower-layer semiconductor packaging part. The semiconductor package stacking combination structure can help achieve the stress dispersion of the soldered joints among the outer leads and avoid short circuits.
Reclamaciones(4)  traducido del chino
  1. 一种保护外引脚之间焊点的半导体封装堆叠组合构造,其特征在于其包括:一第一半导体封装件,包括一第一封胶体、至少一被密封在该第一封胶体的第一晶片以及一导线架的复数个第一外引脚,其中该些第一外引脚是由该第一封胶体的侧边延伸且外露;至少一第二半导体封装件,其接合于该第一半导体封装件上,该第二半导体封装件包括一第二封胶体、至少一被密封在该第二封胶体的第二晶片以及一导线架的复数个第二外引脚,其中该些第二外引脚是由该第二封胶体的侧边延伸且外露;焊接物质,其是焊接该些第二外引脚的端面与对应该些第一外引脚的一区段;以及介电涂胶,其沿着该第一半导体封装件的第一封胶体侧边而形成于第二半导体封装件的该些第二外引脚的端面,以连接该些第二外引脚与该焊接物质;其中所述的介电涂胶部分密封该焊接物质,并且其中所述的介电涂胶为对应焊接物质的团块状或是悬空的胶条状。 An outer protective pad between the semiconductor package pin structure stack composition, characterized in that it comprises: a first semiconductor package comprising a first package material, at least one of the first seal is sealed in a first colloid chip and a lead frame of a plurality of first external pins, wherein the plurality of first external pins are extending from the first side edge and the exposed adhesive body; at least one second semiconductor package, which is joined to the first the semiconductor package, the second semiconductor package includes a second seal colloid, at least one second wafer is sealed in the second seal colloid and a lead frame of a plurality of second external pins, wherein the plurality of second external pins are extending from the side of the second package material and exposed; welding material, which is welded to the end face of those should be some one section of the second outer pin of the first outer pin; and a dielectric coating These outer end surface of the second plastic pin, which package material along a first side of the first semiconductor package and the second semiconductor package is formed so as to connect the outer pin and the second of these welding material ; a dielectric coating wherein the sealing portion of the welding material, and wherein the dielectric coating lumps corresponding welding material or floating plastic strips.
  2. 2.根据权利要求1所述的保护外引脚之间焊点的半导体封装堆叠组合构造,其特征在于其中所述的介电涂胶是低模数的介电涂胶,所述介电涂胶用于吸收该些第一外引脚与该些第二外引脚之间的应力。 The semiconductor package stacking combined structure between the protective outer pin 1 of the solder joints of claim wherein said dielectric coating is a low modulus dielectric coating, the dielectric coating and stress between the second outer pin some of the glue used in these first pin-absorption.
  3. 3.根据权利要求2所述的保护外引脚之间焊点的半导体封装堆叠组合构造,其特征在于其中所述的介电涂胶是为导热硅胶。 3. The composition according to the semiconductor package stack structure between pins 2, wherein the outer protective pads as claimed in claim wherein said dielectric coating is thermal silica.
  4. 4.根据权利要求1所述的保护外引脚之间焊点的半导体封装堆叠组合构造,其特征在于其中所述的第二封胶体是叠合接触于该第一封胶体。 4. The semiconductor package stacked structure between the protective outer pin composition according to claim solder, wherein said second package material is laminated to the first contact with the package material.
Descripción  traducido del chino

保护外引脚之间焊点的半导体封装堆叠组合构造 The semiconductor package stacked combination solder protection between the outer pin configuration

技术领域 Technical Field

[0001] 本发明涉及一种导线架基底半导体封装堆叠组合构造(leadframe-based POP device),特别是涉及一种可避免受到封胶体与导线架热膨胀系数差异导致焊点断裂发生, 还能防止引脚间电性短路,另还能吸收封胶体与导线架热膨胀系数差异作用于外引脚之间焊点的应力的保护外引脚之间焊点的半导体封装堆叠组合构造。 [0001] The present invention relates to a lead frame combinations stacked semiconductor package substrate structure (leadframe-based POP device), more particularly to a package material can be avoided by the thermal expansion coefficient difference between the lead frame and the lead solder joint fracture, but also to prevent the lead The semiconductor package stacked combination solder joint structure between the protective outer pin electrical short circuit between the foot and the other can absorb lead frame package material and the thermal expansion coefficient differences between the stress acting on the solder joints of the outer pin.

背景技术 Background

[0002] 近年来高科技电子产品不断推出更人性化、功能更佳的电子产品,造成产品有愈加轻、薄、短、小的趋势。 [0002] In recent years, high-tech electronic products has introduced a more humane, it functions better electronic products, resulting in product there is even more light, thin, short, small trend. 因此,一种半导体元件的组合型式是将多个半导体封装件作纵向3D 堆叠以符合小型表面接合面积与高密度元件设置的要求,称之为半导体封装堆叠组合构造(lead frame-based POPdevice)。 Thus, a combination of the type of a semiconductor element is a plurality of semiconductor packages are stacked 3D longitudinally to conform to small surface area of engagement elements disposed in a high density requirements, combined structure is called stacked semiconductor package (lead frame-based POPdevice). 其中,可堆叠的半导体封装元件以导线架作为晶片载体, 成本最低,其是以延伸出元件(封胶体)的外引脚焊接并堆叠连接在一起,藉以达到电路的串接,但外引脚之间焊点容易有断裂现象。 Among them, semiconductor packages can be stacked to a lead frame as a wafer carrier, the lowest cost, which is extending element (package material) pin-welding and stacked together, in order to achieve the series circuit, but external pin between joints prone to breakage.

[0003] 请参阅图1及图2所示,图1是现有习知的半导体封装堆叠组合构造的前视示意图,图2是现有习知的半导体封装堆叠组合构造的局部侧视示意图。 [0003] Please refer to FIG. 1 and FIG. 2, FIG. 1 is a front view showing the conventional semiconductor package stacking conventional combination structure, FIG. 2 is a partial schematic side view of a prior art conventional semiconductor package stacked structure in combination. 现有习知的半导体封装堆叠组合构造100,主要包括一第一半导体封装件110以及至少一堆叠在该第一半导体封装件110上的第二半导体封装件120。 Existing conventional stacked semiconductor package structure 100 in combination, including a first semiconductor package 110 and at least one second semiconductor package stacked on the first semiconductor package 110 120. 该第一半导体封装件110与该第二半导体封装件120皆为导线架基底,其内封装的晶片可为快闪内存(flash memory,快闪内存即快闪记忆体)或双倍资料速度(DDR)的动态随机存取记忆体(memory,记忆体即存储介质,存储器,内存等,以下均称为记忆体),以增加记忆体容量或增加应用功能。 The first semiconductor package 110 and the second semiconductor package substrate 120 are all lead frame, chip within the package for flash memory (flash memory, flash memory, that is, flash memory) or double data rate ( DDR) dynamic random access memory (memory, memory that is a storage medium, memory, memory, etc., hereafter referred to as memory) to increase the memory capacity or add applications. 该第一半导体封装件110 包括有一第一封胶体111、一第一晶片112以及一导线架的复数个第一外引脚113。 The first semiconductor package 110 comprises a first package material 111, a first wafer 112 and a plurality of first lead frame 113 external pins. 其中,该些第一外引脚113可利用焊料150表面接合至一电路板140。 Among them, the first of these pins 113 can take advantage of 150 outside surface of the solder bonded to a circuit board 140. 通常的导线架产品可为TS0P、 QFP、TQFP 等等。 Usually lead frame products for TS0P, QFP, TQFP and so on.

[0004] 该第二半导体封装件120,包括有一第二封胶体121、一第二晶片122以及一导线架的复数个第二外引脚123。 [0004] The second semiconductor package 120, comprising a second package material 121, a second wafer 122 and a plurality of second lead frame 123 external pins. 其中,第二半导体封装件120的第二外引脚123是外露于该第二封胶体121,约为I形脚,其是为笔直并概与在该第二封胶体121上的标示面为垂直,并以焊接物质130连接至第一半导体封装件110的第一外引脚113的一区段。 Wherein the second semiconductor package 120 of the second outer pin 123 is exposed to the second adhesive body 121, which is about I-shaped feet, which is almost straight and with the label on the second sealing surface 121 of colloid vertical, and the welding material 130 is connected to the pin 113 of a first outer segment 110 of the first semiconductor package. 由于该些第一外引脚113与该些第二外引脚123之间焊点(即焊接物质130的位置)为独立形成,在温度循环试验(temperature cycling test)中容易断裂。 Because these joints between the first outer pin 113 and the second outer pin 123 of these (ie welding material position 130) is formed separately, at a temperature cycle test (temperature cycling test) are easily broken. 经试验与研究,外引脚之间焊点的断裂原因为元件材料的热膨胀系数不匹配(CTE mismatch)所造成。 After testing and research, Fracture of joints between the outer pin element material for the thermal expansion coefficient mismatch (CTE mismatch) caused. 虽然不同的材料供应商与不同的型号会有不同的材料性质,但仍举例而言,该第一半导体封装件110与该第二半导体封装件120的封胶体111与121的热膨胀系数约为10ppm/°C当低于玻璃转化温度(Tg), 约为36ppm/°C当高于玻璃转化温度(Tg),其中封胶体的玻璃转化温度一般约为120°C ;而一般导线架(即外引脚113与123)的材质为金属或合金材料,以铁镍合金Alloy 42为例, 其热膨胀系数约为4. 3ppm/°C。 Although different material suppliers and different models have different material properties, but still example, the first semiconductor package 110 and the second semiconductor package 120, the package material 111 and the thermal expansion coefficient of about 10ppm 121 / ° C when below the glass transition temperature (Tg), about 36ppm / ° C when above the glass transition temperature (Tg), which sealed the colloidal glass transition temperature is generally about 120 ° C; and generally lead frame (ie outside Pins 113 and 123) is made of a metal or alloy, iron-nickel alloy, Alloy 42, for example, the thermal expansion coefficient of about 4. 3ppm / ° C. 因此,当半导体封装堆叠组合构造100的温度越高,封胶体111与121的体积热膨胀量越大,与外引脚113与123膨胀拉伸量差异越大,封胶体111与121之间的接触界面产生了拉扯该些第二引脚123的应力(如图1所示)。 Therefore, the contact structure of a semiconductor package stacked combination of the higher temperature of 100, the larger the package material 111 121 volume thermal expansion, the greater the outer pin 113 and 123 expanded the amount of stretch difference between 111 and 121 seal colloid when pull the stress generated at the interface of these second pin 123 (Figure 1). 故该些第二引脚123的部分焊点承受过大集中的应力,特别是该些第二引脚123的侧边缘引脚,会存在有焊点断裂的问题。 So that some portion of the second pin 123 joints exposed to excessive concentration of stress, especially those of the second pin 123 of the side edge pins will there solder fracture problems.

[0005] 由此可见,上述现有的半导体封装堆叠组合构造在结构与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。 [0005] Thus, the conventional semiconductor package stack structure in combination with the use of the structure, it is clear there is still inconvenient and defects, and needs to be further improved. 为解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品又没有适切结构能够解决上述问题,此显然是相关业者急欲解决的问题。 In order to solve the above problems, the firms did not dare to think hard and to seek a solution, but has long been seen to be applicable to the design of complete development, and general product and no appropriate structure can solve the above problems, this is clearly related industry anxious to solve the problem. 因此如何能创设一种新型结构的保护外引脚之间焊点的半导体封装堆叠组合构造,实属当前重要研发课题之一,亦成为当前业界极需改进的目标。 So how can we create joints between the protective outer lead a new structure of the semiconductor package stack combined structure, it is currently one of the important research and development issues, has become the industry in dire need of improvement goals.

[0006] 有鉴于上述现有的半导体封装堆叠组合构造存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,并配合学理的运用,积极加以研究创新,以期创设一种新型结构的保护外引脚之间焊点的半导体封装堆叠组合构造,能够改进一般现有的半导体封装堆叠组合构造,使其更具有实用性。 [0006] In view of the conventional semiconductor package stacking combination construction defects, the present inventors based in the design and manufacture of such products for many years a wealth of practical experience and expertise, and with the use of theoretical and actively to research and innovation, to create The semiconductor package stacked combination solder joint structure between the protective outer pin of a new structure, it is possible to improve the general conventional semiconductor package stacking combination structure to make it more practical. 经过不断的研究、设计,并经过反复试作样品及改进后,终于创设出确具实用价值的本发明。 Through continuous research, design, and test for the sample after repeated and improvement, and finally the creation of a really a practical value of the present invention.

发明内容 DISCLOSURE

[0007] 本发明的主要目的在于,克服现有的半导体封装堆叠组合构造存在的缺陷,而提供一种新型结构的保护外引脚之间焊点的半导体封装堆叠组合构造,所要解决的技术问题是使其能使外引脚之间焊点的应力分散,进而可以避免受到封胶体与导线架的热膨胀系数的差异导致焊点断裂的发生。 [0007] The main object of the present invention is to overcome the existing combination of semiconductor packages stacked structure defects, and to provide a semiconductor package stacked combination solder joint structure between the protective outer pin of a new structure, the technical problem to be solved It is that it enables the stress dispersion between the outer pin pad, and then prevented by the difference in thermal expansion coefficient of the package material and the lead frame lead to solder joint fracture occurs. 此外,能够防止引脚之间电性短路,非常适于实用。 In addition, it is possible to prevent electrical short circuit between the pins, very fit for practical use.

[0008] 本发明的另一目的在于,提供一种保护外引脚之间焊点的半导体封装堆叠组合构造,所要解决的技术问题是使其能吸收封胶体与导线架的热膨胀系数的差异作用于外引脚之间焊点的应力,从而更加适于实用。 [0008] Another object of the present invention is to provide a protective structure of a semiconductor package stacking combination between an outer pin joints, the technical problem to be solved is the difference in coefficient of thermal expansion of the role that it can absorb the package material and the lead frame in between the outer lead solder joint stress, and thus more suitable for practical.

[0009] 本发明的还一目的在于,提供一种保护外引脚之间焊点的半导体封装堆叠组合构造,所要解决的技术问题是使其能够包覆焊接物质在外引脚之间焊点,有助于传导热量,而能在高温下维持外引脚之间的电性连接,从而更加适于实用。 [0009] Yet another object of the present invention is to provide a protective structure semiconductor package stacked combination solder between the outer pins, technical problem to be solved is to enable them to cover joints between the outer pin welding material, It helps to conduct heat, and can maintain the electrical connection between the outer lead at a high temperature, and thus more suitable for practical.

[0010] 本发明的目的及解决其技术问题是采用以下技术方案来实现的。 [0010] The purpose and solving the technical problem of the invention is the use of the following technical solutions to achieve. 依据本发明提出的一种保护外引脚之间焊点的半导体封装堆叠组合构造,其包括:一第一半导体封装件, 包括一第一封胶体、至少一被密封在该第一封胶体的第一晶片以及一导线架的复数个第一外引脚,其中该些第一外引脚是由该第一封胶体的侧边延伸且外露;至少一第二半导体封装件,其接合于该第一半导体封装件上,该第二半导体封装件包括一第二封胶体、至少一被密封在该第二封胶体的第二晶片以及一导线架的复数个第二外引脚,其中该些第二外引脚是由该第二封胶体的侧边延伸且外露;焊接物质,其是焊接该些第二外引脚的端面与对应该些第一外引脚的一区段;以及介电涂胶,其沿着该第一半导体封装件的第一封胶体侧边而形成于第二半导体封装件的该些第二外引脚的端面,以连接该些第二外引脚与该焊接物质;其中所述的介电涂胶部分密封该焊接物质,并且其中所述的介电涂胶为对应焊接物质的团块状或是悬空的胶条状。 According to the present invention provides a method of protecting semiconductor package stacked combination solder between the outer pin structure, comprising: a first semiconductor package, comprising a first package material, at least one of the first seal is sealed colloid The first chip and a lead frame of a plurality of first external pins, wherein the plurality of first external pins are extending from the first side edge and the exposed adhesive body; at least one second semiconductor package, which engages in the on the first semiconductor package, the second semiconductor package includes a second seal colloid, at least one second wafer is sealed in the second seal colloid and a lead frame of a plurality of second external pins, wherein the plurality of The second external pins are extending from the second side edge and the exposed adhesive body; welding material, which is welded These second outer end face of the pin and to be more of a section of the first pin-out; and referral These end faces of the outer pins of the second coating, the first package material along the sides of the first semiconductor package and formed in the second semiconductor package to connect the outer pin and the second of these welding material; a dielectric coating wherein the sealing portion of the welding material, and wherein the dielectric coating lumps corresponding welding material or floating plastic strips.

[0011] 本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。 [0011] The purpose and solving the technical problem of the invention can be applied to the following technical measures for further implementation.

[0012] 前述的保护外引脚之间焊点的半导体封装堆叠组合构造,其中所述的介电涂胶是 [0012] The semiconductor package stacked combination solder joint structure between the aforementioned protective outer pin, wherein the dielectric coating is

4低模数的介电涂胶,所述介电涂胶用于吸收该些第一外引脚与该些第二外引脚之间的应力。 4 low modulus dielectric coating, the dielectric coating to absorb the stress between some of the first pin-pin-with some second.

[0013] 前述的保护外引脚之间焊点的半导体封装堆叠组合构造,其中所述的介电涂胶是为导热硅胶。 [0013] The semiconductor package stacked combination solder joint structure between the aforementioned protective outer pin, wherein the dielectric coating is thermal silica.

[0014] 前述的保护外引脚之间焊点的半导体封装堆叠组合构造,其中所述的第二封胶体是叠合接触于该第一封胶体。 [0014] The semiconductor package stacked combination solder joint structure between the aforementioned protective outer pin, wherein said second package material is folded in contact with the first seal colloid.

[0015] 本发明与现有技术相比具有明显的优点和有益效果。 [0015] The present invention over the prior art has obvious advantages and benefits. 由以上可知,为达到上述目的,依据本发明一种保护外引脚之间焊点的半导体封装堆叠组合构造,主要包括一第一半导体封装件、至少一第二半导体封装件、焊接物质以及非导电性涂胶。 These results show that, to achieve the above object, according to the present invention is a semiconductor package stack protection structure between outer pin solder composition, including a first semiconductor package member, the at least one second semiconductor package, soldering material and non- conductive adhesive. 该第一半导体封装件包括一第一封胶体、至少一被密封在该第一封胶体的第一晶片以及一导线架的复数个第一外引脚,其中该些第一外引脚是由该第一封胶体的侧边延伸且外露。 The first semiconductor package includes a first package material, at least one of the first wafer is sealed in the first seal colloid and a lead frame of a plurality of first external pins, wherein the plurality of first external pins are made The first seal colloid sides extending exposed. 该第二半导体封装件是接合于该第一半导体封装件上,该第二半导体封装件包括一第二封胶体、至少一被密封在该第二封胶体的第二晶片以及一导线架的复数个第二外引脚,其中该些第二外引脚是由该第二封胶体的侧边延伸且外露。 The second member is bonded to the semiconductor package on the first semiconductor package, the second semiconductor package comprises a second package material, at least one of a plurality of the second wafer is sealed in the package material, and a second lead frame a second external pins, wherein the plurality of second external pins are extending from the second side seal colloid and exposed. 该焊接物质是焊接该些第二外引脚的端面与对应该些第一外引脚的一区段。 The welding material is welded These second outer end face of the pin and to be more of a section of the first outer pin. 该非导电性涂胶是沿着该第一半导体封装件的第一封胶体侧边而形成于第二半导体封装件的该些第二外引脚的端面,以连接该些第二外引脚并包覆该焊接物质。 The non-conductive adhesive along the first side of the package material of the first semiconductor package is formed on the end face of the second semiconductor package some second external pins to connect the second external pin some and covering the welding material. 藉以可以达到外引脚之间焊点的应力分散,并能够防止短路。 Whereby stress can be achieved between the outer lead solder dispersion, and a short circuit can be prevented.

[0016] 在前述的半导体封装堆叠组合构造中,该介电涂胶是可为低模数,以吸收该些第一外引脚与该些第二外引脚之间的应力。 [0016] In the aforementioned semiconductor package stack combined structure, the dielectric coating is a low modulus, to absorb some of the stress between the first pin-pin-with some second. 在前述的半导体封装堆叠组合构造中,该介电涂胶可为导热硅胶。 In the aforementioned semiconductor package stack combined structure, the dielectric coating for thermal silica. 在前述的半导体封装堆叠组合构造中,该第二封胶体可叠合接触于该第一封胶体。 In the aforementioned semiconductor package stack combined structure, the second seal contact with colloid can be laminated to the first seal colloid. 在前述的半导体封装堆叠组合构造中,该介电涂胶可部分或完全密封该焊接物质。 In the aforementioned semiconductor package stack combined structure, the dielectric coating may be partially or completely seal the solder material. 在前述的半导体封装堆叠组合构造中,该介电涂胶可为团块状或胶条状。 In the aforementioned semiconductor package stack combined structure, the dielectric coating may be a lump or rubber strips.

[0017] 借由上述技术方案,本发明保护外引脚之间焊点的半导体封装堆叠组合构造至少具有下列优点及有益效果: [0017] by means of a combination of a semiconductor package stack structure by the technical aspect, the present invention is to protect the solder joints between the outer pin has at least the following advantages and beneficial effects:

[0018] 1、本发明能够使外引脚之间焊点的应力分散,进而可以避免受到封胶体与导线架的热膨胀系数的差异导致焊点断裂的发生。 [0018] 1, the present invention enables the stress dispersion between the outer pin pad, and then prevented by the difference in thermal expansion coefficient of the package material and the lead frame lead to solder joint fracture occurs. 此外,还能够防止引脚之间电性短路,非常适于实用。 In addition, it is possible to prevent electrical short circuit between the pins, very fit for practical use.

[0019] 2、另外,本发明能够吸收封胶体与导线架的热膨胀系数的差异作用于外引脚之间焊点的应力,更加适于实用。 Role difference in thermal expansion coefficient [0019] 2. In addition, the present invention is capable of absorbing package material and the lead frame in between the outer lead solder joint stress, more fit for practical use.

[0020] 3、再者,本发明能够包覆焊接物质在外引脚之间焊点,有助于传导热量,而能够在高温下维持外引脚之间的电性连接,从而更加适于实用。 [0020] 3. Furthermore, the present invention can be coated with solder material between the outer lead solder, help conduct heat, and can maintain the electrical connection between the outer lead at a high temperature, and thus more suitable for practical .

[0021] 综上所述,本发明是有关一种保护外引脚之间焊点的半导体封装堆叠组合构造, 主要包括复数个相互堆叠的半导体封装件以及非导电性涂胶。 [0021] In summary, the present invention is a combination of a semiconductor package stack structure relates to a solder joint between the outer pin protection, including a plurality of semiconductor packages stacked on each other and non-conductive coating. 每一半导体封装件,包括至少一晶片、一导线架的复数外引脚及一封胶体,而该些外引脚是外露于该些封胶体的侧边。 Each semiconductor package including at least one chip, a plurality of pin-lead frame and a package material, and that these pins are exposed to the outside of these sides of the package material. 其中,一上层的半导体封装件的复数个外引脚的端面是焊接至一下层半导体封装件的对应外引脚的一区段。 Wherein, the outer end surface of a plurality of pins of a semiconductor package member is welded to the upper layer at a section of the semiconductor layer corresponding to the outer package pins. 该非导电性涂胶是沿着下层半导体封装件的封胶体侧边而形成于上层半导体封装件的外引脚端面,以部分或全部包覆上下层半导体封装件的外引脚之间的焊点。 Pin-end surface of the non-conductive coating along the lower side of the package material of the semiconductor package is formed in the upper layer of the semiconductor package to weld cladding on the lower part of or all of the semiconductor package pin-out between point. 藉以本发明可以达到外引脚之间焊点的应力分散并能够防止短路。 Whereby the present invention can be achieved between the outer lead solder joint stress is dispersed and a short circuit can be prevented. 本发明具有上述诸多优点及实用价值,其不论在产品结构或功能上皆有较大的改进,在技术上有显著的进步,并产生了好用及实用的效果,且较现有的半导体封装堆叠组合构造具有增进的突出功效,从而更加适于实用,诚为一新颖、进步、实用的新设计。 The present invention has the above advantages and practical value, regardless of Jieyou its structure or function of the product in major improvements in technology have significant progress, and produce useful and practical results, and more conventional semiconductor package Stacking combined structure has highlighted the effectiveness of the promotion, which is more suitable for practical, honest to a new, progressive, practical new design.

[0022] 上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图详细说明如下。 [0022] The above description is only an overview of the technical solution of the present invention, in order to more clearly understand the techniques of the present invention, and can be implemented in accordance with the prospectus, and in order to make the aforementioned and other objects, features and advantages of the present invention can be more apparent from the following features give the preferred embodiment, and with the detailed description of the drawings below.

附图说明 Brief Description

[0023] 图1是现有习知的半导体封装堆叠组合构造的前视示意图。 [0023] FIG. 1 is a front view showing the conventional semiconductor package stacking conventional combination structure.

[0024] 图2是现有习知的半导体封装堆叠组合构造的局部侧视示意图。 [0024] FIG. 2 is a partially schematic side view of a prior art conventional semiconductor package stacked structure in combination.

[0025] 图3是依据本发明的一具体实施例,一种保护外引脚之间焊点的半导体封装堆叠组合构造的截面示意图。 [0025] FIG. 3 is a cross-sectional schematic view of the combined structure of a semiconductor package stacking a specific embodiment of the present invention, a solder joint between the pin-protected basis.

[0026] 图4是依据本发明的一具体实施例,该半导体封装堆叠组合构造的局部侧视示意图。 [0026] Figure 4 is one embodiment according to the present invention, the semiconductor package stacked partial schematic side view of the combined structure.

[0027] 图5是依据本发明的一具体实施例,绘示该半导体封装堆叠组合构造的介电涂胶不同包覆型态的局部截面放大示意图。 [0027] FIG. 5 is one embodiment according to the present invention, illustrates a partial cross-sectional structure of the semiconductor package stack dielectric coating composition of different coating patterns enlarged schematic view.

[0028] 图6是依据本发明的一具体实施例,另一种保护外引脚之间焊点的半导体封装堆叠组合构造的局部侧视示意图。 [0028] Figure 6 is one embodiment of the present invention, a partial schematic side view of the stacked semiconductor package between the outer lead solder composition of another configuration of the protection.

[0029] 100 :半导体封装堆叠组合构造110 :第一半导体封装件 [0029] 100: stacking a semiconductor package 110 configured in combination: a first semiconductor package

[0030] 111:第一封胶体 112:第一晶片 [0030] 111: The first letter Colloid 112: first wafer

[0031] 113:第一外引脚 120:第二半导体封装件 [0031] 113: The first pin-120: a second semiconductor package

[0032] 121 :第二封胶体 122 :第二晶片 [0032] 121: The second letter Colloid 122: second wafer

[0033] 123:第二外引脚 130:焊接物质 [0033] 123: the second outer pin 130: welding material

[0034] 140:电路板 150 :焊料 [0034] 140: Circuit board 150: Solder

[0035] 200 :半导体封装堆叠组合构造210 :第一半导体封装件 [0035] 200: stacking a semiconductor package 210 configured in combination: a first semiconductor package

[0036] 211:第一封胶体 212:第一晶片 [0036] 211: The first letter Colloid 212: first wafer

[0037] 213:第一外引脚 214:外引脚区段 [0037] 213: The first pin-214: pin-section

[0038] 215 :第一焊线 216 :第一焊垫 [0038] 215: The first wire 216: the first pad

[0039] 217 :粘晶胶 220 :第二半导体封装件 [0039] 217: Crystal glue stick 220: second semiconductor package

[0040] 221 :第二封胶体 222 :第二晶片 [0040] 221: The second letter Colloid 222: second wafer

[0041] 223 :第二外引脚 224 :第二外引脚端面 [0041] 223: the second outer pin 224: second outer pin end face

[0042] 225 :第二焊线 226 :第二焊垫 [0042] 225: The second wire 226: second pad

[0043] 227 :粘晶胶 230 :焊接物质 [0043] 227: Crystal glue stick 230: welding material

[0044] 240:介电涂胶 240A:介电涂胶 [0044] 240: dielectric coating 240A: dielectric coating

[0045] 240B:介电涂胶 240C:介电涂胶 [0045] 240B: dielectric coating 240C: dielectric coating

[0046] 240,:介电涂胶 250:电路板 [0046] 240 ,: dielectric coating 250: PCB

[0047] 260 :焊料 [0047] 260: Solder

具体实施方式 DETAILED DESCRIPTION

[0048] 为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的保护外引脚之间焊点的半导体封装堆叠组合构造其具体实施方式、结构、特征及其功效,详细说明如后。 [0048] To further illustrate the present invention to achieve the intended purpose of the invention taken technical means and effectiveness, the accompanying drawings and the following preferred embodiment of the present invention according to the proposed protection between the pin-pad of a semiconductor package stacking combined structure specific embodiment, the structure, characteristics and effect, as described in detail later.

[0049] 有关本发明的前述及其他技术内容、特点及功效,在以下配合参考图式的较佳实施例的详细说明中将可清楚呈现。 [0049] The foregoing and other technology-related content, features and effectiveness of the present invention will be described in detail hereinafter with reference to the drawings of the preferred embodiment presented in clear. 通过具体实施方式的说明,当可对本发明为达成预定目的所采取的技术手段及功效得一更加深入且具体的了解,然而所附图式仅是提供参考与说明之用,并非用来对本发明加以限制。 By way of illustration a specific embodiment, when the invention can be taken to achieve the intended purpose of the technical means and efficacy have a more in-depth and specific knowledge, but the accompanying drawings and the description is provided for reference only, and are not used to the present invention be limited.

[0050] 请参阅图3与图4所示,是本发明一具体实施例所揭示的一种保护外引脚之间焊点的半导体封装堆叠组合构造。 [0050] See Figure 3 and Figure 4 is a semiconductor package stacked combination solder joint structure between the embodiment disclosed a protective outer pin an embodiment of the present invention. 图3是一种保护外引脚之间焊点的半导体封装堆叠组合构造的截面示意图,图4是该半导体封装堆叠组合构造的局部侧视示意图。 Figure 3 is a protective pad between the outer pin semiconductor package stacked combination of a cross-sectional schematic configuration, FIG. 4 is a partially schematic side view of the combined structure of the semiconductor package stack. 本发明一具体较佳实施例的保护外引脚之间焊点的半导体封装堆叠组合构造200,主要包括一第一半导体封装件210、至少一第二半导体封装件220、焊接物质230以及介电涂胶240。 The semiconductor package stacked between the protective outer lead solder composition according to one preferred embodiment of the present invention, the specific structure 200, including a first semiconductor package 210, the at least one second semiconductor package 220, welding 230 and a dielectric substance 240 glue.

[0051] 上述的第一半导体封装件210与该第二半导体封装件220,是可为单晶片封装或多晶片封装。 [0051] said first semiconductor package 210 and the second semiconductor package 220 is a single-chip package or the chip package. 如图3所示,在本实施例中,该第一半导体封装件210与该第二半导体封装件220皆为单晶片的薄小外形封装(TSOP)。 3, in this embodiment, the first semiconductor package 210 and the second semiconductor package 220 are all single wafer thin small outline package (TSOP).

[0052] 上述的第一半导体封装件210,包括一第一封胶体211、一被密封在该第一封胶体211的第一晶片212以及一导线架的复数个第一外引脚213 ; [0052] said first semiconductor package 210, comprising a first package material 211, is sealed in a package material of the first wafer 211 of the first lead frame 212 and a plurality of first external lead 213;

[0053] 该第一晶片212,其主动面设有一第一焊垫216,并可藉由粘晶胶217将该第一晶片212的主动面粘固于该导线架的该些第一外引脚213的被封胶区段的下表面,另以复数个打线形成的第一焊线215作为电连接元件,将该第一晶片212的该第一焊垫216电性连接至该导线架的该些第一外引脚213的被封胶区段的上表面。 [0053] The first wafer 212, which has a first active surface pad 216, and 217 by die attach adhesive cements the active surface of the first wafer 212 in the lead frame of the first of these outer lead The pin 213 is sealed plastic lower surface section of the first wire with a plurality of other wire 215 is formed as an electrical connecting element, the first wafer 212 of the first bonding pad 216 electrically connected to the lead frame Some of the first outer pin 213 is sealed plastic on the surface segment. 该第一封胶体211是形成在封胶(encapsulate)步骤中,以密封该第一晶片212、该些第一焊线215以及该些第一外引脚213的被封胶区段。 The first seal 211 is formed in a colloid sealant (encapsulate) step, to seal the first wafer 212, the first wire 215 and some of these first outer pin 213 is sealed plastic segments.

[0054] 该些第一外引脚213,是由该第一封胶体211的侧边延伸且外露。 [0054] The first of these outer pin 213, is extending from the first side of the package material 211 and exposed. 在本实施例中, 该些第一外引脚213是为海鸥脚(gull lead),用以表面接合至一电路板250,通常以焊料260焊接。 In the present embodiment, the first of these is an outer pin 213 Seagull foot (gull lead), to engage to a surface of the circuit board 250, the solder 260 is usually welded. 而该电路板250可以为主机板、记忆体模组载板、显示卡载板、记忆卡基板或手机通讯板等等。 And the circuit board 250 may be the motherboard, memory module carrier board, display card carrier board, memory card substrate or mobile communications board and so on.

[0055] 上述的第二半导体封装件220,接合于该第一半导体封装件210上,藉以做封装堆叠组合,完成多层的TSOP堆叠结构。 [0055] said second semiconductor package 220 is joined to the semiconductor package of the first member 210, in order to make the combination package stacking, the TSOP the multilayer stack structure. 该第二半导体封装件220包括一第二封胶体221、至少一被密封在该第二封胶体221的第二晶片222以及一导线架的复数个第二外引脚223 ;其中: The second semiconductor package 220 includes a second adhesive body 221, at least a second sealed package material 221 in the second wafer 222 and a lead frame of a plurality of second external pins 223; wherein:

[0056] 该些第二外引脚223,是由该第二封胶体221的侧边延伸且外露。 [0056] The second of these outer pin 223, is extending from the second side 221 of the package material and exposed. 较佳的,该些第二外引脚223可为垂直型态的I型脚,以使该些第二外引脚223的端面224能利用该焊接物质230焊接至该些第一外引脚213的一区段214(如图3所示的放大图)。 Preferably, the second of these outer pin 223 may be a vertical type I foot patterns, so that the pin 223 of these second outer end surface 224 can be welded using the welding material 230 to the plurality of first pin- a sector 213 214 (as shown in enlarged view in FIG. 3).

[0057] 如图3所示,在一具体实施例中,第二半导体封装件220更包括至少一粘晶胶227 与复数个第二焊线225。 [0057] 3, in a particular embodiment, the second semiconductor package 220 further includes at least one glue stick crystal 227 and a plurality of second wire 225.

[0058] 该粘晶胶227,是粘固该第二晶片222于该导线架的第二外引脚223或晶片承座(图未绘出)。 [0058] The die attach adhesive 227, is the anchor of the second wafer 222 in the second outer pin chip socket 223 or the wire rack (not shown).

[0059] 该些第二焊线225,是电性连接该第二晶片222的复数个第二焊垫226至对应的第二外引脚223。 [0059] The second of these wire 225 is electrically connected to the second wafer 222, a plurality of second pads 226 and 223 corresponding to the second external pins. [0060] 除了皆具有侧延伸的外引脚之外,该第二半导体封装件220的封装型态可与该第一半导体封装件210相同或不相同。 [0060] In addition to having both side outer pins extending outside the second semiconductor encapsulation package 220 may be the same or different patterns 210 and the first semiconductor package.

[0061] 通常该第一晶片212与该第二晶片222可为记忆体晶片,如快闪记忆体或是动态随机存取记忆体,藉以提高记忆体容量又不会增加表面接合面积。 [0061] Typically the first wafer 212 and the second wafer 222 for memory chips, such as flash memory or dynamic random access memory, in order to increase memory capacity without increasing the bonding surface area.

[0062] 该第一封胶体211与该第二封胶体221,可为环氧模封化合物(EpoxyMolding Compound, EMC)。 [0062] The first adhesive body 211 and the second adhesive body 221, for sealing epoxy molding compound (EpoxyMolding Compound, EMC). 此外,该第二封胶体221的底面是可叠合接触于该第一封胶体211的顶面,以缩小层叠的高度。 In addition, the bottom surface 221 of the second seal colloid is laminated in contact with the top surface of the first seal colloid 211 to narrow stacking height.

[0063] 另外,上述的焊接物质230,是焊接该些第二外引脚223的端面224与对应该些第一外引脚213的一区段214,藉以电性连接该些第二外引脚213与该些第二外引脚223。 [0063] Further, the above-described welding material 230 is welded to the second of these outer end surface 224 and the pin 223 of pin 213 should be those of a first outer segment 214, thereby electrically connecting the second external lead these some 213 feet to the second outer pin 223. 该焊接物质230为可熔焊导电金属,如锡铅或是无铅焊剂。 The welding material 230 to be welded conductive metal, such as lead or lead-free solder tin.

[0064] 请参阅图3,并结合参阅图4所示,上述的介电涂胶240,是沿着该第一半导体封装件210的第一封胶体211侧边而形成于第二半导体封装件220的该些第二外引脚223的端面224。 [0064] Please refer to FIG. 3, in conjunction with reference to Figure 4, the dielectric coating 240, the first semiconductor package along a first seal member 210 and the colloid formed in the second side 211 of the semiconductor package Some 220 of the second end surface of the outer pin 223 224. 在本实施例中,该介电涂胶240可为团块状,以连接该些第二外引脚223并包覆该焊接物质230,藉以分散该些外引脚213、223之间焊点(即该焊接物质230的位置)受到热膨胀系数差异的应力,而可达到防止外引脚的焊点断裂的功效。 In this embodiment, the dielectric coating 240 may be a mass, to connect the second outer pin 223 and those covering the soldering material 230, in order to disperse the joints between these external pin 213, 223 stress (i.e., the position of the welding material 230) by the difference in thermal expansion coefficient, and the pin-up to prevent the solder joint fracture effect. 其中,上述热膨胀系数差异是指导线架的该些外引脚213、223与封胶体211、221的热膨胀系数差异。 Wherein the thermal expansion coefficient differences between the guide wire frame these outer pin 213, 223 and the package material differences in the thermal expansion coefficient of 211,221.

[0065] 在本实施例中,该介电涂胶240并可以部分密封该焊接物质230的外侧。 [0065] In the present embodiment, the dielectric coating 240 and may be welded to the outer portion of the sealing material 230. 然而,介电涂胶的粘稠度与涂施量为可调整以改变成适当包覆面积与包覆形状,请参阅图5所示, 是依据本发明的一具体实施例,绘示该半导体封装堆叠组合构造的介电涂胶不同包覆型态的局部截面放大示意图。 However, viscosity and dielectric coating applicator is adjustable to vary the amount of covered area and covered an appropriate shape, see Figure 5, is based on a specific embodiment of the present invention, it illustrates the semiconductor partial cross-sectional structure of the combination package stacking dielectric coating covering different patterns enlarged schematic. 在不同的实施例中,一种介电涂胶240A并可部分密封该焊接物质230的内侧(如图5的A所示);一种介电涂胶240B并可完全密封该焊接物质230并具有较薄的覆盖厚度(如图5的B所示);一种介电涂胶240C并可完全密封该焊接物质230并具有较厚的覆盖厚度(如图5的C所示)。 In a different embodiment, a dielectric coating 240A and the inside of the welded portion of the seal material 230 (A shown in FIG. 5); a dielectric coating 240B and 230 is completely sealed and the welding material covered with a thin thickness (as shown in Fig. 5 B); a dielectric coating 240C and completely seal the solder material 230 and has a thicker coating thickness (as shown in Fig. 5 C).

[0066] 较佳地,该介电涂胶240可为低模数,以吸收该些第一外引脚213与该些第二外引脚223之间的应力,使其能吸收更大应力,而提高了该半导体封装堆叠组合构造200的抗冲击性、抗掉落性、抗热循环性与抗热冲击性。 [0066] Preferably, the dielectric coating 240 may be a low modulus, to absorb some of the first outer pin 213 between the pin 223 and the second outer these stresses, so that it can absorb greater stress , and improve the structure of the semiconductor package stack combination the impact resistance of 200, anti-drop, thermal cycling resistance and thermal shock resistance. 因此,该半导体封装堆叠组合构造200不会存在有外引脚之间焊点断裂的问题,而可提高产品的可靠性。 Thus, the semiconductor package stack combined structure 200 does not exist between the outer lead solder fracture problems, and can improve product reliability. 更具体而言,该介电涂胶240可为导热硅胶,其导热系数应相当于甚至高于该第一封胶体211或该第二封胶体221的导热系数,以帮助散热。 More specifically, the dielectric coating 240 may be a thermal silica, thermal conductivity shall be equal to or even higher than the first thermal conductivity of the package material 211 or 221 of the second seal colloid to help dissipate heat.

[0067] 请参阅图6所示,是依据本发明一具体实施例,另一种保护外引脚之间焊点的半导体封装堆叠组合构造的局部侧视示意图。 [0067] See Figure 6 is a partial side view of one embodiment of the present invention, another semiconductor package stack protection combined structure between the outer solder pin basis. 该保护外引脚之间焊点的半导体封装堆叠组合构造200,主要包括一第一半导体封装件210、至少一第二半导体封装件220、焊接物质230 以及非导电性涂胶240'。 The protective pad between the outer pin semiconductor package stacked structure 200 in combination, including a first semiconductor package 210, the at least one second semiconductor package 220, weld material 230 and a non-conductive adhesive 240 '. 除了非导电性涂胶240'的形状与上述实施例稍有不同之外,其它元件可概为相同,故沿用相同的标号。 In addition to the non-conductive adhesive 240 'is shaped slightly different from the above-described embodiment, the other components may be almost the same, it follows the same reference numerals.

[0068] 该第一半导体封装件210,包括一用以密封晶片的第一封胶体211以及一导线架的复数个第一外引脚213,可以利用焊料260焊接于一电路板250上。 [0068] The first semiconductor package 210 includes a first seal for sealing wafers colloidal lead frame 211, and a plurality of first external pins 213, 260 can be used welding solder a circuit board 250 in.

[0069] 该第二半导体封装件220,是接合于该第一半导体封装件210上,该第二半导体封装件220包括一用以密封晶片的第二封胶体221以及一导线架的复数个第二外引脚223。 [0069] The second semiconductor package 220 is joined to the semiconductor package of the first member 210, the second semiconductor package comprises a plurality of first member 220 to seal a second wafer 221 and a package material of the lead frame two pin-223.

[0070] 该焊接物质230,是焊接该些第二外引脚223的端面与对应该些第一外引脚213的一区段。 [0070] The welding material 230 is welded to the outer pin 223 of these second end face to be some of the first outer pin 213 of a section.

[0071] 该非导电性涂胶240',是沿着该第一半导体封装件210的第一封胶体211侧边而形成于第二半导体封装件220的该些第二外引脚223的端面,以连接该些第二外引脚223 并包覆该焊接物质230。 [0071] The non-conductive adhesive 240 ', is along the first semiconductor package 210 of the first side of the package material 211 is formed on the second end surface of the semiconductor package of the second outer pin some 220 223 to connect the second outer pin 223 and those covering the solder material 230. 藉以达到外引脚之间焊点的应力分散并防止短路。 In order to achieve stress dispersion between the outer pin joints and prevent short-circuiting. 较佳的,该非导电性涂胶240'是为胶条状,以非导电性串接不同第二外引脚223,而能够达到应力分散于不同外引脚的功效。 Preferably, the non-conductive coating 240 'is gum strip to cascade the second non-conductive outer pin 223, and to achieve stress dispersion in different pin-out effect.

[0072] 以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。 [0072] described above, only the preferred embodiment of the present invention, it is not the invention of any formal restrictions, although the present invention has been described with preferred embodiments anyone familiar with the drawings described above, however, not intended to limit the present invention, Those skilled in the art, without departing from the scope of the present invention within the program, when the technology can be used to reveal the contents of the above-mentioned omissions, or make substitutions and changes in the equivalent of examples, but those who present invention without departing from the technical solution, Any modification technique based on simple essence of the invention made by the above example embodiments, equivalent variation and modification as would fall within the scope of the present invention the technical solution.

Citas de patentes
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Clasificaciones
Clasificación internacionalH01L23/488, H01L25/00, H01L23/28
Clasificación cooperativaH01L2224/73215, H01L2224/4826, H01L2224/48091, H01L2224/32245
Eventos legales
FechaCódigoEventoDescripción
22 Abr 2009C06Publication
17 Jun 2009C10Request of examination as to substance
29 Sep 2010C14Granted