CN101416435B - 高速双向发信号的非对称控制 - Google Patents
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- CN101416435B CN101416435B CN2007800077529A CN200780007752A CN101416435B CN 101416435 B CN101416435 B CN 101416435B CN 2007800077529 A CN2007800077529 A CN 2007800077529A CN 200780007752 A CN200780007752 A CN 200780007752A CN 101416435 B CN101416435 B CN 101416435B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0023—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the signalling
- H04L1/0026—Transmission of channel quality indication
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/205—Arrangements for detecting or preventing errors in the information received using signal quality detector jitter monitoring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
- H04L1/243—Testing correct operation by comparing a transmitted test signal with a locally generated replica at the transmitter, using a loop-back
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L2001/0092—Error control systems characterised by the topology of the transmission link
- H04L2001/0094—Bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
Abstract
Description
Claims (8)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/368,785 US7729465B2 (en) | 2006-03-06 | 2006-03-06 | Asymmetric control of high-speed bidirectional signaling |
US11/368,785 | 2006-03-06 | ||
PCT/US2007/004375 WO2007102981A2 (en) | 2006-03-06 | 2007-02-20 | Asymmetric control of high-speed bidirectional signaling |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101416435A CN101416435A (zh) | 2009-04-22 |
CN101416435B true CN101416435B (zh) | 2012-04-04 |
Family
ID=38330441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800077529A Active CN101416435B (zh) | 2006-03-06 | 2007-02-20 | 高速双向发信号的非对称控制 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7729465B2 (zh) |
JP (1) | JP2009529289A (zh) |
KR (1) | KR20080100843A (zh) |
CN (1) | CN101416435B (zh) |
DE (1) | DE112007000574B4 (zh) |
GB (1) | GB2448651B (zh) |
TW (1) | TWI421699B (zh) |
WO (1) | WO2007102981A2 (zh) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7721160B2 (en) * | 2006-09-11 | 2010-05-18 | Advanced Micro Devices, Inc. | System for protecting data during high-speed bidirectional communication between a master device and a slave device |
US7783954B2 (en) * | 2006-09-11 | 2010-08-24 | Globalfoundries Inc. | System for controlling high-speed bidirectional communication |
US8131903B2 (en) * | 2007-04-30 | 2012-03-06 | Hewlett-Packard Development Company, L.P. | Multi-channel memory connection system and method |
US20090097401A1 (en) | 2007-10-12 | 2009-04-16 | Wael William Diab | Method and system for configurable data rate thresholds for energy efficient ethernet |
US7991098B2 (en) | 2007-10-31 | 2011-08-02 | Micron Technology, Inc. | Method and apparatus for training the reference voltage level and data sample timing in a receiver |
US20090259786A1 (en) * | 2008-04-10 | 2009-10-15 | Chu-Ming Lin | Data transfer system and method for host-slave interface with automatic status report |
US8713330B1 (en) * | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
WO2010093529A2 (en) * | 2009-02-12 | 2010-08-19 | Rambus Inc. | Memory interface with reduced read-write turnaround delay |
JP2011130008A (ja) * | 2009-12-15 | 2011-06-30 | Hitachi-Lg Data Storage Inc | データ入出力装置 |
TWI435596B (zh) * | 2010-07-06 | 2014-04-21 | Realtek Semiconductor Corp | 應用於網路裝置之主從決定裝置及主從決定方法 |
CN102868567B (zh) * | 2011-07-05 | 2015-05-20 | 瑞昱半导体股份有限公司 | 应用于网络装置的主从判定装置及主从判定方法 |
US8495440B2 (en) | 2011-08-30 | 2013-07-23 | Advanced Micro Devices, Inc. | Fully programmable parallel PRBS generator |
JP6162514B2 (ja) | 2013-07-12 | 2017-07-12 | 東芝メディカルシステムズ株式会社 | 磁気共鳴イメージング装置 |
US10122392B2 (en) * | 2016-08-18 | 2018-11-06 | Advanced Micro Devices, Inc. | Active equalizing negative resistance amplifier for bi-directional bandwidth extension |
US10896723B2 (en) * | 2019-04-30 | 2021-01-19 | Ambient Scientific Inc. | Signal communication circuit implementing receiver and transmitter circuits |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010038674A1 (en) * | 1997-07-31 | 2001-11-08 | Francois Trans | Means and method for a synchronous network communications system |
JP2004213438A (ja) * | 2003-01-07 | 2004-07-29 | Matsushita Electric Ind Co Ltd | データ転送回路 |
US6839393B1 (en) * | 1999-07-14 | 2005-01-04 | Rambus Inc. | Apparatus and method for controlling a master/slave system via master device synchronization |
US20060034358A1 (en) * | 2004-08-16 | 2006-02-16 | Hitoshi Okamura | Methods and transmitters for loop-back adaptive pre-emphasis data transmission |
Family Cites Families (25)
Publication number | Priority date | Publication date | Assignee | Title |
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US4763249A (en) * | 1983-09-22 | 1988-08-09 | Digital Equipment Corporation | Bus device for use in a computer system having a synchronous bus |
JP2570845B2 (ja) * | 1988-05-27 | 1997-01-16 | セイコーエプソン株式会社 | 情報処理装置 |
EP0619547A1 (en) * | 1993-04-05 | 1994-10-12 | Motorola, Inc. | A method of requesting data and apparatus therefor |
JP2738340B2 (ja) * | 1995-05-11 | 1998-04-08 | 日本電気株式会社 | マルチアクセス通信方式 |
US6029250A (en) * | 1998-09-09 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same |
US6434650B1 (en) * | 1998-10-21 | 2002-08-13 | Intel Corporation | Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6467012B1 (en) * | 1999-07-08 | 2002-10-15 | International Business Machines Corporation | Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors |
US6316966B1 (en) | 1999-07-16 | 2001-11-13 | Conexant Systems, Inc. | Apparatus and method for servo-controlled self-centering phase detector |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US6321282B1 (en) | 1999-10-19 | 2001-11-20 | Rambus Inc. | Apparatus and method for topography dependent signaling |
US6975585B1 (en) | 2000-07-27 | 2005-12-13 | Conexant Systems, Inc. | Slotted synchronous frequency division multiplexing for multi-drop networks |
US6898726B1 (en) * | 2000-11-15 | 2005-05-24 | Micron Technology, Inc. | Memory system that sets a predetermined phase relationship between read and write clock signals at a bus midpoint for a plurality of spaced device locations |
US6516282B2 (en) | 2001-04-19 | 2003-02-04 | Ge Medical Systems Global Technology Company | Predictive thermal control used with a vacuum enclosed coil assembly of a magnetic resonance imaging device |
JP2003050738A (ja) | 2001-08-03 | 2003-02-21 | Elpida Memory Inc | キャリブレーション方法及びメモリシステム |
US6877103B2 (en) | 2001-10-05 | 2005-04-05 | Via Technologies, Inc. | Bus interface timing adjustment device, method and application chip |
US7362800B1 (en) | 2002-07-12 | 2008-04-22 | Rambus Inc. | Auto-configured equalizer |
US20040268190A1 (en) | 2003-05-19 | 2004-12-30 | International Business Machines Corporation | Adjusting parameters of a serial link |
US7165153B2 (en) * | 2003-06-04 | 2007-01-16 | Intel Corporation | Memory channel with unidirectional links |
US7234070B2 (en) | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7516029B2 (en) | 2004-06-09 | 2009-04-07 | Rambus, Inc. | Communication channel calibration using feedback |
US7305574B2 (en) | 2004-10-29 | 2007-12-04 | International Business Machines Corporation | System, method and storage medium for bus calibration in a memory subsystem |
US7346795B2 (en) | 2004-12-31 | 2008-03-18 | Intel Corporation | Delaying lanes in order to align all lanes crossing between two clock domains |
US7590173B2 (en) | 2005-06-30 | 2009-09-15 | Intel Corporation | System and method for performing adaptive phase equalization |
US7370247B2 (en) | 2005-09-28 | 2008-05-06 | Intel Corporation | Dynamic offset compensation based on false transitions |
-
2006
- 2006-03-06 US US11/368,785 patent/US7729465B2/en active Active
-
2007
- 2007-02-20 GB GB0815491A patent/GB2448651B/en not_active Expired - Fee Related
- 2007-02-20 WO PCT/US2007/004375 patent/WO2007102981A2/en active Application Filing
- 2007-02-20 KR KR1020087024453A patent/KR20080100843A/ko not_active Application Discontinuation
- 2007-02-20 DE DE112007000574T patent/DE112007000574B4/de active Active
- 2007-02-20 JP JP2008558284A patent/JP2009529289A/ja active Pending
- 2007-02-20 CN CN2007800077529A patent/CN101416435B/zh active Active
- 2007-03-03 TW TW096107334A patent/TWI421699B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010038674A1 (en) * | 1997-07-31 | 2001-11-08 | Francois Trans | Means and method for a synchronous network communications system |
US6839393B1 (en) * | 1999-07-14 | 2005-01-04 | Rambus Inc. | Apparatus and method for controlling a master/slave system via master device synchronization |
JP2004213438A (ja) * | 2003-01-07 | 2004-07-29 | Matsushita Electric Ind Co Ltd | データ転送回路 |
US20060034358A1 (en) * | 2004-08-16 | 2006-02-16 | Hitoshi Okamura | Methods and transmitters for loop-back adaptive pre-emphasis data transmission |
Non-Patent Citations (1)
Title |
---|
JP特开2004213438A 2004.07.29 |
Also Published As
Publication number | Publication date |
---|---|
KR20080100843A (ko) | 2008-11-19 |
WO2007102981A3 (en) | 2007-11-29 |
GB2448651A (en) | 2008-10-22 |
DE112007000574T5 (de) | 2009-01-22 |
US7729465B2 (en) | 2010-06-01 |
US20070208819A1 (en) | 2007-09-06 |
WO2007102981A2 (en) | 2007-09-13 |
TWI421699B (zh) | 2014-01-01 |
TW200801961A (en) | 2008-01-01 |
CN101416435A (zh) | 2009-04-22 |
GB0815491D0 (en) | 2008-10-01 |
DE112007000574B4 (de) | 2013-11-28 |
JP2009529289A (ja) | 2009-08-13 |
GB2448651B (en) | 2010-11-17 |
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Owner name: GLOBALFOUNDRIES INC. Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20100730 |
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Effective date of registration: 20100730 Address after: Grand Cayman, Cayman Islands Applicant after: Globalfoundries Semiconductor Inc. Address before: American California Applicant before: Advanced Micro Devices Inc. |
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Effective date of registration: 20201217 Address after: California, USA Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Patentee before: GLOBALFOUNDRIES Inc. |
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Effective date of registration: 20210316 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Patentee after: MEDIATEK Inc. Address before: California, USA Patentee before: Lattice chip (USA) integrated circuit technology Co.,Ltd. |