CN101421830A - 无限选择性的光刻胶掩膜蚀刻 - Google Patents
无限选择性的光刻胶掩膜蚀刻 Download PDFInfo
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Abstract
提供一种用于将特征蚀刻入蚀刻层的方法,该蚀刻层设在光刻胶掩膜下方而没有中间硬掩膜。提供多个蚀刻循环。每个蚀刻循环包括提供沉积蚀刻阶段,其将特征蚀刻入该蚀刻层和将聚合物沉积在这些特征的侧壁上和该光刻胶之上,以及提供清理阶段,其去除沉积在这些侧壁上的聚合物。
Description
背景技术
[0001]本发明涉及半导体器件的形成。更具体地,本发明涉及通过在蚀刻层中蚀刻特征形成半导体器件。
[0002]在半导体晶片处理过程中,使用公知的图案化和蚀刻工艺在晶片中形成半导体器件的特征。在这些工艺中,光刻胶(PR)材料沉积在晶片上并且之后暴露于由中间掩模过滤的光线。该中间掩模可以是图案化为具有模板特征几何形状的玻璃板,该几何形状阻止光线透过该中间掩模。
[0003]穿过中间掩模之后,光线接触光刻胶材料的表面。光线改变光刻胶材料的化学成分,从而显影剂可以去除一部分光刻胶材料。对于正光刻胶材料,暴露部分被去除,而对于负光刻胶材料,未暴露部分被去除。其后该晶片被蚀刻,这样,下层材料被从不再受该光刻胶材料保护的区域去除,并由此在该晶片中形成所需的特征。
[0004]在基于半导体的设备(例如,集成电路或平面显示器)制造中,双镶嵌结构可连同铜导体材料一起使用,用以减小与用于前一代技术的铝基材料中的信号传播有关的RC延迟。在双镶嵌中,蚀刻该介电材料,而非该导体材料,从而形成过孔和沟槽,并且用铜填充该过孔和沟槽。
[0005]通常,在蚀刻下层材料过程中,一些光刻胶材料被去除。被蚀刻的下层材料的量相对被蚀刻的光刻胶材料的比用来确定蚀刻选择性(selectivity)。
发明内容
[0006]为了实现前述和按照本发明的目的,提供一种将特征蚀刻入蚀刻层的方法,该蚀刻层设在光刻胶掩模下方而没有中间硬掩模。提供多个蚀刻循环。每个蚀刻循环包括提供沉积蚀刻阶段,其将特征蚀刻入该蚀刻层并且将聚合物沉积在这些特征的侧壁上和该光刻胶上,以及提供清理阶段,其去除沉积在该侧壁上的聚合物。
[0007]在本发明的另一表现形式中,提供一种将特征蚀刻入蚀刻层的方法,该蚀刻层设在光刻胶掩模下方而没有中间硬掩模。提供15到50个具有无限选择性(infinitely selective)的蚀刻循环蚀刻。每个蚀刻循环包括提供沉积蚀刻阶段,其将特征蚀刻入该蚀刻层并且将聚合物沉积在这些特征的侧壁上和该光刻胶上,以及提供清理阶段,其去除沉积在这些侧壁上的聚合物。
[0008]本发明的另一表现形式中,提供一种用于在蚀刻层中形成特征的装置,其中该蚀刻层由基片支撑,以及其中该蚀刻层由光刻胶掩模覆盖而没有中间硬掩模。等离子处理室提供有形成等离子处理室外壳的室壁。基片支撑件在该等离子处理室外壳内支撑基片。压力调节器调节该等离子处理室外壳中的压力。至少一个电极向该等离子处理室外壳提供能源,用以维持等离子。气体入口提供气体进入该等离子处理室外壳。气体出口从该等离子处理室外壳排出气体。气体源与该气体入口流体连接,并包括蚀刻气体源、沉积气体源和清理阶段气体源。控制器可控制地连接到该气体源和该至少一个电极。该控制器包括至少一个处理器和计算机可读介质。该计算机可读介质包括用于提供15到50个蚀刻循环的计算机可读代码,该计算机可读代码包括用于提供沉积蚀刻阶段的计算机可读代码(该阶段将特征蚀刻入该蚀刻层以及将聚合物沉积在这些特征的侧壁上和该光刻胶之上),该用于提供沉积蚀刻阶段的计算机可读代码包括用于从该蚀刻气体源提供蚀刻气体的计算机可读代码、用于由该蚀刻气体生成等离子的计算机可读代码、用于从该沉积气体源提供沉积气体的计算机可读代码、用于由该沉积气体生成等离子的计算机可读代码和用于停止该沉积和蚀刻阶段的计算机可读代码;以及用于提供清理阶段的计算机可读代码(该阶段去除沉积在这些侧壁上的聚合物),该用于提供清理阶段的计算机可读代码包括用于从该清理阶段气体源提供清理阶段气体的计算机可读代码、用于从该清理阶段气体生成等离子的计算机可读代码和用于停止该清理阶段的计算机可读代码。
[0009]本发明的这些和其他特征将在下面的具体描述中结合附图更详细地说明。
附图说明
[0010]在附图中,本发明作为示例而不是作为限制来说明,其中相似的参考标号表示类似的要素,并且其中:
[0011]图1是在本发明实施方式中使用的、在蚀刻层中形成特征的高级流程图。
[0012]图2A-D按照图1所示的实施方式的形成特征的示意图。
[0013]图3是两步骤沉积蚀刻阶段的更详细的流程图。
[0014]图4是可用来蚀刻和剥离的等离子处理室的示意图。
[0015]图5A-B说明适于实现用于本发明实施方式的控制器的计算机系统。
具体实施方式
[0016]现在将根据其几个优选实施方式更详细地描述本发明在下面的描述中,阐述许多具体细节以提供对本发明的彻底理解。然而,对于本领域技术人员,显然,本发明可不利用这些具体细节的一些或者全部而实施。在有的情况下,公知的工艺步骤和/或结构没有说明,以避免不必要的混淆本发明。
[0017]为了便于理解,图1是本发明实施方式中使用的工艺的高级流程图。在蚀刻层之上提供过孔掩模(步骤104)。图2是堆栈200的剖视图,其具有形成在阻挡层212之上的蚀刻层220,该阻挡层形成在晶片210之上。在这个例子中,层208设置在该阻挡层212和该晶片210之间。尽管该层208示为形成在该晶片210上,在该蚀刻层220和该晶片210之间可以形成任意数目的层。在这个例子中,该阻挡层212可以是碳化硅(SiC)层或其也可以是SiN。该蚀刻层220可以是低k电介质,如有机硅酸盐电介质和多孔电介质,包括CORALTM,来自San Jose,California的Novellus;Black DiamondTM,来自Santa Clara,California的Applied Materials;AuroraTM,可从Netherlands的ASM International N.V.得到;Sumika ,可从SantaClara,California的Sumitomo Chemical America,Inc.得到;HOSPTM,来自Morristown,New Jersey的AlliedSignal;SiLKTM或高级多孔SiLK,来自DOW Chemical Company;OrionR FlowfillTM,来自Trikon;和LKDTM,来自JSR Corp。
[0018]该过孔图案的形成可通过在该蚀刻层220上形成抗反射层(ARL)216来进行。该ARL216可以通过旋涂沉积来形成。
[0019]光刻胶掩模232形成在该ARL216之上(步骤104)。该光刻胶掩模可通过将光刻胶层暴露于图案化的光线,然后显影该光刻胶层232以在该光刻胶层中获得过孔224。
[0020]将特征有选择地蚀刻入该蚀刻层220(步骤108)。该选择性蚀刻包括多个循环,其中每个循环包括沉积蚀刻阶段(步骤112)和聚合物清理阶段(步骤116)。
[0021]该沉积蚀刻阶段(步骤112)相对该光刻胶掩模232有选择地蚀刻该蚀刻层220,并且将聚合物沉积在该特征的侧壁上以及该光刻胶上。图2B是该堆栈200在沉积蚀刻阶段(步骤112)之后的剖视图。已经执行了一个或多个蚀刻循环。该沉积蚀刻阶段蚀刻特征234的一部分,同时将聚合物层236沉积在这些特征234的侧壁上以及该光刻胶掩模232之上。这样一个沉积蚀刻阶段优选为无限选择性,因为这样一个阶段蚀刻该蚀刻层220而没有蚀刻该光刻胶掩模232,而是在该光刻胶掩模232上形成聚合物层236。
[0022]该聚合物清理阶段(步骤116)去除该沉积的聚合物。图2C是该堆栈200在聚合物清理阶段之后的剖视图。已经执行了一个或多个蚀刻循环。该聚合物清理阶段去除该特征的侧壁上沉积的聚合物。在该优选实施方式中,该蚀刻层在该聚合物清理阶段期间没有蚀刻。在其他实施方式中,该聚合物清理阶段可蚀刻在这些特征底部的蚀刻层。
[0023]该蚀刻循环优选地执行10到100个循环。更优选地,该蚀刻循环执行15到50个循环。最优选地,该蚀刻循环执行大约20个循环。
[0024]图2D是在该选择性蚀刻(步骤108)完成之后该堆栈200的剖视图。在这个例子中,这些特征234被蚀刻为完全穿过该蚀刻层220。该光刻胶掩模232没有被蚀刻,提供无限选择性。
[0025]然后剥离该光刻胶掩模232(步骤120)。
[0026]优选地,这些特征234的侧壁是垂直的。优选地,该垂直的侧壁是从底部到顶部与这些特征的底部成88°到90°之间角度的侧壁。
[0027]优选地,该蚀刻层是介电层。更优选地,该蚀刻层是低k介电层。最优选地,该介电层是二氧化硅基低k介电层。
[0028]在没有该聚合物清理阶段(步骤116)的情况下,连续的沉积蚀刻阶段将持续在这些特征的侧壁上增加更多的聚合物。结果,这些特征的宽度将降低,产生锥形的而不是垂直的侧壁。这样的过程会导致蚀刻停止,这将限制蚀刻的宽度。
单个步骤沉积蚀刻阶段的示例
[0029]本发明的优选实施方式的示例中,该基片210是硅晶片以及该介电蚀刻层220是OSG(有机硅酸盐玻璃)或珊瑚(Coral)。在该优选实施方式中,该阻挡层由SiC形成。使用ArF(193nmPR)光刻胶形成该掩模(步骤104)。在该优选实施方式中,该ARC层是底部抗反射层(BARC)。该基片210设在等离子处理室中。
[0030]图4是可用于蚀刻和剥离的等离子处理室400的示意图。该等离子处理室400包括限制环402、上部电极404、下部电极408、气体源410和排气泵420。该气体源410可包括蚀刻气体源、沉积气体源和清理阶段气体源。在等离子处理室400内,该基片210设在该下部电极408上。该下部电极408结合合适的基片卡紧机构(例如静电、机械夹紧等),用于把持该基片210。该反应器顶部428结合正对着该下部电极408设置的该上部电极404。该上部电极404、下部电极408和限制环402形成该受限制的等离子容积440。气体由该气体源410提供到该受限制的等离子容积,并且由该排气泵420通过这些限制环402和排气口排出该受限制的等离子容积。第一RF源444电连接到该上部电极404。第二RF源448电连接到该下部电极408。室壁452围绕这些限制环402、该上部电极404和该下部电极408。该第一RF源444和该第二RF源448两者都可包括27MHz电源、60MHz电源和2MHz电源。将RF功率连接到该电极的不同组合是可能的。在本发明的优选实施方式中,该27MHz、60MHz和2MHz电源构成该第二RF电源448,其连接到该下部电极,并且该上部电极接地。控制器435可控地连接到该RF源444、448、排气泵420和该气体源410。这样的一个装置能够调节每个阶段的室压力、气体流量、气体组合、RF功率和持续时间。
[0031]图5A和5B说明了一个计算机系统500,其适于实现用于本发明实施方式的控制器435。图5A示出该计算机系统一种可能的物理形式。当然,该计算机系统可以具有从集成电路、印刷电路板和小型手持设备到巨型超级计算机的许多物理形式。计算机系统500包括监视器502、显示器504、机箱506、磁盘驱动器508、键盘510和鼠标512。磁盘514是用来与计算机系统500传入和传出数据的计算机可读介质。
[0032]图5B是计算机系统500的框图的一个例子。连接到系统总线520的是各种各样的子系统。处理器522(也称为中央处理单元,或CPU)连接到存储设备,包括存储器524。存储器524包括随机访问存储器(RAM)和只读存储器(ROM)。如本领域所公知的,ROM用来向CPU单向传输数据和指令,而RAM通常用来以双向的方式传输数据和指令。这两种类型的存储器可包括下面描述的任何合适的计算机可读介质。固定磁盘526也是双向连接到CPU522;其提供额外的数据存储容积并且也包括下面描述的任何计算机可读介质。固定磁盘526可用来存储程序、数据等,并且通常是次级存储介质(如硬盘),其比主存储器慢。可以理解的是保留在固定磁盘526内的信息可以在适当的情况下作为虚拟存储器以标准的方式结合在存储器524中。可移动磁盘514可以采用下面描述的任何计算机可读介质的形式。
[0033]CPU 522还连接到各种输入/输出设备,如显示器504、键盘510、鼠标512和扬声器530。通常,输入/输出设备可以是下面的任何一种:视频显示器、轨迹球、鼠标、键盘、麦克风、触摸显示器、转换器读卡器、磁带或纸带阅读器、书写板、触针、语音或手写识别器、生物阅读器或其他计算机。CPU 522视情况可使用网络接口540连接到另一台计算机或者电信网络。利用这样的网络接口,在执行上述方法步骤地过程中,CPU预计可从网络接收信息或者向网络输出信息。此外,本发明的方法实施方式可在CPU 522上单独执行或者可在如Internet的网络上与共享一部分该数据处理的远程CPU一起执行。
[0034]另外,本发明的实施方式进一步涉及具有计算机可读介质的计算机存储产品,在计算机可读介质上有用于执行各种计算机实现的操作的计算机代码。该介质和计算机代码可以是那些为本发明目的专门设计和构建的,或者它们可以是对于计算机软件领域技术人员来说公知并且可以得到的那种。计算机可读介质的例子包括,但不限于:磁介质,如硬盘、软盘和磁带;光介质,如CD-ROM和全息设备;磁-光介质,如光软盘;以及专门用于存储和执行程序代码的硬件设备,如专用集成电路(ASIC)、可编程逻辑器件(PLD)以及ROM和RAM器件。计算机代码的例子包括如由编译器生成的机器代码,以及包含高级代码的文件,该高级代码能够由计算机使用翻译器来执行。计算机可读介质还可以是在载波中由计算机数据信号传输并且表示能够被处理器执行的指令序列的计算机代码。
[0035]有选择地将特征蚀刻入该蚀刻层220(步骤108)。该选择性蚀刻包括多个循环,其中每个循环包括沉积蚀刻阶段(步骤112)和聚合物清理阶段(步骤116)。
[0036]用于沉积蚀刻阶段(步骤112)的示例制法如下:提供40sccmCF4和90sccmH2组成的沉积蚀刻阶段气体。室压设为90mTorr。由该27MHzRF源提供1200W以及由该2MHz电源提供400W。在这个例子中,沉积蚀刻是在单个步骤中同时完成的。
[0037]用于聚合物清理阶段(步骤116)的示例制法如下:提供300sccmO2的聚合物清理阶段气体。室压设为250mTorr。由该27MHzRF源提供100W,以及由该2MHz电源提供0W。
[0038]然后剥离该沟槽掩模(步骤120)。示例性的掩模剥离提供10~3000sccmO2的剥离气体。室压设为5~500mTorr。由该2MHz、27MHzRF源或2MHz和27MHzRF电源两者组合提供100~1000W。
两步骤沉积蚀刻阶段的示例
[0039]在另一个例子中,使用两步骤沉积蚀刻阶段,第一步骤用来沉积聚合物,第二步骤用来蚀刻该蚀刻层。使用与之前的例子中同样的基片和蚀刻层。掩模形成在该蚀刻层之上(步骤104)。有选择地将特征蚀刻入该蚀刻层220(步骤108)。图3是本例中该沉积蚀刻阶段(步骤112)更详细的流程图。在这个例子中,每个沉积蚀刻阶段包括将聚合物顺次沉积在光刻胶和侧壁上的步骤(步骤304),以及之后的蚀刻特征步骤(步骤308)。在一个实施方式中,对于每个沉积蚀刻阶段(步骤112)执行单个沉积聚合物步骤(步骤304)和接着的单个蚀刻特征步骤(步骤308)。在另一个实施方式中,对于每个沉积蚀刻阶段(步骤112),重复多次单个沉积聚合物步骤(步骤304)和接着的单个蚀刻特征步骤(步骤308)组成的循环过程。
[0040]用于将聚合物沉积在光刻胶和侧壁上步骤(步骤304)的示例制法如下:提供50sccmCH3F和250sccmAr组成的沉积聚合物气体。该室压设为40mTorr。由该27MHzRF源提供500W和由该2MHz电源提供200W,以由该沉积聚合物气体生成等离子。
[0041]用于蚀刻特征步骤(步骤308)的示例制法如下:提供25sccmC4F6、24sccmO2和200sccmAr组成的蚀刻气体。该室压设为40mTorr。由该27MHzRF源提供1200W和由该2MHz电源提供1200W,以由该蚀刻气体生成等离子。
[0042]用于聚合物清理阶段(步骤116)的示例制法如下:提供25sccmC4F6、35sccmO2和200sccmAr组成的聚合物清理阶段气体。该室压设为35mTorr。由该27MHzRF源提供1200W和由该2MHz电源提供1200W,以由该聚合物清理阶段气体生成等离子。
[0043]然后剥离该掩模(步骤120)。在上面的例子中的制法可用来剥离该掩模。
[0044]在这些例子中,该等离子处理室应当能够调节每个阶段的室压、气体流量、气体组合、RF功率和持续时间。
[0045]尽管已经就多个实施方式对本发明进行了描述,仍存在落入本发明范围内的改变、置换和各种替代等同物。还应当注意,有许多实现本发明方法和设备的可选方式。所以,下面所附权利要求的含义应当解释为包括所有这样的落入本发明主旨和范围内的改变、置换和各种替代等同物。
Claims (17)
1.一种用于将特征蚀刻入蚀刻层的方法,该蚀刻层设在光刻胶掩模下方而没有中间硬掩模,该方法包括:
提供多个蚀刻循环,其中每个蚀刻循环包括:
提供沉积蚀刻阶段,其将特征蚀刻入该蚀刻层以及将聚合物沉积在这些特征的侧壁上和该光刻胶之上;以及
提供清理阶段,其去除沉积在这些侧壁上的聚合物。
2.如权利要求1所述的方法,其中该提供多个循环包括提供10到100个循环。
3.如权利要求1所述的方法,其中该提供多个循环包括提供15到50个循环。
4.如权利要求1-3任一项所述的方法,其中沉积蚀刻阶段相对该光刻胶掩模有选择地蚀刻该蚀刻层。
5.如权利要求1-4任一项所述的方法,其中该清理阶段相对该蚀刻层有选择地去除沉积在这些侧壁上的聚合物。
6.如权利要求1-5任一项所述的方法,其中该沉积蚀刻阶段包括单个步骤,其同时蚀刻该蚀刻层和将聚合物沉积在这些特征的侧壁上。
7.如权利要求1-5任一项所述的方法,其中该沉积蚀刻阶段包括蚀刻步骤,其蚀刻该蚀刻层;以及
沉积步骤,其将聚合物沉积在这些特征的侧壁上,其中该蚀刻步骤和沉积步骤是顺次的而不是同时的。
8.如权利要求1-7任一项所述的方法,其中该沉积蚀刻阶段并不去除该光刻胶掩模,提供无限选择性。
9.如权利要求1-6和8任一项所述的方法,其中该提供沉积蚀刻阶段,包括:
提供蚀刻气体;
由该蚀刻气体生成等离子;
提供沉积气体;
由该沉积气体生成等离子;以及
停止该沉积蚀刻阶段,以及其中提供清理阶段包括:
提供清理阶段气体;
由该清理阶段气体生成等离子;以及
停止该清理阶段。
10.如权利要求1-9任一项所述的方法,其中该蚀刻特征具有底部和侧壁,该侧壁从底部到顶部与这些特征的底部成88°到90°角。
11.如权利要求1-10任一项所述的方法,其中该蚀刻特征具有垂直侧壁。
12.一种由权利要求1-11任一项所述的方法形成的半导体器件。
13.一种用于实施权利要求1-11任一项所述的方法的设备。
14.一种用于将特征蚀刻入蚀刻层的方法,该蚀刻层设在光刻胶掩模下方而没有中间硬掩模,该方法包括:
提供15到50个蚀刻循环,其相对该光刻胶掩模以无限选择性蚀刻该蚀刻层,其中每个蚀刻循环包括:
提供沉积蚀刻阶段,其将特征蚀刻入该蚀刻层和将聚合物沉积在这些特征的侧壁上和该光刻胶之上;以及
提供清理阶段,其去除沉积在这些侧壁上的聚合物。
15.如权利要求14所述的方法,其中该蚀刻特征具有底部和侧壁,该侧壁从底部到顶部与这些特征的底部成88°到90°角。
16.如权利要求14-15任一项所述的方法,其中该提供沉积蚀刻阶段,包括:
提供蚀刻气体;
由该蚀刻气体生成等离子;
提供沉积气体;
由该沉积气体生成等离子;以及
停止该沉积蚀刻阶段,以及其中该提供清理阶段包括:
提供清理阶段气体;
由该清理阶段气体生成等离子;以及
停止该清理阶段。
17.一种用于在蚀刻层中形成特征的设备,其中该蚀刻层是由基片支撑,以及其中该蚀刻层是由光刻胶掩模覆盖而没有中间硬掩模,该设备包括:
等离子处理室,包括:
室壁,其形成等离子处理室外壳;
基片支撑件,其用于在该等离子处理室外壳内支撑基片;
压力调节器,其用于调节该等离子处理室外壳的压力;
至少一个电极,其用于提供能量到该等离子处理室外壳,用于维持等离子;
气体入口,其用于提供气体进入该等离子处理室外壳;以及
气体出口,其用于从该等离子处理室外壳排出气体;气体源,其与该气体入口流体连接,包括:
蚀刻气体源;
沉积气体源;以及
清理阶段气体源;以及
控制器,其可控制地连接到该气体源和该至少一个电极,包括:
至少一个处理器;以及
计算机可读介质,包括:
计算机可读代码,其用于提供15到50个蚀刻循环,其相对该光刻胶掩模蚀刻该蚀刻层,包括:
用于提供沉积蚀刻阶段的计算机可读代码,该沉积蚀刻阶段将特征蚀刻入该蚀刻层以及将聚合物沉积在这些特征的侧壁上和该光刻胶之上,该计算机可读代码包括:
用于从该蚀刻气体源提供蚀刻气体的计算机可读代码;
用于由该蚀刻气体生成等离子的计算机可读代码;
用于从该沉积气体源提供沉积气体的计算机可读代码;
用于由该沉积气体生成等离子的计算机可读代码;以及
用于停止该沉积和蚀刻阶段的计算机可读代码;
以及
用于提供清理阶段的计算机可读代码,该清理阶段去除沉积在这些侧壁上的聚合物,该计算机可读代码包括:
用于从该清理阶段气体源提供清理阶段气体的计算机可读代码;
用于从该清理阶段气体生成等离子的计算机可读代码;以及
用于停止该清理阶段的计算机可读代码。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7682516B2 (en) * | 2005-10-05 | 2010-03-23 | Lam Research Corporation | Vertical profile fixing |
JP5103006B2 (ja) | 2006-11-16 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US20080203056A1 (en) * | 2007-02-26 | 2008-08-28 | Judy Wang | Methods for etching high aspect ratio features |
US8901004B2 (en) * | 2009-07-27 | 2014-12-02 | Lam Research Corporation | Plasma etch method to reduce micro-loading |
KR101082134B1 (ko) | 2010-03-16 | 2011-11-09 | 삼성모바일디스플레이주식회사 | 드라이 에칭 장치를 이용한 터치 스크린 패널의 제작방법 |
US8608973B1 (en) * | 2012-06-01 | 2013-12-17 | Lam Research Corporation | Layer-layer etch of non volatile materials using plasma |
US20140051256A1 (en) * | 2012-08-15 | 2014-02-20 | Lam Research Corporation | Etch with mixed mode pulsing |
JP6267953B2 (ja) * | 2013-12-19 | 2018-01-24 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
US9159561B2 (en) | 2013-12-26 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for overcoming broken line and photoresist scum issues in tri-layer photoresist patterning |
US9595451B1 (en) | 2015-10-19 | 2017-03-14 | Applied Materials, Inc. | Highly selective etching methods for etching dielectric materials |
US10497578B2 (en) | 2016-07-22 | 2019-12-03 | Applied Materials, Inc. | Methods for high temperature etching a material layer using protection coating |
US20180323061A1 (en) * | 2017-05-03 | 2018-11-08 | Tokyo Electron Limited | Self-Aligned Triple Patterning Process Utilizing Organic Spacers |
JP6878174B2 (ja) * | 2017-06-29 | 2021-05-26 | 東京エレクトロン株式会社 | プラズマエッチング方法及びプラズマエッチング装置 |
US10727045B2 (en) * | 2017-09-29 | 2020-07-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for manufacturing a semiconductor device |
US10727075B2 (en) | 2017-12-22 | 2020-07-28 | Applied Materials, Inc. | Uniform EUV photoresist patterning utilizing pulsed plasma process |
KR20200108361A (ko) * | 2018-02-05 | 2020-09-17 | 램 리써치 코포레이션 | 비정질 탄소 층 개방 프로세스 |
Family Cites Families (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4414059A (en) * | 1982-12-09 | 1983-11-08 | International Business Machines Corporation | Far UV patterning of resist materials |
JPS6313334A (ja) | 1986-07-04 | 1988-01-20 | Hitachi Ltd | ドライエツチング方法 |
KR900007687B1 (ko) * | 1986-10-17 | 1990-10-18 | 가부시기가이샤 히다찌세이사꾸쇼 | 플라즈마처리방법 및 장치 |
US4698128A (en) | 1986-11-17 | 1987-10-06 | Motorola, Inc. | Sloped contact etch process |
JP2918892B2 (ja) | 1988-10-14 | 1999-07-12 | 株式会社日立製作所 | プラズマエッチング処理方法 |
JP3006048B2 (ja) * | 1990-07-27 | 2000-02-07 | ソニー株式会社 | ドライエッチング方法 |
JPH04240729A (ja) | 1991-01-24 | 1992-08-28 | Toshiba Corp | パターン形成方法 |
DE4241045C1 (de) * | 1992-12-05 | 1994-05-26 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silicium |
JP3437863B2 (ja) * | 1993-01-18 | 2003-08-18 | 株式会社半導体エネルギー研究所 | Mis型半導体装置の作製方法 |
JPH07226397A (ja) | 1994-02-10 | 1995-08-22 | Tokyo Electron Ltd | エッチング処理方法 |
DE4317623C2 (de) * | 1993-05-27 | 2003-08-21 | Bosch Gmbh Robert | Verfahren und Vorrichtung zum anisotropen Plasmaätzen von Substraten und dessen Verwendung |
JP2674488B2 (ja) * | 1993-12-01 | 1997-11-12 | 日本電気株式会社 | ドライエッチング室のクリーニング方法 |
US5545289A (en) * | 1994-02-03 | 1996-08-13 | Applied Materials, Inc. | Passivating, stripping and corrosion inhibition of semiconductor substrates |
US5468342A (en) * | 1994-04-28 | 1995-11-21 | Cypress Semiconductor Corp. | Method of etching an oxide layer |
US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
JPH0936089A (ja) | 1995-07-19 | 1997-02-07 | Toshiba Corp | アッシング方法及びその装置 |
GB9616225D0 (en) * | 1996-08-01 | 1996-09-11 | Surface Tech Sys Ltd | Method of surface treatment of semiconductor substrates |
EP0822582B1 (en) | 1996-08-01 | 2003-10-01 | Surface Technology Systems Plc | Method of etching substrates |
DE19641288A1 (de) * | 1996-10-07 | 1998-04-09 | Bosch Gmbh Robert | Verfahren zum anisotropen Plasmaätzen verschiedener Substrate |
US5882535A (en) * | 1997-02-04 | 1999-03-16 | Micron Technology, Inc. | Method for forming a hole in a semiconductor device |
DE19706682C2 (de) * | 1997-02-20 | 1999-01-14 | Bosch Gmbh Robert | Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium |
US6010603A (en) * | 1997-07-09 | 2000-01-04 | Applied Materials, Inc. | Patterned copper etch for micron and submicron features, using enhanced physical bombardment |
DE19730644C1 (de) * | 1997-07-17 | 1998-11-19 | Bosch Gmbh Robert | Verfahren zum Erkennen des Übergangs unterschiedlicher Materialien in Halbleiterstrukturen bei einer anisotropen Tiefenätzung |
US6187685B1 (en) * | 1997-08-01 | 2001-02-13 | Surface Technology Systems Limited | Method and apparatus for etching a substrate |
DE19734278C1 (de) * | 1997-08-07 | 1999-02-25 | Bosch Gmbh Robert | Vorrichtung zum anisotropen Ätzen von Substraten |
DE19736370C2 (de) * | 1997-08-21 | 2001-12-06 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silizium |
US5942446A (en) * | 1997-09-12 | 1999-08-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer |
US6074959A (en) * | 1997-09-19 | 2000-06-13 | Applied Materials, Inc. | Method manifesting a wide process window and using hexafluoropropane or other hydrofluoropropanes to selectively etch oxide |
US5849639A (en) * | 1997-11-26 | 1998-12-15 | Lucent Technologies Inc. | Method for removing etching residues and contaminants |
TWI246633B (en) | 1997-12-12 | 2006-01-01 | Applied Materials Inc | Method of pattern etching a low k dielectric layen |
KR100520148B1 (ko) * | 1997-12-31 | 2006-05-12 | 주식회사 하이닉스반도체 | 신규한바이시클로알켄유도체와이를이용한포토레지스트중합체및이중합체를함유한포토레지스트조성물 |
US6228775B1 (en) * | 1998-02-24 | 2001-05-08 | Micron Technology, Inc. | Plasma etching method using low ionization potential gas |
US6387287B1 (en) | 1998-03-27 | 2002-05-14 | Applied Materials, Inc. | Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window |
US6071822A (en) * | 1998-06-08 | 2000-06-06 | Plasma-Therm, Inc. | Etching process for producing substantially undercut free silicon on insulator structures |
US6127258A (en) | 1998-06-25 | 2000-10-03 | Motorola Inc. | Method for forming a semiconductor device |
US6025255A (en) * | 1998-06-25 | 2000-02-15 | Vanguard International Semiconductor Corporation | Two-step etching process for forming self-aligned contacts |
US6211092B1 (en) * | 1998-07-09 | 2001-04-03 | Applied Materials, Inc. | Counterbore dielectric plasma etch process particularly useful for dual damascene |
KR100639841B1 (ko) | 1998-07-23 | 2006-10-27 | 서페이스 테크놀로지 시스템스 피엘씨 | 이방성 에칭 장치 및 방법 |
US6406995B1 (en) * | 1998-09-30 | 2002-06-18 | Intel Corporation | Pattern-sensitive deposition for damascene processing |
JP2000208767A (ja) * | 1998-11-13 | 2000-07-28 | Seiko Epson Corp | 半導体装置の製造方法 |
TW406363B (en) * | 1998-11-27 | 2000-09-21 | United Microelectronics Corp | The method of forming the opening |
US6100200A (en) * | 1998-12-21 | 2000-08-08 | Advanced Technology Materials, Inc. | Sputtering process for the conformal deposition of a metallization or insulating layer |
US6187666B1 (en) * | 1999-06-08 | 2001-02-13 | Advanced Micro Devices, Inc. | CVD plasma process to fill contact hole in damascene process |
US6316169B1 (en) * | 1999-06-25 | 2001-11-13 | Lam Research Corporation | Methods for reducing profile variation in photoresist trimming |
US6235453B1 (en) | 1999-07-07 | 2001-05-22 | Advanced Micro Devices, Inc. | Low-k photoresist removal process |
KR100327346B1 (ko) * | 1999-07-20 | 2002-03-06 | 윤종용 | 선택적 폴리머 증착을 이용한 플라즈마 식각방법 및 이를이용한 콘택홀 형성방법 |
US6593653B2 (en) * | 1999-09-30 | 2003-07-15 | Novellus Systems, Inc. | Low leakage current silicon carbonitride prepared using methane, ammonia and silane for copper diffusion barrier, etchstop and passivation applications |
US6291357B1 (en) * | 1999-10-06 | 2001-09-18 | Applied Materials, Inc. | Method and apparatus for etching a substrate with reduced microloading |
WO2001029879A2 (en) | 1999-10-20 | 2001-04-26 | Mattson Technology, Inc. | Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing |
US6326307B1 (en) * | 1999-11-15 | 2001-12-04 | Appllied Materials, Inc. | Plasma pretreatment of photoresist in an oxide etch process |
US6391788B1 (en) * | 2000-02-25 | 2002-05-21 | Applied Materials, Inc. | Two etchant etch method |
US6451703B1 (en) | 2000-03-10 | 2002-09-17 | Applied Materials, Inc. | Magnetically enhanced plasma etch process using a heavy fluorocarbon etching gas |
US6284666B1 (en) * | 2000-05-31 | 2001-09-04 | International Business Machines Corporation | Method of reducing RIE lag for deep trench silicon etching |
JP2002025979A (ja) * | 2000-07-03 | 2002-01-25 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6500743B1 (en) * | 2000-08-30 | 2002-12-31 | Advanced Micro Devices, Inc. | Method of copper-polysilicon T-gate formation |
US6569774B1 (en) * | 2000-08-31 | 2003-05-27 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
US6403491B1 (en) * | 2000-11-01 | 2002-06-11 | Applied Materials, Inc. | Etch method using a dielectric etch chamber with expanded process window |
DE10059836A1 (de) | 2000-12-01 | 2002-06-13 | Infineon Technologies Ag | Verfahren zur Strukturierung dielektrischer Schichten |
US6743727B2 (en) * | 2001-06-05 | 2004-06-01 | International Business Machines Corporation | Method of etching high aspect ratio openings |
US20030027427A1 (en) * | 2001-08-06 | 2003-02-06 | Applied Materials, Inc. | Integrated system for oxide etching and metal liner deposition |
JP2005508078A (ja) * | 2001-10-31 | 2005-03-24 | 東京エレクトロン株式会社 | 高アスペクト比形態のエッチング方法 |
US20030118948A1 (en) * | 2001-12-21 | 2003-06-26 | Rohit Grover | Method of etching semiconductor material to achieve structure suitable for optics |
US6647994B1 (en) * | 2002-01-02 | 2003-11-18 | Taiwan Semiconductor Manufacturing Company | Method of resist stripping over low-k dielectric material |
US6846516B2 (en) | 2002-04-08 | 2005-01-25 | Applied Materials, Inc. | Multiple precursor cyclical deposition system |
US6979652B2 (en) * | 2002-04-08 | 2005-12-27 | Applied Materials, Inc. | Etching multi-shaped openings in silicon |
US6784096B2 (en) | 2002-09-11 | 2004-08-31 | Applied Materials, Inc. | Methods and apparatus for forming barrier layers in high aspect ratio vias |
CN1723549B (zh) * | 2002-10-11 | 2012-01-18 | 兰姆研究有限公司 | 增强等离子体蚀刻性能的方法 |
US6833325B2 (en) * | 2002-10-11 | 2004-12-21 | Lam Research Corporation | Method for plasma etching performance enhancement |
US7169695B2 (en) * | 2002-10-11 | 2007-01-30 | Lam Research Corporation | Method for forming a dual damascene structure |
US20040097077A1 (en) * | 2002-11-15 | 2004-05-20 | Applied Materials, Inc. | Method and apparatus for etching a deep trench |
US7294580B2 (en) * | 2003-04-09 | 2007-11-13 | Lam Research Corporation | Method for plasma stripping using periodic modulation of gas chemistry and hydrocarbon addition |
US6916746B1 (en) * | 2003-04-09 | 2005-07-12 | Lam Research Corporation | Method for plasma etching using periodic modulation of gas chemistry |
US7056830B2 (en) * | 2003-09-03 | 2006-06-06 | Applied Materials, Inc. | Method for plasma etching a dielectric layer |
-
2006
- 2006-02-17 US US11/357,548 patent/US7910489B2/en active Active
-
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- 2007-01-30 KR KR1020087022696A patent/KR101442269B1/ko active IP Right Grant
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- 2007-01-30 WO PCT/US2007/002511 patent/WO2007094957A1/en active Application Filing
- 2007-01-30 CN CNA200780013713XA patent/CN101421830A/zh active Pending
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102856191A (zh) * | 2011-06-30 | 2013-01-02 | 株式会社日立高新技术 | 等离子处理方法 |
TWI469215B (zh) * | 2011-06-30 | 2015-01-11 | Hitachi High Tech Corp | Plasma processing method |
CN105565252A (zh) * | 2014-10-10 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | 一种mems器件及其制备方法、电子装置 |
CN105565252B (zh) * | 2014-10-10 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | 一种mems器件及其制备方法、电子装置 |
CN107068555A (zh) * | 2015-12-21 | 2017-08-18 | 台湾积体电路制造股份有限公司 | 形成沟槽的方法 |
US10854507B2 (en) | 2015-12-21 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming trenches |
CN111261593A (zh) * | 2018-11-30 | 2020-06-09 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
Also Published As
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KR101442269B1 (ko) | 2014-09-19 |
US7910489B2 (en) | 2011-03-22 |
WO2007094957A1 (en) | 2007-08-23 |
TWI424491B (zh) | 2014-01-21 |
US20070193973A1 (en) | 2007-08-23 |
CN105390390A (zh) | 2016-03-09 |
TW200735210A (en) | 2007-09-16 |
KR20080109762A (ko) | 2008-12-17 |
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