CN101447510B - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN101447510B CN101447510B CN2007101716659A CN200710171665A CN101447510B CN 101447510 B CN101447510 B CN 101447510B CN 2007101716659 A CN2007101716659 A CN 2007101716659A CN 200710171665 A CN200710171665 A CN 200710171665A CN 101447510 B CN101447510 B CN 101447510B
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Abstract
The invention relates to a semiconductor device which comprises a semiconductor basement, a grid, a lateral wall and a passivation layer; wherein, a source region, a drain region and a conductive channel region are arranged in the semiconductor basement; the grid is arranged on the semiconductor base; the lateral wall surrounds the gate; and the passivation layer is used for covering the semiconductor base, the grid and the lateral wall. The determined stress is provided in the conductive channel region of the device comprising the passivation layer. The passivation layer comprises a first passivation layer and a second passivation layer. The first passivation layer is connected with the second passivation layer. The first passivation layer has a first stress. The second passivation layer has a second stress. Leakage current of the device can be lowered without changing the stress in the conductive channel region of the device. A forming method for the semiconductor device is also provided by the invention. With the method, the semiconductor device which can lower the leakage current of the device without changing the stress in the conductive channel region of the device is formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor device and forming method thereof.
Background technology
Current, industry is known, has following piezoresistance effect: produce stress in semiconductor film, can cause the interior lattice spacing of rete to change, cause the interior band structure of substrate to change then, and then carrier mobility is changed.Carrier mobility becomes greatly or diminishes, and different, described stress types comprises tension stress and compression according to the difference of the moving direction of the face direction of substrate, charge carrier and stress types.For example, be in the silicon substrate of interarea with (100) face, when the moving direction of charge carrier is (011) direction, be under the situation of electronics at charge carrier, if produce tension stress on the direction that the electronics of channel region moves, then the mobility of charge carrier rate improves; At charge carrier is under the situation in hole, if produce compression stress on the direction that moves in the hole of channel region, then the mobility of charge carrier rate improves; The ratio that the mobility of charge carrier rate improves is relevant with the size of stress.Thus, industry generally adopts the technology to the semiconductor film stress application, to improve carrier mobility.
But, because the existence of leakage current also can cause the waste of power when device is not worked, can cause the shortening of device operating time, therefore, under the prerequisite that improves carrier mobility, the leakage current that reduces device becomes the subject matter that industry is endeavoured to solve.
On January 17th, 2007, disclosed publication number provided a kind of semiconductor device and forming method thereof in the Chinese patent application of " CN 1897303A ", as shown in Figure 1, described semiconductor device comprises substrate 18, gate electrode 21 is formed in the substrate 18, grid spacer 30 is formed at (comprising the first sept 30a and the first sept 30b) both sides of gate electrode 21, source/drain region 36 is formed in the substrate 18, and conductive region 38 is formed on source/drain region 36, conductive region 38 comprises the first conductive region 38a and the second conductive region 38b, wherein the second conductive region 38b is formed between the first conductive region 38a and the grid spacer 30, the top surface of the first conductive region 38a is the top surface that is lower than the second conductive region 38b, and above-mentioned two top surfaces differ the height of a step, promptly have interface 38c; Wherein, omit the binding site 44 of describing gate dielectric 20, light doping section 22, shallow channel isolation area 24, barrier layer 40, channel region 43 and interface 38c and source/drain region.That is, this method to promote the mode of the tension stress in the channel region, realizes reducing the purpose of device creepage by forming depression at conductive region.But the semiconductor device of formation has more multi-stylus corner structure, easily causes undesirable electric leakage/electrostatic effect in successive process.
Summary of the invention
The invention provides a kind of semiconductor device, can under the condition that does not change device conducting channel district internal stress, reduce the leakage current of device; The invention provides a kind of semiconductor device formation method, can form and not change device conducting channel district internal stress, and reduced the semiconductor device of device creepage.
A kind of semiconductor device provided by the invention comprises: the semiconductor-based end, have source region, drain region and the conducting channel district between described source region and drain region at described the semiconductor-based end; Be positioned at the suprabasil grid of described semiconductor, around the side wall of described grid; And, cover the passivation layer of the described semiconductor-based end, grid and side wall, comprise in the conducting channel district of device of described passivation layer and have definite stress; Described passivation layer comprises first passivation layer and second passivation layer, and described first passivation layer and second passivation layer join, and described first passivation layer has first stress, and described second passivation layer has second stress.
Alternatively, described first passivation layer and described second passivation layer have same stress types; Alternatively, described stress types comprises tension stress or compression; Alternatively, described first passivation layer has first stress types; Described second passivation layer has second stress types; Alternatively, when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
A kind of semiconductor device provided by the invention comprises: the semiconductor-based end, have source region, drain region and the conducting channel district between described source region and drain region at described the semiconductor-based end; Be positioned at the suprabasil grid of described semiconductor, around the side wall of described grid, and, cover the passivation layer in described source region and drain region, comprise in the conducting channel district of device of described passivation layer and have definite stress; Described passivation layer comprises first passivation layer and second passivation layer, and described first passivation layer and second passivation layer cover described source region and drain region respectively, and described first passivation layer has first stress, and described second passivation layer has second stress.
Alternatively, described first passivation layer and described second passivation layer have same stress types; Alternatively, described stress types comprises tension stress or compression; Alternatively, described first passivation layer has first stress types; Described second passivation layer has second stress types; Alternatively, when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
A kind of semiconductor device formation method provided by the invention comprises:
The semiconductor-based end, be provided;
On the described semiconductor-based end, form grid and around the side wall of described grid;
In the described semiconductor-based end, form source region and drain region;
Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has first stress;
Graphical described first passivation layer;
Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has second stress;
Described second passivation layer of described first passivation layer after the removal cover graphicsization joins described first passivation layer and second passivation layer.
Alternatively, described first passivation layer and described second passivation layer have same stress types; Alternatively, described stress types comprises tension stress or compression; Alternatively, described first passivation layer has first stress types; Described second passivation layer has second stress types; Alternatively, when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
A kind of semiconductor device formation method provided by the invention comprises:
The semiconductor-based end, be provided;
On the described semiconductor-based end, form grid and around the side wall of described grid;
In the described semiconductor-based end, form source region and drain region;
Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has first stress;
Graphical described first passivation layer makes described first passivation layer after graphical cover described source region or drain region;
Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has second stress;
Remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region.
Alternatively, described first passivation layer and described second passivation layer have same stress types; Alternatively, described stress types comprises tension stress or compression; Alternatively, described first passivation layer has first stress types; Described second passivation layer has second stress types; Alternatively, when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
Compared with prior art, technique scheme has the following advantages:
Semiconductor device provided by the invention, by forming first passivation layer and second passivation layer respectively at described semiconductor-based basal surface, described first passivation layer and second passivation layer join, and described first passivation layer has first stress, and described second passivation layer has second stress; Comprise and still have the stress of determining same as the prior art in the conducting channel district of device with described passivation layer, and described definite stress and described first stress and second stress and be directly proportional, promptly, can under the condition that does not change device conducting channel district internal stress, change the stress of neighboring area, described conducting channel district; To control the tunnelling probability of described conducting channel district neighboring area charge carrier respectively, promptly, further reduce the leakage current of device by changing the stress of conducting channel periphery;
Semiconductor device provided by the invention, by forming first passivation layer and second passivation layer respectively at described semiconductor-based basal surface, described first passivation layer and second passivation layer cover source region and drain region respectively, and described first stress types has first stress, and described second stress types has second stress; Comprise and still have the stress of determining same as the prior art in the conducting channel district of device with described passivation layer, and described definite stress and described first stress and second stress and be directly proportional, promptly, can under the condition that does not change device conducting channel district internal stress, change the stress of neighboring area, described conducting channel district; To control the tunnelling probability of described conducting channel district neighboring area charge carrier respectively, promptly, further reduce the leakage current of device by changing the stress of conducting channel periphery; And can prevent to have the continuous variation that reaches by described continuous each the passivation layer internal stress that causes of passivation layer of different stress;
Semiconductor device formation method provided by the invention, by after forming patterned and having first passivation layer of first stress, form second passivation layer that covers described first passivation layer and the described semiconductor-based end of part, grid and/or side wall and have second stress; Then, remove described second passivation layer that covers described first passivation layer; Do not change the semiconductor device of conducting channel zone internal stress with the stress of the conducting channel neighboring area that forms the follow-up formation of may command, and can further reduce the leakage current of described semiconductor device;
Semiconductor device formation method provided by the invention, by after form covering source region or drain region and having first passivation layer of first stress, form second passivation layer that covers described first passivation layer and the described semiconductor-based end of part, grid and/or side wall and have second stress; Then, remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region; Do not change the semiconductor device of conducting channel zone internal stress with the stress of the conducting channel neighboring area that forms the follow-up formation of may command, and can further reduce the leakage current of described semiconductor device; And the passivation layer that can prevent to have different stress links to each other and by the variation of described each the passivation layer internal stress that causes of linking to each other.
Description of drawings
Fig. 1 is for promoting the structural representation that the channel region tension stress also can reduce the semiconductor device of leakage current in the explanation prior art;
Fig. 2 is the structural representation of the semiconductor device of explanation first embodiment of the invention;
Fig. 3 is the structural representation of the semiconductor device of explanation second embodiment of the invention;
Fig. 4 is the structural representation of the semiconductor device of explanation third embodiment of the invention;
Fig. 5 is the structural representation of the semiconductor device of explanation fourth embodiment of the invention.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 2, as first embodiment, semiconductor device provided by the invention comprises: the semiconductor-based end 100, have source region 120a, drain region 120b and the conducting channel district 120c between described source region 120a and drain region 120b at described the semiconductor-based end 100; Be positioned at grid 140 at the described semiconductor-based end 100, around the side wall 160 of described grid 140, and, cover the passivation layer 180 of the described semiconductor-based end 100, grid 140 and side wall 160, comprise in the conducting channel district 120c of device of described passivation layer 180 and have definite stress; Especially, described passivation layer 180 comprises first passivation layer 180a with first stress types and the second passivation layer 180b with second stress types, the described first passivation layer 180a and the second passivation layer 180b join, the described first passivation layer 180a has first stress, and the described second passivation layer 180b has second stress.
In the presents, term " stress " means the measured value of stress in thin film in the actual production, and described measured value has the technology permissible variation scope that satisfies requirement on devices, and described stress is the power on the average unit are, and unit is Pa; Term " stress types " be according to stress with the stress in thin film sorting result, stress is that positive interval scale stress types is tension stress (tensile stress); Stress is compression (compressive stress) for negative interval scale stress types.Described " having definite stress " means and forms the stress that satisfies requirement on devices that has in the device conducting channel district behind the passivation layer; The difference that term " identical " or " equaling " mean between comparison object can be ignored under the process conditions that are suitable for.
The described semiconductor-based end 100, is for to form shallow trench isolation from the Semiconductor substrate (substrate) to define the source region; Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).The described semiconductor-based end, can comprise oxide layer, and described oxide layer materials comprises silicon dioxide (SiO
2), the silicon dioxide or the hafnium oxide (HfO of doping hafnium (Hf)
2).
Stack combination or metal that described grid 140 comprises doped polycrystalline silicon, formed by polysilicon and metal silicide.
Described side wall 160 comprises the stack combination that stack combination that silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride forms or silicon dioxide, silicon oxynitride and/or silicon nitride, silicon dioxide form, perhaps a kind of in the stack combination that joins of the stack combination of silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide formation and silicon dioxide and silicon oxynitride and/or silicon nitride spacer.
Described source region 120a and drain region 120b are by forming after the operation of mixing is carried out in definite zone at described the semiconductor-based end 100, and described doping operation utilizes ion implantation technology to carry out.The doping particle that relates to comprises boron (B), fluoridizes inferior boron (BF
2), arsenic (As), phosphorus (P) but or a kind of in other dopant material.
Described passivation layer 180 comprises a kind of and combination in silicon nitride, silicon oxynitride, carborundum or the silicon oxide carbide.Described passivation layer 180 both can be used as the separator of processing procedure at interval, and described separator is protected not stain at goods of forming behind the experience aforesaid operations of the semiconductor-based end; Also can be used as the etching stop layer of subsequent etching operation.
Described first stress types and second stress types comprise tension stress or compression.After forming the tension stress passivation layer, has tension stress among the conducting channel 120c that forms after can between follow-up drain-source, applying appropriate voltage; After forming the compression passivation layer, has compression among the conducting channel 120c that forms after can between follow-up drain-source, applying appropriate voltage.In the present embodiment, described first passivation layer is identical with the stress types of second passivation layer.
It should be noted that the junction point that the described first passivation layer 180a and the second passivation layer 180b join can be positioned at any position on the described semiconductor-based end, grid and side wall surface, as described in being positioned at gate surface central authorities or be positioned at as described in the joint of grid and side wall.The particular location at described junction point is determined according to product requirement and process conditions.
Described first stress and second stress are determined according to process conditions and product requirement.As example, when the junction point that the described first passivation layer 180a and the second passivation layer 180b join is positioned at described gate surface central, be example, when using traditional handicraft with the nmos device, when passivation layer had the tension stress of 1.0GPa, tension stress was 1.05e in the conducting channel district
8Pa gets Vg=Vd=1.2V, and Vs=Vb=0V, leakage current are 9.0e
2Pa/ μ m.
And in the present invention, determining that the described first passivation layer 180a can have the tension stress of 2.1GPa for keeping stress types and stress in the device conducting channel district, the described second passivation layer 180b can have the tension stress of 0.5GPa; At this moment, tension stress is 1.13e in the conducting channel district
8Pa gets Vg=Vd=1.2V, and Vs=Vb=0V, leakage current only are 3.75e
2Pa/ μ m.That is, still have in the conducting channel district with prior art in the identical stress of determining, and second stress that has of first stress that has of described definite stress and the described first passivation layer 180a and the described second passivation layer 180b be directly proportional; In other words, the described first passivation layer 180a can have the tension stress of 4.2GPa, and the described second passivation layer 180b can have the tension stress of 1GPa; At this moment, tension stress is 2.26e in the conducting channel district
8Pa.
Above-mentioned data are to utilize Sentaurus simulation tool (in October, 2006 version) that U.S. Synopsis company produces and obtain with reference to Typical 65nm CMOS technology technological process.
The present inventor thinks that the introducing of stress can change the energy gap of semiconductor substrate materials after analyzing, and the change of described energy gap will influence the tunnelling probability of charge carrier, that is, energy gap increases, and tunnelling probability is tending towards reducing, energy gap reduces, and tunnelling probability is tending towards increasing; And then the change of described energy gap will influence the size of leakage current.In the actual production, because leakage current is tunnelling current, so only under the bigger situation of voltage, just have the numerical value that to survey, therefore, be example with NMOS, only just can produce bigger tunnelling current in the drain region that links to each other with supply voltage, and in the source region, descended at least size of a threshold voltage of voltage, corresponding tunnelling current can be ignored, so only note usually the drain region leakage current reduce get final product.
Method provided by the invention, by to 120c neighboring area, conducting channel district (in the present embodiment, be source region and drain region) carry out Stress Control respectively, can under the condition that does not change device conducting channel district internal stress, change the stress of neighboring area, described conducting channel district; To control the tunnelling probability of described conducting channel district neighboring area charge carrier respectively, promptly, further reduce the leakage current of device by changing the stress of conducting channel periphery.
As shown in Figure 3, as second embodiment, in the semiconductor device provided by the invention, the described first passivation layer 180c can have different stress types with the second passivation layer 180d.When described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
As shown in Figure 4, as the 3rd embodiment, semiconductor device provided by the invention comprises: the semiconductor-based end 100, have source region 120a, drain region 120b and the conducting channel district 120c between described source region 120a and drain region 120b at described the semiconductor-based end 100; Be positioned at grid 140 at the described semiconductor-based end 100, around the side wall 160 of described grid 140, and, cover the passivation layer 200 of described source region 120a and drain region 120b, comprise in the conducting channel district of device of described passivation layer 200 and have definite stress; Especially, described passivation layer 200 comprises the first passivation layer 200a and the second passivation layer 200b, the described first passivation layer 200a and the second passivation layer 200b cover described source region and drain region respectively, and the described first passivation layer 200a has first stress, and the described second passivation layer 200b has second stress.By making the described first passivation layer 200a and the second passivation layer 200b cover source region and drain region respectively, and do not cover described grid and side wall surface, can prevent to cover the passivation layer with different stress and link to each other, described linking to each other will cause the variation of corresponding passivation layer internal stress.
As shown in Figure 5, as the 4th embodiment, in the semiconductor device provided by the invention, the described first passivation layer 180c and the second passivation layer 180d can have same stress types.Described stress types can be tension stress or compression.By making the described first passivation layer 200c and the second passivation layer 200d cover source region and drain region respectively, and do not cover described grid and side wall surface, can prevent to cover the passivation layer with different stress and link to each other, described linking to each other will cause the variation of corresponding passivation layer internal stress.
The present invention also provides a kind of semiconductor device formation method, and concrete steps comprise: the semiconductor-based end is provided; On the described semiconductor-based end, form grid and around the side wall of described grid; In the described semiconductor-based end, form source region and drain region; Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has first stress types and first stress; Graphical described first passivation layer; Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has second stress types and second stress; Described second passivation layer of described first passivation layer after the removal cover graphicsization joins described first passivation layer and second passivation layer.
The described semiconductor-based end, is for to form shallow trench isolation from the Semiconductor substrate (substrate) to define the source region; Described Semiconductor substrate comprises but is not limited to comprise the silicon materials of semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).The described semiconductor-based end, can comprise oxide layer, and described oxide layer materials comprises silicon dioxide (SiO
2), the silicon dioxide or the hafnium oxide (HfO of doping hafnium (Hf)
2).
Described source region and drain region are by forming after carrying out the operation of mixing definite zone at the described semiconductor-based end, and described doping operation utilizes ion implantation technology to carry out.The doping particle that relates to comprises boron (B), fluoridizes inferior boron (BF
2), arsenic (As), phosphorus (P) but or a kind of in other dopant material.
Stack combination or metal that described grid comprises doped polycrystalline silicon, formed by polysilicon and metal silicide.
Described side wall comprises the stack combination that stack combination that silicon dioxide or silicon dioxide and silicon oxynitride and/or silicon nitride forms or silicon dioxide, silicon oxynitride and/or silicon nitride, silicon dioxide form, perhaps a kind of in the stack combination that joins of the stack combination of silicon dioxide, silicon oxynitride, silicon nitride, silicon oxynitride and silicon dioxide formation and silicon dioxide and silicon oxynitride and/or silicon nitride spacer.
Described passivation layer comprises a kind of and combination in silicon nitride, silicon oxynitride, carborundum or the silicon oxide carbide.Described passivation layer both can be used as the separator of processing procedure at interval, and described separator is protected not stain at goods of forming behind the experience aforesaid operations of the semiconductor-based end; Also can be used as the etching stop layer of subsequent etching operation.
Described first stress types comprises tension stress (tensile stress) or compression (compressive stress).After forming the tension stress passivation layer, has tension stress in the conducting channel that forms after can between follow-up drain-source, applying appropriate voltage; After forming the compression passivation layer, has compression in the conducting channel that forms after can between follow-up drain-source, applying appropriate voltage.
Described second stress types comprises compression or tension stress.When described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
Described first stress and second stress are determined according to process conditions and product requirement.The stress that described passivation layer has is the geometrical mean of the algebraical sum of first stress that has respectively of described first passivation layer and second passivation layer and second stress.
The present invention also provides a kind of semiconductor device formation method, and concrete steps comprise: the semiconductor-based end is provided; On the described semiconductor-based end, form grid and around the side wall of described grid; In the described semiconductor-based end, form source region and drain region; Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has the definite stress types and first stress; Graphical described first passivation layer; Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has the same stress types and second stress; Described second passivation layer of described first passivation layer after the removal cover graphicsization.
Described definite stress types comprises tension stress or compression; Described stress types is determined according to product requirement.
Use semiconductor device formation method provided by the invention, by after forming patterned and having first passivation layer of first stress, form second passivation layer that covers described first passivation layer and the described semiconductor-based end of part, grid and/or side wall and have second stress; Then, remove described second passivation layer that covers described first passivation layer; Do not change the semiconductor device of conducting channel zone internal stress with the stress of the conducting channel neighboring area that forms the follow-up formation of may command, and can further reduce the leakage current of described semiconductor device.
The present invention also provides a kind of semiconductor device formation method, and concrete steps comprise: the semiconductor-based end is provided; On the described semiconductor-based end, form grid and around the side wall of described grid; In the described semiconductor-based end, form source region and drain region; Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has first stress types and first stress; Graphical described first passivation layer makes described first passivation layer after graphical cover described source region or drain region; Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has second stress types and second stress; Remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region.
The present invention also provides a kind of semiconductor device formation method, and concrete steps comprise: the semiconductor-based end is provided; On the described semiconductor-based end, form grid and around the side wall of described grid; In the described semiconductor-based end, form source region and drain region; Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has the definite stress types and first stress; Graphical described first passivation layer makes described first passivation layer after graphical cover described source region or drain region; Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has the same stress types and second stress; Remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region.
Described definite stress types comprises tension stress or compression; Described stress types is determined according to product requirement.
Use semiconductor device formation method provided by the invention, by after form covering source region or drain region and having first passivation layer of first stress, form second passivation layer that covers described first passivation layer and the described semiconductor-based end of part, grid and/or side wall and have second stress; Then, remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region; Do not change the semiconductor device of conducting channel zone internal stress with the stress of the conducting channel neighboring area that forms the follow-up formation of may command, and can further reduce the leakage current of described semiconductor device; And the passivation layer that can prevent to have different stress links to each other and by the variation of described each the passivation layer internal stress that causes of linking to each other.
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (10)
1. a semiconductor device comprises: the semiconductor-based end, have source region, drain region and the conducting channel district between described source region and drain region at described the semiconductor-based end; Be positioned at the suprabasil grid of described semiconductor, around the side wall of described grid, and, cover the passivation layer in described source region and drain region, comprise in the conducting channel district of device of described passivation layer and have definite stress; It is characterized in that: described passivation layer comprises first passivation layer and second passivation layer, and described first passivation layer and second passivation layer cover described source region and drain region respectively, and described first passivation layer has first stress, and described second passivation layer has second stress; Described definite stress and described first stress and second stress and be directly proportional.
2. semiconductor device according to claim 1 is characterized in that: described first passivation layer and described second passivation layer have same stress types.
3. semiconductor device according to claim 2 is characterized in that: described stress types comprises tension stress or compression.
4. semiconductor device according to claim 1 is characterized in that: described first passivation layer has first stress types; Described second passivation layer has second stress types.
5. semiconductor device according to claim 4 is characterized in that: when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
6. a semiconductor device formation method is characterized in that, comprising:
The semiconductor-based end, be provided;
On the described semiconductor-based end, form grid and around the side wall of described grid;
In the described semiconductor-based end, form source region and drain region;
Form first passivation layer that covers the described semiconductor-based end, grid and side wall, described first passivation layer has first stress;
Graphical described first passivation layer makes described first passivation layer after graphical cover described source region or drain region;
Described first passivation layer after the formation cover graphicsization and second passivation layer of the described semiconductor-based end of part, grid and/or side wall, described second passivation layer has second stress;
Remove described second passivation layer of part, when making described first passivation layer cover described source region, described second passivation layer covers described drain region; When described first passivation layer covered described drain region, described second passivation layer covered described source region; Comprise in the conducting channel district of device of described first, second passivation layer and have definite stress, and described definite stress and described first stress and second stress and be directly proportional.
7. semiconductor device according to claim 6 is characterized in that: described first passivation layer and described second passivation layer have same stress types.
8. semiconductor device according to claim 7 is characterized in that: described stress types comprises tension stress or compression.
9. semiconductor device according to claim 6 is characterized in that: described first passivation layer has first stress types; Described second passivation layer has second stress types.
10. semiconductor device according to claim 9 is characterized in that: when described first stress types was tension stress, described second stress types was a compression; When described first stress types was compression, described second stress types was a tension stress.
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| US7279758B1 (en) * | 2006-05-24 | 2007-10-09 | International Business Machines Corporation | N-channel MOSFETs comprising dual stressors, and methods for forming the same |
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| US7279758B1 (en) * | 2006-05-24 | 2007-10-09 | International Business Machines Corporation | N-channel MOSFETs comprising dual stressors, and methods for forming the same |
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| JP特开平9-306929A 1997.11.28 |
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