CN101452743B - Writing-in system and method for phase change memory - Google Patents
Writing-in system and method for phase change memory Download PDFInfo
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- CN101452743B CN101452743B CN200710197139XA CN200710197139A CN101452743B CN 101452743 B CN101452743 B CN 101452743B CN 200710197139X A CN200710197139X A CN 200710197139XA CN 200710197139 A CN200710197139 A CN 200710197139A CN 101452743 B CN101452743 B CN 101452743B
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Abstract
The embodiment of the invention provides a writing system for a phase change memory, which comprises a first writing circuit, a verification circuit, a first phase change memory unit and a second phase change memory unit, wherein the first writing circuit executes a writing program, receives first data and writes the first data in the first phase change memory unit; the verification circuit executes an verification program and comprises a processing unit and a second writing circuit; the processing unit reads and compares data stored in the second phase change memory unit and second data; and the second writing circuit writes the second data in the second phase change memory unit again when the data stored in the second phase change memory unit does not accord with the second data.
Description
Technical field
The present invention relates to a kind of writing system and method for phase transition storage.
Background technology
Development along with the portable use product, make the demand of nonvolatile memory that the trend that day by day increases be arranged, the phase transition storage technology is owing to have competitive characteristics such as speed, power, capacity, fiduciary level, process integration degree and cost, has been regarded as the non-volatile memory technologies of potentialization of next epoch.
The operation of phase transition storage mainly is to be applied on the phase transition storage by two kinds of different big or small current impulses, make phase transition storage because the effect of Ohmic heating, cause amorphous state (amorphous state) that regional area causes phase-change material because of different temperature changes with crystalline state (crystalline state) but anti-phase change, and reach the purpose of storage data by the different resistance values that this two phase transformations structure is presented.The current impulse synoptic diagram of Fig. 1 for generally phase transition storage being write and reads.When phase transition storage carries out the RESET operation, mainly be to apply the short and higher reset current I of pulse height of a pulse width
RESET, make the temperature of phase transition storage regional area can be higher than the melting temperature (T of phase-change material by applying of this pulse
m) and melt.When the zone of this thawing during in instantaneous temperature reduction, carry out crystallization again owing to have insufficient time to, therefore in the process of solidifying, can form amorphous state, this moment, phase-change material had high value.On the other hand, when phase transition storage carries out the SET operation, then be to utilize a pulse width broad and the lower setting electric current I of pulse height
SET, make the temperature of phase transition storage regional area between the Tc (T of phase-change material by applying of this pulse
c) and melting temperature (T
m) between, so then can be again by crystallization through the noncrystallineization zone after the SET operation.As mentioned above, the RESET of phase transition storage operation and SET operation promptly as writing in the storer (write) with wipe (erase) operation, at last by phase transition storage being operated in the effect that resistance difference between crystalline state and the amorphous state reaches storage.When the data in the reading phase change memories, then utilize a size of current less than I
SETRead electric current I
ReadJudge its resistance value, to learn the data of its storage.
Summary of the invention
One embodiment of the invention are a kind of writing system of phase transition storage, comprise one first write circuit, a proof scheme, one first phase-change memory cell and one second phase-change memory cell.This first write circuit is carried out a write-in program, receives one first data and writes to this first phase-change memory cell.This proof scheme is carried out a proving program, comprises a processing unit and one second write circuit.This processing unit reads and the data and one second data of relatively this second phase-change memory cell storage.This second write circuit when the data and one second data of the storage of this second phase-change memory cell and when not meeting, writes this second phase-change memory cell once more with these second data.
Another embodiment of the present invention is a kind of wiring method of phase transition storage, utilizes a proof scheme and one first write circuit to finish, and comprising: in a period 1 one first phase-change memory cell is carried out a write-in program; In this period 1, one second phase-change memory cell is carried out a proving program; If this second phase-change memory cell authentication failed, then this proof scheme is exported an electric current and is adjusted signal to this first write circuit, adjusts first write current of this first write circuit output.
Description of drawings
The current impulse synoptic diagram of Fig. 1 for generally phase transition storage being write and reads.
Fig. 2 is the electric current and the resistance characteristic curve map of a phase transition storage.
Fig. 3 is the synoptic diagram according to the control circuit of a phase transition storage of the present invention.
Fig. 4 is writing and the verification operation process flow diagram according to phase transition storage of the present invention.
Fig. 5 is writing and verification operation and the sequential chart with an embodiment of verification operation of writing according to phase transition storage of the present invention of a known phase transition storage.
Fig. 6 is the synoptic diagram according to an embodiment of the writing system of a phase transition storage of the present invention.
Fig. 7 is the circuit diagram of an embodiment of a write circuit and auxiliary write circuit.
Fig. 8 is the synoptic diagram according to another embodiment of the writing system of a phase transition storage of the present invention.
The reference numeral explanation
31～read and proof scheme
32～write circuit
33～phase change memory array
34～read circuit
35～proof scheme
36,37～bit line
61～authentication unit
62～the first write circuits
63～phase transition storage
64～processor
65～read circuit
66～the second write circuits
81～authentication unit
82～the first write circuits
83～phase transition storage
84～detect and comparator circuit
85～matrix current adjustment circuit
86～read circuit
87～the second write circuits
Embodiment
Fig. 2 is the electric current and the resistance characteristic curve map of a phase transition storage.Curve 21 is the family curve of a normal phase transition storage, when phase transition storage receives the setting electric current I
SET, can make the resistance value of phase transition storage roughly become R
SET, when phase transition storage receives reset current I
RESET, can make the resistance value of phase transition storage roughly become R
RESETWhen the number of times that is read when phase transition storage increases, may cause the pattern drift of phase transition storage, cause situation to take place as curve 22.With curve 22, when phase transition storage receives the setting electric current I
SET, the resistance value of phase transition storage roughly is still R
SET, receive reset current I but work as phase transition storage
RESET, can make that the resistance value of phase transition storage just is not the R of expection
RESET, just phase transition storage can't normally be write.In this case, must utilize bigger setting electric current I
SETWith reset current I
RESETCould make phase transition storage by normal running.
In another embodiment, may be because the relation of phase transition storage technology causes and works as with general setting electric current I
SETDuring the input phase transition storage, its resistance value can't maintain R
SET, in this case, must utilize less setting electric current I
SETWith reset current I
RESETCould make phase transition storage by normal running.
Fig. 3 is the synoptic diagram according to the control circuit of a phase transition storage of the present invention.Control circuit in Fig. 3, the present invention adopts a kind of circuit structure of reading and writing separation, can effectively promote the usefulness of phase transition storage.Read and comprise with proof scheme 31 and to read a circuit 34 and a proof scheme 35, in order to checking phase change memory array 33.When the bit line 37 of 32 pairs of phase change memory arrays 33 of write circuit carried out write operation, the phase-change memory cell that reads on the bit line 36 with 31 pairs of phase change memory arrays 33 of proof scheme carried out verification operation.Read the data that circuit 34 reads the storage that is coupled to the phase-change memory cell on the bit line 36 earlier, and be sent in the proof scheme 35.Proof scheme 35 will read the data that circuit 34 reads and compare with a reference data, if both are identical, represent that then phase change memory array 33 can normally be read.If both differences are then exported one and controlled signal to write circuit 32, adjust the size of the write current of write circuit 32 outputs.
Generally speaking, for the writing speed of phase transition storage is accelerated, can strengthen write current, therefore employed transistorized breadth length ratio (W/L ratio) must be bigger, just can bear bigger write current.For instance, when write circuit 32 wanted phase-change memory cell on the pairs of bit line 36 to carry out write operation, control signal S1 can turn-on transistor T1, makes write current be input to phase change memory array 33 by transistor T 1.In like manner, transistor T 2 also is same as transistor T 1 with the running of Tn.When reading circuit 34 and want phase-change memory cell on the pairs of bit line 36 to carry out read operation, control signal X1 can turn-on transistor Y1, makes that reading electric current is input to phase change memory array 33 by transistor Y1.In like manner, the running of transistor Y2 and Yn also is same as transistor Y1.
Generally speaking, phase transition storage usually can be with the less data that electric current comes reading phase change memories to be stored that read, also because the less relation of electric current is difficult for driving the bigger transistor of breadth length ratio when reading.Thus, though having speeded up of writing, the speed that reads is slack-off, and is still limited for the improvement of overall efficiency.Therefore, in the present embodiment, the switchgear that write circuit 32 is coupled and read the switchgear that circuit 34 couples and realize with different transistors.In order to accelerate writing speed, so the switchgear that coupled of write circuit 32, as transistor T 1, selection can be born the switchgear of big electric current, that is transistor T 1 has bigger breadth length ratio.In order to accelerate reading speed, read the switchgear that circuit 34 couples, as transistor X1, select to bear the switchgear of less electric current, that is transistor T 1 has less breadth length ratio.
Fig. 4 is writing and the verification operation process flow diagram according to phase transition storage of the present invention.In step S41, earlier (N-1) individual phase-change memory cell is carried out a write operation, then, jump to step S42 and step S43.In step S42, continue N phase-change memory cell carried out a write operation.In the same time, in step S43, (N-1) individual phase-change memory cell is carried out checking (verify) operation.In step S44, read electric current by one earlier and read the data that are stored in (N-1) individual phase-change memory cell, then compare with a reference data again.This reference data is original predetermined data that will write in (N-1) individual phase-change memory cell.In step S45, whether the data of utilizing a comparator circuit relatively to be stored in (N-1) individual phase-change memory cell are coincident with reference data, if then jump to step S48.If not, then jump to step S46.In step S46, write current can be adjusted according to the comparative result of step S45, and in step S48, promptly utilizes adjusted write current to come (N+1) individual phase-change memory cell is carried out write operation.In the present embodiment, step S42 finishes in the same cycle to S46, and when at execution in step S48, simultaneously N phase-change memory cell is carried out a verification operation.
In the present embodiment, write current jumps to step S47 (N-1) individual phase-change memory cell is carried out a write operation after step S46 is adjusted, in order to this reference data is write in (N-1) individual phase-change memory cell.In the present embodiment, the adjustment meeting of write current is according to the comparative result of step S45.In another embodiment, step S47 utilizes different write circuits to finish respectively with the write operation of step S48.And (N-1) individual phase-change memory cell is being carried out a write operation, can carry out a verification operation to N phase-change memory cell simultaneously.
Fig. 5 is writing and verification operation and the sequential chart with an embodiment of verification operation of writing according to phase transition storage of the present invention of a known phase transition storage.Sequential 51 is the sequential chart with verification operation of writing of known phase transition storage.Known writing with verification operation is to finish the back in a write operation to carry out a verification operation at once, if checking is correct, then continues writing of next phase-change memory cell, if authentication failed is then carried out write operation to phase-change memory cell again.Sequential 52 is the sequential chart with an embodiment of verification operation of writing according to phase transition storage of the present invention.In this embodiment, write operation utilizes different processing units to finish respectively with verification operation, therefore can carry out simultaneously, significantly reduces the required write time of phase transition storage.In this embodiment, processing unit can be realized by software or hardware.
Fig. 6 is the synoptic diagram according to an embodiment of the writing system of a phase transition storage of the present invention.First write circuit 62 receives a reference data, and with this reference data recording phase change memory 63.Authentication unit 61 comprises that a processor 64, reads circuit 65 and one second write circuit 66.Read circuit 65 output one and read current to phase transition storage 63, in order to read and to transmit the data that are stored in this phase transition storage 63 to processor 64.Processor 64 relatively this reference data reads the data that circuit 65 sends with oneself, if both are consistent, then transmits confirmation signal to the first write circuit 62, in order to keep the size of write circuit write current.If processor detects this reference data and do not meet from reading the data that circuit 65 sends, then export one and control signal to this first write circuit 62 and this second write circuit 66, in order to adjust the size of write current.
After second write circuit 66 receives this control signal, can be with adjusted write current with reference data once more in the recording phase change memory 63.In the present embodiment, when authentication unit 61 when (N-1) individual phase-change memory cell is carried out a verification operation, 62 pairs of N phase-change memory cells of this first write circuit carry out a write operation.In one embodiment, if the write operation of the phase-change memory cell that writes that first write circuit 62 is present is not finished as yet, and when first write circuit 62 receives this control signal, first write circuit 62 is interrupted the write operation of this phase-change memory cell, and with adjusted write current reference data is write in this phase-change memory cell.In another embodiment, authenticate to the error in data that writes of (N-1) individual phase-change memory cell when authentication unit 61, and when the write operation that 62 pairs of N phase-change memory cells of first write circuit carry out has been finished, first write circuit 62 is adjusted the size of write current according to this control signal, and (N+1) individual phase-change memory cell is carried out write operation.In another embodiment, first write circuit 62 all comprises an auxiliary write circuit with this second write circuit 66, by this control signal, in order to adjust the size of write current.
Fig. 7 is the circuit diagram of an embodiment of a write circuit and auxiliary write circuit.Write circuit 72 is exported write current I according to the reference current Ires of a reference current source 71 outputs.73 in process auxiliary drive circuit utilizes the current replication mechanism of current mirror, by adjusting the breadth length ratio (W/L) of transistor T 1, T2, T3, T4, T5 and T6, export the auxiliary currents of different sizes, select the auxiliary current that to export by control signal S1, S2 and S3 again.In the present embodiment, process auxiliary drive circuit 73 is exported auxiliary current in the mode of current summation, and those skilled in the art make process auxiliary drive circuit 73 to export auxiliary current in the mode of current subtraction when making suitable modification according to this circuit.
Fig. 8 is the synoptic diagram according to another embodiment of the writing system of a phase transition storage of the present invention.First write circuit 82 receives and writes data, in order to recording phase change memory 83.Whether authentication unit 81 is according to a reference data, correct in order to the corresponding data of checking phase transition storage 83 storages.In the present embodiment, when authentication unit 81 when (N-1) individual phase-change memory cell is carried out a verification operation, this first write circuit 82 is carried out a write operation over against N phase-change memory cell.
After second write circuit 87 receives this control signal, can be with adjusted write current with reference data once more in the recording phase change memory 83.In the present embodiment, when authentication unit 81 when (N-1) individual phase-change memory cell is carried out a verification operation, 82 pairs of N phase-change memory cells of this first write circuit carry out a write operation.In one embodiment, if the write operation of the phase-change memory cell that writes that first write circuit 82 is present is not finished as yet, and when first write circuit 82 receives this control signal, first write circuit 82 is interrupted the write operation of this phase-change memory cell, and with adjusted write current reference data is write in this phase-change memory cell.In another embodiment, authenticate to the error in data that writes of (N-1) individual phase-change memory cell when authentication unit 81, and when the write operation of carrying out when 82 pairs of N phase-change memory cells of first write circuit has been finished, first write circuit 82 is adjusted the size of write current according to this control signal, and (N+1) individual phase-change memory cell is carried out write operation.In another embodiment, first write circuit 82 all comprises an auxiliary write circuit with this second write circuit 87, by this control signal, in order to adjust the size of write current.
Though the present invention discloses as above with specific embodiment; so it is only in order to be easy to illustrate technology contents of the present invention; and be not with narrow sense of the present invention be defined in this embodiment; those skilled in the art; under the premise without departing from the spirit and scope of the present invention; when can doing some changes and modification, so protection scope of the present invention should be as the criterion with the application's claim.
Claims (16)
1. the writing system of a phase transition storage comprises:
One first phase-change memory cell and one second phase-change memory cell;
One first write circuit is carried out a write-in program, receives one first data and writes to this first phase-change memory cell; And
One proof scheme is carried out a proving program, comprising:
One processing unit reads and the data and one second data of relatively this second phase-change memory cell storage; And
One second write circuit when the data and one second data of the storage of this second phase-change memory cell and when not meeting, writes this second phase-change memory cell once more with these second data.
2. the writing system of phase transition storage as claimed in claim 1, wherein this processing unit also comprises:
One reads circuit, in order to read the data of this second phase-change memory cell storage; And
One processor, relatively data and this second data of the storage of this second phase-change memory cell, and under the data and the incongruent situation of these second data of this second phase-change memory cell storage, export an electric current and adjust signal to this first write circuit and this second write circuit.
3. the writing system of phase transition storage as claimed in claim 2 wherein also comprises:
One the first transistor, have one first control end, a first input end and one first output terminal, wherein this first input end couples this first write circuit, and this first output terminal couples this first phase-change memory cell, and this first control end is controlled by one first control signal; And
One transistor seconds, have one second control end, one second input end and one second output terminal, wherein this second input end couples this and reads circuit, and this second output terminal couples this second phase-change memory cell, and this second control end is controlled by one second control signal.
4. the writing system of phase transition storage as claimed in claim 3, wherein the breadth length ratio of this transistor seconds is less than the breadth length ratio of this first transistor.
5. the writing system of phase transition storage as claimed in claim 2, wherein this processor also comprises:
One detects and comparator circuit, relatively data and this second data of this second phase-change memory cell storage, and export a comparison signal;
One electric current is adjusted control circuit, receives this comparison signal and exports this electric current adjustment signal.
6. the writing system of phase transition storage as claimed in claim 2, wherein this first write circuit also comprises one first auxiliary write circuit, receives this electric current and adjusts signal in order to adjust the write current size of this first write circuit output.
7. the writing system of phase transition storage as claimed in claim 6, wherein this first auxiliary write circuit comprises a current mirroring circuit, produce an auxiliary current according to a reference current, and adjust signal according to this electric current and export this auxiliary current to this first write circuit.
8. the writing system of phase transition storage as claimed in claim 2, wherein this second write circuit also comprises one second auxiliary write circuit, receives this electric current and adjusts signal in order to adjust the write current size of this second write circuit output.
9. the writing system of phase transition storage as claimed in claim 8, wherein this second auxiliary write circuit comprises a current mirroring circuit, produce an auxiliary current according to a reference current, and adjust signal according to this electric current and export this auxiliary current to this second write circuit.
10. the writing system of phase transition storage as claimed in claim 1, wherein this write-in program and this proving program are finished in the cycle at one time.
11. the wiring method of a phase transition storage utilizes a proof scheme and one first write circuit to finish, and comprising:
In a period 1, one first phase-change memory cell is carried out a write-in program;
In this period 1, one second phase-change memory cell is carried out a proving program; And
If this second phase-change memory cell authentication failed, then this proof scheme is exported an electric current and is adjusted signal to this first write circuit, adjusts first write current of this first write circuit output.
12. the wiring method of phase transition storage as claimed in claim 11, when wherein not finishing and receiving this electric current adjustment signal as yet as if this write-in program, this first write circuit is adjusted signal according to this electric current and is adjusted this first write current, and this first phase-change memory cell is carried out this write-in program again.
13. the wiring method of phase transition storage as claimed in claim 11, wherein this proof scheme also comprises one second write circuit, and when this second phase-change memory cell authentication failed, this second write circuit receives this electric current and adjusts one second write current of signal adjustment by this second write circuit output, and this second phase-change memory cell is carried out this write-in program again.
14. the wiring method of phase transition storage as claimed in claim 11 wherein also comprises:
In a second round one third phase is become storage unit and carry out this write-in program; And
In this second round, this first phase-change memory cell is carried out this proving program.
15. the wiring method of phase transition storage as claimed in claim 11, wherein this proving program also comprises:
Read the data that this second phase-change memory cell is stored;
This second phase-change memory cell data and reference data of storing relatively; And
If data and this reference data that this second phase-change memory cell is stored do not meet, export this electric current and adjust signal to this first write circuit.
16. the wiring method of phase transition storage as claimed in claim 15, wherein this proving program also comprises:
If data and this reference data that this second phase-change memory cell is stored meet, export a confirmation signal to this first write circuit, in order to keep the size of this first write current.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710197139XA CN101452743B (en) | 2007-12-05 | 2007-12-05 | Writing-in system and method for phase change memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710197139XA CN101452743B (en) | 2007-12-05 | 2007-12-05 | Writing-in system and method for phase change memory |
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| Publication Number | Publication Date |
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| CN101452743A CN101452743A (en) | 2009-06-10 |
| CN101452743B true CN101452743B (en) | 2011-10-26 |
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| TWI347607B (en) | 2007-11-08 | 2011-08-21 | Ind Tech Res Inst | Writing system and method for a phase change memory |
| TWI402845B (en) | 2008-12-30 | 2013-07-21 | Higgs Opl Capital Llc | Verification circuits and methods for phase change memory |
| TWI412124B (en) | 2008-12-31 | 2013-10-11 | Higgs Opl Capital Llc | Phase change memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545907B1 (en) * | 2001-10-30 | 2003-04-08 | Ovonyx, Inc. | Technique and apparatus for performing write operations to a phase change material memory device |
| CN1574093A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Device and method for pulse width control in a phase change memory device |
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- 2007-12-05 CN CN200710197139XA patent/CN101452743B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6545907B1 (en) * | 2001-10-30 | 2003-04-08 | Ovonyx, Inc. | Technique and apparatus for performing write operations to a phase change material memory device |
| CN1574093A (en) * | 2003-06-03 | 2005-02-02 | 三星电子株式会社 | Device and method for pulse width control in a phase change memory device |
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