CN101479852A - 无电容器单晶体管浮体动态随机存取存储器单元及其形成方法 - Google Patents

无电容器单晶体管浮体动态随机存取存储器单元及其形成方法 Download PDF

Info

Publication number
CN101479852A
CN101479852A CNA2007800239294A CN200780023929A CN101479852A CN 101479852 A CN101479852 A CN 101479852A CN A2007800239294 A CNA2007800239294 A CN A2007800239294A CN 200780023929 A CN200780023929 A CN 200780023929A CN 101479852 A CN101479852 A CN 101479852A
Authority
CN
China
Prior art keywords
word line
island
grid
semiconductive material
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2007800239294A
Other languages
English (en)
Other versions
CN101479852B (zh
Inventor
费尔南多·冈萨雷斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN101479852A publication Critical patent/CN101479852A/zh
Application granted granted Critical
Publication of CN101479852B publication Critical patent/CN101479852B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Abstract

本发明包括一种无电容器单晶体管DRAM单元，所述单元包括接纳于半导电材料(18)内的一对间隔开的源极/漏极区域(60、62)。电浮体区域(26)设置于所述半导电材料内的源极/漏极区域之间。间隔开的第一栅极(24)与所述源极/漏极区域之间的体区域分开且以电容方式耦合到所述体区域。一对相对的导电互连第二栅极(44、46)与所述第一栅极间隔开且横向接纳于所述第一栅极外部。所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。本发明揭示形成无电容器单晶体管DRAM单元的线路的方法。

Description

无电容器单晶体管浮体动态随机存取存储器单元及其形成方法
技术领域
本发明涉及无电容器单晶体管DRAM单元，涉及包含无电容器单晶体管DRAM单元阵列的集成电路，且涉及形成无电容器单晶体管DRAM单元的线路的方法。
背景技术
半导体存储器(例如，动态随机存取存储器(DRAM))广泛用于计算机系统中以存储数据。DRAM单元通常包括存取场效晶体管(FET)及存储电容器。所述存取FET允许数据电荷在读取及写入操作期间向及从所述存储电容器转移。所述存储电容器上的数据电荷在刷新操作期间周期性地刷新。
也已开发无电容器的单晶体管DRAM单元。一种类型的所述单元使用绝缘体上半导体晶体管的浮体效应，例如如第6,969,662号美国专利中所揭示。所述存储器单元可包含部分耗尽或完全耗尽的绝缘体上硅晶体管(或形成于体衬底材料中的晶体管)，其具有邻近所述体且通过栅极电介质与所述体分离设置的沟道。由于设置于所述晶体管的体区域下方的绝缘或非导电区域，所述体区域电浮动。通过电荷在所述绝缘体上半导体晶体管的体区域内的集中来确定所述存储器单元的状态。
虽然本发明的动机是解决上文所标识的问题，但其绝不受此限制。在不解释性或其它限制性参考本说明书的情况下且根据等效原则，本发明仅受随附权利要求书的字面文字的限制。
发明内容
附图说明
下文参照以下附图说明本发明的优选实施例。
图1是半导体衬底在根据本发明的方面的过程中的概略俯视平面图。
图2是沿图1中的线2-2截取的概略截面图。
图3是图1的衬底在图1所示的步骤之后的处理步骤处的视图。
图4是沿图3中的线4-4截取的概略截面图。
图5是图4的衬底在图4所示的步骤之后的处理步骤处的视图。
图6是图5的衬底在图5所示的步骤之后的处理步骤处的视图。
图7是图6的衬底在图6所示的步骤之后的处理步骤处的视图。
图8是图7的衬底在图7所示的步骤之后的处理步骤处的视图。
图9是图8的衬底的概略透视图。
图10是图8及9的衬底的概略俯视平面图，其中图8沿图10中的线8-8截取。
图11是图8的衬底在图8所示的步骤之后的处理步骤处的视图。
图12是图11的衬底的替代实施例衬底的概略截面图。
具体实施方式
所述论述首先着手论述形成无电容器单晶体管DRAM单元的线路的实例性方法。不管所述制造方法如何，本发明的方面还包括无电容器单晶体管DRAM单元，及包含无电容器单晶体管DRAM单元阵列的集成电路。
参照图1及2，一般使用参考编号10指示衬底(优选地是半导体衬底)。在本文件的上下文中，术语“半导体衬底”或“半导电衬底”经定义以意指包含半导电材料的任何构造，所述半导电材料包括但不限于例如半导电晶片(单独或在于其上包含其它材料的组件中)及半导电材料层(单独或在包含其它材料的组件中)等体半导电材料。术语“衬底”是指任何支撑结构，其包括但不限于上文所说明的半导电衬底。衬底10包含基础衬底12，举例来说体单晶硅。然而，衬底10可包含另一衬底(不管是现有或是尚待开发的衬底)，且举例来说包含绝缘体上半导体衬底。
衬底10经形成以包含间隔开的半导电材料18的岛20的实例性线路14、16。图中显示线路14、16为大致直线线性，但当然也涵盖弯曲、锯齿、成角或其它形状的线路。实例性优选半导电材料18为单晶硅，举例来说由实例性体半导体衬底材料12制作。仅以实例的方式，形成所描绘岛20的实例性方式是通过现有或尚待开发的沟槽及横向在岛20附近形成绝缘材料22的再填充技术。实例性优选材料包括二氧化硅及/或氮化硅中的一者或其组合。举例来说，可通过紧在岛20下方将氧原子离子植入到体衬底材料12中一峰值植入深度且从此形成二氧化硅在岛20下方上升地制作绝缘材料22。另外仅以实例的方式但并非最优选，可沉积绝缘材料22，在其中蚀刻岛开口20，且随后用半导电材料(举例来说，单晶硅及/或多晶硅)填充所述岛开口。再一选择为，当然，可使用一种或一种以上技术，从而将横向相对的沟槽做入半导体衬底12中，后跟岛20下方的横向底切蚀刻，且其中随后用一种或一种以上绝缘材料填充所述底切的体积。无论如何，在一个实例性实施方案中，可认为绝缘材料22被横向接纳于相应岛20附近及下方，且接触所述岛的半导电材料18。为便于说明，所述论述相对于形成无电容器单晶体管DRAM单元的线路(相对于间隔开的半导电材料18的岛20的线路14)的方法而继续。
参照图3及4，形成字线24，其为间隔开的岛20的线路14所共用且在间隔开的岛20的线路14上方延伸。字线24形成在相应间隔开的岛20的浮体区域26上方。字线24(举例来说)通过/借助所描绘的实例性电介质层28与体区域26间隔开且以电容方式耦合到体区域26。所述电介质层可包含任何适合的电介质，其中二氧化硅从优选的硅半导电材料18热生长仅为一个实例。材料28的实例性优选厚度范围是从12埃到100埃。另外仅以实例的方式，材料18的实例性优选深度是从500埃到1,000埃。字线24优选地包含高熔点金属、高熔点金属硅化物及/或经导电掺杂的半导电材料(例如，多晶硅)中的任一者或其组合。在字线24上方接纳绝缘顶盖30，其中氮化硅及/或二氧化硅为实例性材料。出于继续论述的目的，可认为字线24包含实例性图3描绘中的端32。出于继续论述的目的，可认为浮体区域26具有基底34，其中绝缘材料22被接纳抵靠在基底34上。在仅一个实施方案中，绝缘材料22在基底34下方的实例性优选厚度范围是从500埃到3,000埃。
参照图5，在字线/栅极24的侧壁上方形成绝缘材料36。所述绝缘材料可由单种材料或一种或一种以上材料组成，其中(举例来说)所描绘区域36中的每一者包含两个或两个以上不同绝缘材料层。实例性优选材料包括二氧化硅、氮化硅、氧氮化硅、二氧化铪及/或氧化铝。材料36的实例性优选厚度范围是从50埃到150埃。所述材料可通过在字线24的材料的侧壁上方热生长或沉积形成，此作为一个实例。另外仅以实例的方法，所述材料可通过沉积及随后的无掩模各向异性间隔物蚀刻形成。
已在字线24上方并与其间隔开地形成导电层38，举例来说通过绝缘/电介质材料30及36与其间隔开。层38的实例性优选材料包括氮化钛、多晶硅(p型或n型)、铝及硅化钴，其中层38的实例性优选厚度范围是从50埃到500埃。
参照图6，已在导电层38及字线24上方形成遮掩块40。仅以实例的方式，遮掩块40的优选材料包括光致抗蚀剂。出于继续论述的目的，可认为遮掩块40具有至少接近相对于导电层38接纳块40的地方的间隔开的相对横向边缘42。
参照图7，已加热遮掩块40，以在导电层38上方更加远离彼此地有效地横向向外移动相对的横向边缘42。用于进行此步骤的实例性技术包括在150℃下加热经图案化的光致抗蚀剂遮掩块40一到三分钟。在所述实例性优选实施例中，横向向外移动相对的横向边缘42一大致等于材料38在字线24的横向宽度外部的横向厚度的距离，其中先将遮掩块40图案化以与据以图案化字线24及其上的绝缘顶盖材料30的图案的遮掩块大致吻合。
参照图8-10，已使用遮掩块40(未显示)作为掩模蚀刻导电层38以形成一对互连栅极线44、46，其为间隔开的岛20的线路14所共用且沿着并横向邻近字线24的相对侧在间隔开的岛20的线路14上方延伸，其中栅极线44、46对被接纳于相应间隔开的岛20的相应浮体区域26上方。此仅提供一个将导电层38图案化为一对栅极线的实例性优选方法，所述对栅极线为间隔开的岛的线路所共用且沿着并横向邻近所述字线的相对侧在间隔开的岛的线路上方延伸。出于继续论述的目的，可认为栅极线44、46对包含接近字线端32的相应端48、50。在一个实例性实施方案中，层38的图案化致使字线端32不与栅极线端48、50中的任一者纵向共同定位，如所示实例。在一个优选实施方案中，导电层38的图案化致使字线24纵向延伸超出栅极线44、46对的相应端48、50，如所示实例。无论如何，在一个优选实施方案中，所述图案化形成长度比字线24的长度短的栅极线44、46对。
参照图9及10，将第一导电触点52形成到字线24，且将第二导电触点54形成到栅极线44、46对。因此，在最优选的实施例中，不同的第一及第二导电触点与相应的栅极线44、46及字线24相关联，使得可如所属技术领域中的技术人员所认识的那样单独对其进行控制，如下文所说明的实例。在图9及10中仅用虚线圈概略指示触点52及54，因为所述触点可能穿过随后沉积的电介质材料(出于清晰的目的未在图式中显示)形成到实例性所描绘位置。在一个实例性优选实施方案中，将第一导电触点52形成到纵向延伸超出栅极线44、46对的相应端48、50的字线24的某一部分，如所示实例。
参照图11，横向在互连栅极线44、46对外部且在岛20的半导电材料18内形成相应的间隔开的源极/漏极区域60、62对。因此，通常且优选地，在导电层38的图案化之后形成所述源极/漏极区域。无论如何，图11描绘实例性所制作无电容器单晶体管DRAM单元75。
在一个方面中，虽然制作多个所述DRAM单元为优选且为典型，但不管所述制造方法如何且不管是否制作多个所述DRAM单元，本发明均涵盖无电容器单晶体管DRAM单元。所述DRAM单元包含接纳于半导电材料内的一对间隔开的源极/漏极区域。上文所说明的区域60、62及形成于半导电材料18的实例性岛20内仅为实例性构造。在所述半导电材料内的源极/漏极区域之间设置电浮体区域。另外仅以实例的方式，将所述实例性单元描绘为并非完全耗尽式，其中直接在源极/漏极区域60、62下方的半导电材料也包含电浮体区域/材料。
第一栅极与所述源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。字线24的所述部分被接纳于个别岛20上方仅为一个实例性所述第一栅极。一对相对的导电互连第二栅极与所述第一栅极间隔开且横向接纳于所述第一栅极外部。所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。仅以实例的方式，第二栅极44、46构成一对实例性所述第二栅极。在一个所描绘且优选的实施方案中，第二栅极44、46通过导电材料(即，导电材料区域70)彼此导电互连，所述导电材料在第二栅极44、46对之间的第一栅极24上方上升延伸。第二栅极44、46对可通过另一方式导电互连，举例来说且仅以实例的方式，通过在最初隔离的第二栅极44、46上方形成的单独导电层。在所述实例中，所述导电层可相同于或不同于制成栅极44、46的材料。另外当然，栅极44及46不需要由相同的组合物构成，但优选地由相同化合物构成。
在一个优选实施方案中，无电容器单晶体管DRAM单元包含衬底，所述衬底包含半导电材料岛。在所述岛附近及下方横向接纳绝缘材料且所述绝缘材料接触所述岛的半导电材料。在所述岛半导电材料内接纳一对间隔开的源极/漏极区域。在所述岛半导电材料内的源极/漏极区域之间设置电浮体区域。第一栅极与所述岛的源极/漏极区域之间的岛体区域间隔开且以电容方式耦合到所述岛体区域。一对导电第二栅极与所述第一栅极间隔开且被横向接纳于所述第一栅极外部，其中所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的体区域间隔开且以电容方式耦合到所述体区域。此可包含于上文所说明方法及结构中的任一者中。
图12描绘替代且对应于图11的实施方案及实施例的实例性额外实施方案及实施例。已在适当地方使用来自首先说明的实施例的相同编号，其中用后缀“a”或用不同的编号指示不同之处。在图12中，优选地在相应岛20附近及下方横向接纳绝缘材料22a且绝缘材料22a接触所述岛的半导电材料18。在绝缘材料22a外部在相应岛20附近及下方横向接纳经导电掺杂的半导电材料80。实例性优选材料80为经导电掺杂p型或n型多晶硅。优选地，绝缘材料22a在岛20下方及在岛20的横向侧壁与经导电掺杂的半导电材料80之间(两者)具有不大于200埃的厚度。材料22a的更优选所述厚度范围是从50埃到150埃。当然，可通过任何现有或尚待开发的方法制作图12的构造。
所属领域的技术人员将了解并开发用于在上文所描绘实例性DRAM单元内且在包含所述DRAM单元阵列的集成电路中写入、读取、刷新及/或保存数据的各种操作电压。仅以实例的方式，以下表格描绘实例性操作电压，其中Vi是第一栅极电压，Vcs(导电间隔物)是所述对第二栅极的电压，Vt是阈值电压，Vs是源极电压，且VD是漏极电压。另外仅以实例的方式，在所述实例中使用图12实施例中导电的包围半导电材料80，优选地将此半导电材料维持在-3V到-10V的某一适合实例性固定电压下不变。使用包围经导电掺杂的半导电材料80的优选非限制性原因是建立并维持晶体管的优选多晶硅的两侧的相同电位，使得电荷通过电介质电容在所述结构的壁处聚集。
其所长                       实例性操作电压
          Vi           Vcs          Vt        VD          Vs
写入      -3V到-10V    -2.5V        高       1.8V/0V     浮动/0V
保存数据  -3V到-10V    0V           高       浮动/浮动   浮动/0V
读取      2.5V         2.5V         0.5V     0.1V/0.1V   0V/0V
重新写入  -3V到-10V    -2.5V        高       1.8V/0V     浮动/0V
保存数据  -3V到-10V    0V           高       浮动/浮动   浮动/0V
仅以实例的方式，在以下专利中揭示用于无电容器单晶体管DRAM单元的操作的实例性技术及构造：第6,969,662号美国专利；发表编号为2005/0017240及2005/0063224的美国专利申请案；郭(Kuo)等人发表于IEDM，IEEE 2002第843-846页的“用于高密度应用的无电容器双栅极DRAM栅极单元设计(A CapacitorlessDouble-Gate DRAM Gate Cell Design For High Density Applications)”；及吉田(Yoshida)等人发表于IEEE电子装置学报第53卷第4号2006年4月第692-697页的“将栅极诱发漏极泄漏(GIDL)电流用于低功率及高速度嵌入式存储器的无电容器1T-DRAM技术(A Capacitorless 1 T-DRAM Technology Using Gate-InducedDrain-Leakage(GIDL)Current For Low-Power And High-Speed Embedded Memory)”。第5,714,786、6,005,273、6,090,693及7,005,710号美国专利的揭示内容以引用的方式并入本文中。

Claims (38)

1、一种无电容器单晶体管DRAM单元，其包含：
一对间隔开的源极/漏极区域，其接纳于半导电材料内；
电浮体区域，其设置于所述半导电材料内的所述源极/漏极区域之间；
第一栅极，其与所述源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域；及
一对相对的导电互连第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域。
2、如权利要求1所述的DRAM单元，其中所述对第二栅极由在所述对第二栅极之间的所述第一栅极上方上升延伸的导电材料导电互连。
3、如权利要求1所述的DRAM单元，其中所述第一栅极由至少两种绝缘材料与所述第二栅极分离。
4、如权利要求1所述的DRAM单元，其中所述浮体区域具有基底，绝缘层被接纳抵靠所述基底，所述绝缘层具有从500埃到3,000埃的厚度。
5、如权利要求1所述的DRAM单元，其中：
所述浮体区域具有基底，绝缘层被接纳抵靠所述基底；且
经导电掺杂的半导电材料接纳抵靠所述基底下方的所述绝缘层。
6、如权利要求5所述的DRAM单元，其中所述绝缘层在所述基底与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
7、一种无电容器单晶体管DRAM单元，其包含：
衬底，其包含半导电材料岛；
绝缘材料，其横向接纳于所述岛附近及下方并接触所述岛的半导电材料；
一对间隔开的源极/漏极区域，其接纳于所述岛半导电材料内；
电浮体区域，其设置于所述岛半导电材料内的所述源极/漏极区域之间；
第一栅极，其与所述岛源极/漏极区域之间的所述岛体区域间隔开且以电容方式耦合到所述岛体区域；及
一对导电第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述第一栅极外部且在所述对源极/漏极区域之间的所述体区域间隔开且以电容方式耦合到所述体区域。
8、如权利要求7所述的DRAM单元，其包含在所述绝缘材料外部横向接纳于所述岛附近及下方的经导电掺杂的半导电材料。
9、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方具有不大于200埃的厚度。
10、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
11、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方及在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
12、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛下方具有从50埃到150埃的厚度。
13、如权利要求8所述的DRAM单元，其中所述绝缘材料在所述岛的横向侧壁与所述经导电掺杂的半导电材料之间具有从50埃到150埃的厚度。
14、一种包含无电容器单晶体管DRAM单元阵列的集成电路，其包含：
间隔开的半导电材料岛的线路，其接纳于衬底内；及
个别无电容器单晶体管DRAM单元，其相对于所述间隔开的岛中的个别岛被接纳，所述个别单元包含：
一对源极/漏极区域，其接纳于所述相应岛的所述半导电材料内；
电浮体区域，其设置于所述相应岛的所述半导电材料内的所述源极/漏极区域之间；
第一栅极，其由字线组成，所述字线为所述相应对源极/漏极区域之间的间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸，所述字线与所述相应对源极/漏极区域之间的所述相应岛的所述相应体区域间隔开且以电容方式耦合到所述相应体区域；及
一对相对的导电互连第二栅极，其与所述第一栅极间隔开且横向接纳于所述第一栅极外部，所述第二栅极与横向位于所述相应第一栅极外部且在所述相应岛的所述相应对源极/漏极区域之间的所述相应体区域间隔开且以电容方式耦合到所述相应体区域，所述对相对的互连第二栅极包含为间隔开的岛的所述线路所共用且沿所述字线上升地并横向地接纳于所述字线上方的导电线。
15、如权利要求14所述的集成电路，其包含连接到所述字线的第一导电触点及连接到所述导电线的不同的第二导电触点。
16、如权利要求14所述的集成电路，其中所述字线在长度上比所述导电线长。
17、如权利要求14所述的集成电路，其中所述导电线具有一端且所述字线具有接近所述导电线端的一端，所述字线端与所述导电线端不纵向共同定位。
18、如权利要求17所述的集成电路，其中所述字线在长度上比所述导电线长。
19、如权利要求17所述的集成电路，其中所述字线端纵向接纳于所述导电线端外部。
20、如权利要求19所述的集成电路，其中所述字线在长度上比所述导电线长。
21、如权利要求14所述的集成电路，其包含横向接纳于所述相应岛附近及下方且接触所述相应岛的半导电材料的绝缘材料；及
在所述绝缘材料外部横向接纳于所述岛附近及下方的经导电掺杂的半导电材料。
22、如权利要求21所述的集成电路，其中所述绝缘材料在所述相应岛下方及在所述相应岛的横向侧壁与所述经导电掺杂的半导电材料之间具有不大于200埃的厚度。
23、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方；
在所述字线上方且与所述字线间隔开地形成导电层；
将所述导电层图案化为一对栅极线，所述对栅极线为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在所述间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方，所述图案化将所述对栅极线形成为在长度上比所述字线的长度短；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述对栅极线外部。
24、如权利要求23所述的方法，其中在所述图案化之后形成所述源极/漏极区域。
25、如权利要求23所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
26、如权利要求23所述的方法，其中所述字线经形成以具有一端且所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线端不与所述栅极线端中的任一者纵向共同定位。
27、如权利要求23所述的方法，其中所述图案化包含：
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；及
在所述加热之后，使用所述遮掩块作为掩模来蚀刻所述导电层以形成所述对栅极线。
28、如权利要求27所述的方法，其中所述字线经形成以具有一端且所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线端不与所述栅极线端中的任一者纵向共同定位。
29、如权利要求23所述的方法，其包含：
提供横向在所述相应岛附近及下方并接触所述相应岛的半导电材料的绝缘材料；及
提供在所述绝缘材料外部横向在所述岛附近及下方的经导电掺杂的半导电材料。
30、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方且包含一端；
在所述字线上方且与所述字线间隔开地形成导电层；
将所述导电层图案化为一对栅极线，其为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在所述间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方，所述图案化形成所述对栅极线的接近所述字线端的相应端，所述图案化致使所述字线纵向延伸超出所述对栅极线的所述相应端；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述对栅极线外部。
31、如权利要求30所述的方法，其中所述图案化包含：
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；及
在所述加热之后，使用所述遮掩块作为掩模来蚀刻所述导电层以形成所述对栅极线。
32、如权利要求30所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
33、如权利要求32所述的方法，其包含将所述第一导电触点形成到所述字线的纵向延伸超出所述对栅极线的所述相应端的某一部分。
34、如权利要求30所述的方法，其包含：
提供横向在所述相应岛附近及下方并接触所述相应岛的半导电材料的绝缘材料；及
提供在所述绝缘材料外部横向在所述岛附近及下方的经导电掺杂的半导电材料。
35、一种形成无电容器单晶体管DRAM单元的线路的方法，其包含：
相对于衬底形成间隔开的半导电材料岛的线路；
形成为间隔开的岛的所述线路所共用且在所述间隔开的岛的所述线路上方延伸的字线，所述字线形成在所述相应间隔开的岛的电浮体区域上方；
在所述字线上方且与所述字线间隔开地形成导电层；
在所述导电层及所述字线上方形成遮掩块，所述遮掩块具有间隔开的相对横向边缘；
在形成所述遮掩块之后，加热所述遮掩块以在所述导电层上方有效地横向向外移动所述相对横向边缘更加远离彼此；
在所述加热之后，使用所述遮掩块作为掩模蚀刻所述导电层以形成一对互连栅极线，所述对互连栅极线为间隔开的岛的所述线路所共用且沿着并横向邻近所述字线的相对侧在间隔开的岛的所述线路上方延伸，所述对栅极线接纳于所述相应间隔开的岛的相应浮体区域上方；及
在所述相应岛的所述半导电材料内形成相应对间隔开的源极/漏极区域，所述对间隔开的源极/漏极区域横向接纳于所述互连对栅极线外部。
36、如权利要求35所述的方法，其包含形成所述遮掩块以包含光致抗蚀剂。
37、如权利要求35所述的方法，其中在所述图案化之后形成所述源极/漏极区域。
38、如权利要求35所述的方法，其包含将第一导电触点形成到所述字线及将第二导电触点形成到所述对栅极线。
39、如权利要求38所述的方法，其包含将所述第一导电触点形成到所述字线的纵向延伸超出所述对栅极线的所述相应端的某一部分。
CN2007800239294A 2006-07-17 2007-06-25 无电容器单晶体管浮体动态随机存取存储器单元及其形成方法 Active CN101479852B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/488,384 2006-07-17
US11/488,384 US7602001B2 (en) 2006-07-17 2006-07-17 Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
PCT/US2007/014689 WO2008010891A2 (en) 2006-07-17 2007-06-25 Capacitorlbss one-transistor floating-body dram cell and method of forming the same

Publications (2)

Publication Number Publication Date
CN101479852A true CN101479852A (zh) 2009-07-08
CN101479852B CN101479852B (zh) 2012-06-13

Family

ID=38668936

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2007800239294A Active CN101479852B (zh) 2006-07-17 2007-06-25 无电容器单晶体管浮体动态随机存取存储器单元及其形成方法

Country Status (8)

Country Link
US (3) US7602001B2 (zh)
EP (2) EP2772942A3 (zh)
JP (1) JP5181304B2 (zh)
KR (1) KR101149666B1 (zh)
CN (1) CN101479852B (zh)
SG (1) SG173381A1 (zh)
TW (1) TWI356471B (zh)
WO (1) WO2008010891A2 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547945B2 (en) * 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) * 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) * 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
KR101324196B1 (ko) * 2007-06-05 2013-11-06 삼성전자주식회사 커패시터리스 디램 및 그의 제조방법
US8999852B2 (en) 2012-12-12 2015-04-07 Micron Technology, Inc. Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice pattern from an oblique lattice pattern, and methods of forming a pattern on a substrate
US8889559B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8889558B2 (en) 2012-12-12 2014-11-18 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8937018B2 (en) * 2013-03-06 2015-01-20 Micron Technology, Inc. Methods of forming a pattern on a substrate
US10068918B2 (en) 2015-09-21 2018-09-04 Globalfoundries Inc. Contacting SOI subsrates
US9859388B1 (en) 2016-06-17 2018-01-02 International Business Machines Corporation Uniform vertical field effect transistor spacers
US9812443B1 (en) 2017-01-13 2017-11-07 International Business Machines Corporation Forming vertical transistors and metal-insulator-metal capacitors on the same chip

Family Cites Families (311)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51147280A (en) * 1975-06-13 1976-12-17 Hitachi Ltd Semiconductor device
JPS5681974A (en) 1979-12-07 1981-07-04 Toshiba Corp Manufacture of mos type semiconductor device
JPS58220464A (ja) * 1982-06-17 1983-12-22 Fujitsu Ltd 半導体記憶装置
KR920010461B1 (ko) 1983-09-28 1992-11-28 가부시끼가이샤 히다찌세이사꾸쇼 반도체 메모리와 그 제조 방법
JPS60256747A (ja) 1984-06-01 1985-12-18 Nippon Denso Co Ltd 空調装置の吹き出し口
WO1986003341A1 (en) 1984-11-27 1986-06-05 American Telephone & Telegraph Company Trench transistor
GB2190789B (en) * 1986-04-17 1990-05-09 Plessey Co Plc System for optically coupling components of integrated circuits
US4722910A (en) * 1986-05-27 1988-02-02 Analog Devices, Inc. Partially self-aligned metal contact process
US4835741A (en) 1986-06-02 1989-05-30 Texas Instruments Incorporated Frasable electrically programmable read only memory cell using a three dimensional trench floating gate
US5160491A (en) 1986-10-21 1992-11-03 Texas Instruments Incorporated Method of making a vertical MOS transistor
JPS63183691A (ja) 1987-01-26 1988-07-29 Mitsubishi Electric Corp 半導体記憶装置
FR2625044B1 (fr) 1987-12-18 1990-08-31 Commissariat Energie Atomique Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor
US4979004A (en) 1988-01-29 1990-12-18 Texas Instruments Incorporated Floating gate memory cell and device
US4931409A (en) 1988-01-30 1990-06-05 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device having trench isolation
US5014110A (en) 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
JPH0294477A (ja) 1988-09-30 1990-04-05 Toshiba Corp 半導体装置及びその製造方法
JPH0778977B2 (ja) 1989-03-02 1995-08-23 松下電器産業株式会社 磁気ディスクカートリッジ
US5108938A (en) 1989-03-21 1992-04-28 Grumman Aerospace Corporation Method of making a trench gate complimentary metal oxide semiconductor transistor
US5021355A (en) 1989-05-22 1991-06-04 International Business Machines Corporation Method of fabricating cross-point lightly-doped drain-source trench transistor
JPH03219677A (ja) 1990-01-24 1991-09-27 Fujitsu Ltd 半導体装置
US5107459A (en) 1990-04-20 1992-04-21 International Business Machines Corporation Stacked bit-line architecture for high density cross-point memory cell array
JPH0834302B2 (ja) 1990-04-21 1996-03-29 株式会社東芝 半導体記憶装置
US5013680A (en) 1990-07-18 1991-05-07 Micron Technology, Inc. Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography
US5244824A (en) 1990-09-05 1993-09-14 Motorola, Inc. Trench capacitor and transistor structure and method for making the same
US5047117A (en) 1990-09-26 1991-09-10 Micron Technology, Inc. Method of forming a narrow self-aligned, annular opening in a masking layer
US5289030A (en) 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
US5122848A (en) 1991-04-08 1992-06-16 Micron Technology, Inc. Insulated-gate vertical field-effect transistor with high current drive and minimum overlap capacitance
JPH07106435B2 (ja) 1991-04-15 1995-11-15 新日本製鐵株式会社 双ロール式連続鋳造装置
KR940006679B1 (ko) 1991-09-26 1994-07-25 현대전자산업 주식회사 수직형 트랜지스터를 갖는 dram셀 및 그 제조방법
US5467305A (en) 1992-03-12 1995-11-14 International Business Machines Corporation Three-dimensional direct-write EEPROM arrays and fabrication methods
US5573837A (en) 1992-04-22 1996-11-12 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
US5254218A (en) 1992-04-22 1993-10-19 Micron Technology, Inc. Masking layer having narrow isolated spacings and the method for forming said masking layer and the method for forming narrow isolated trenches defined by said masking layer
JP2748072B2 (ja) 1992-07-03 1998-05-06 三菱電機株式会社 半導体装置およびその製造方法
US5281548A (en) 1992-07-28 1994-01-25 Micron Technology, Inc. Plug-based floating gate memory
JP2889061B2 (ja) 1992-09-25 1999-05-10 ローム株式会社 半導体記憶装置およびその製法
JP3311070B2 (ja) 1993-03-15 2002-08-05 株式会社東芝 半導体装置
US5358879A (en) 1993-04-30 1994-10-25 Loral Federal Systems Company Method of making gate overlapped lightly doped drain for buried channel devices
WO1994027325A1 (en) 1993-05-07 1994-11-24 Vlsi Technology, Inc. Integrated circuit structure and method
KR0141218B1 (ko) 1993-11-24 1998-07-15 윤종용 고집적 반도체장치의 제조방법
US5514604A (en) 1993-12-08 1996-05-07 General Electric Company Vertical channel silicon carbide metal-oxide-semiconductor field effect transistor with self-aligned gate for microwave and power applications, and method of making
US5532089A (en) 1993-12-23 1996-07-02 International Business Machines Corporation Simplified fabrication methods for rim phase-shift masks
KR100362751B1 (ko) 1994-01-19 2003-02-11 소니 가부시끼 가이샤 반도체소자의콘택트홀및그형성방법
US5964750A (en) 1994-03-15 1999-10-12 Medolas Gesellschaft Fuer Medizintechnik Gmbh Laser catheter for bypass surgery
JP2658870B2 (ja) 1994-04-22 1997-09-30 日本電気株式会社 半導体記憶装置およびその製造方法
US5413949A (en) 1994-04-26 1995-05-09 United Microelectronics Corporation Method of making self-aligned MOSFET
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
US5841611A (en) 1994-05-02 1998-11-24 Matsushita Electric Industrial Co., Ltd. Magnetoresistance effect device and magnetoresistance effect type head, memory device, and amplifying device using the same
KR0151195B1 (ko) * 1994-09-13 1998-10-01 문정환 박막 트랜지스터의 구조 및 제조방법
US5753947A (en) 1995-01-20 1998-05-19 Micron Technology, Inc. Very high-density DRAM cell structure and method for fabricating it
US5574621A (en) 1995-03-27 1996-11-12 Motorola, Inc. Integrated circuit capacitor having a conductive trench
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
DE19519160C1 (de) 1995-05-24 1996-09-12 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JPH0982918A (ja) 1995-09-19 1997-03-28 Toshiba Corp 半導体記憶装置およびその製造方法
KR0179175B1 (ko) * 1995-10-05 1999-03-20 문정환 반도체 메모리 장치 및 제조방법
US5854501A (en) 1995-11-20 1998-12-29 Micron Technology, Inc. Floating gate semiconductor device having a portion formed with a recess
US6420786B1 (en) 1996-02-02 2002-07-16 Micron Technology, Inc. Conductive spacer in a via
JP2751909B2 (ja) 1996-02-26 1998-05-18 日本電気株式会社 半導体装置の製造方法
US6090700A (en) 1996-03-15 2000-07-18 Vanguard International Semiconductor Corporation Metallization method for forming interconnects in an integrated circuit
JP3219677B2 (ja) 1996-03-28 2001-10-15 三洋電機株式会社 ロッド選別システム
US5869539A (en) 1996-04-17 1999-02-09 Board Of Regents, The University Of Texas System Emulsions of perfluoro compounds as solvents for nitric oxide (NO)
KR20000015822A (ko) 1996-05-21 2000-03-15 칼 하인쯔 호르닝어 박막 다층 콘덴서_
DE19620625C1 (de) 1996-05-22 1997-10-23 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JPH1022476A (ja) 1996-07-02 1998-01-23 Sony Corp 容量素子
US5792687A (en) 1996-08-01 1998-08-11 Vanguard International Semiconductor Corporation Method for fabricating high density integrated circuits using oxide and polysilicon spacers
TW308727B (en) 1996-08-16 1997-06-21 United Microelectronics Corp Semiconductor memory device with capacitor (4)
TW304290B (en) 1996-08-16 1997-05-01 United Microelectronics Corp The manufacturing method for semiconductor memory device with capacitor
US5739066A (en) 1996-09-17 1998-04-14 Micron Technology, Inc. Semiconductor processing methods of forming a conductive gate and line
US5714786A (en) 1996-10-31 1998-02-03 Micron Technology, Inc. Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
JP4056588B2 (ja) 1996-11-06 2008-03-05 富士通株式会社 半導体装置及びその製造方法
US5714412A (en) 1996-12-02 1998-02-03 Taiwan Semiconductor Manufacturing Company, Ltd Multi-level, split-gate, flash memory cell and method of manufacture thereof
KR19980064176A (ko) 1996-12-17 1998-10-07 윌리엄비.켐플러 집적 회로 유전체
JP4053647B2 (ja) 1997-02-27 2008-02-27 株式会社東芝 半導体記憶装置及びその製造方法
US5792690A (en) 1997-05-15 1998-08-11 Vanguard International Semiconductor Corporation Method of fabricating a DRAM cell with an area equal to four times the used minimum feature
US6337497B1 (en) 1997-05-16 2002-01-08 International Business Machines Corporation Common source transistor capacitor stack
US6054355A (en) 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
US5909618A (en) 1997-07-08 1999-06-01 Micron Technology, Inc. Method of making memory cell with vertical transistor and buried word and body lines
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
US6191470B1 (en) 1997-07-08 2001-02-20 Micron Technology, Inc. Semiconductor-on-insulator memory cell with buried word and body lines
US6072209A (en) 1997-07-08 2000-06-06 Micro Technology, Inc. Four F2 folded bit line DRAM cell structure having buried bit and word lines
US5869359A (en) 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6380026B2 (en) 1997-08-22 2002-04-30 Micron Technology, Inc. Processing methods of forming integrated circuitry memory devices, methods of forming DRAM arrays, and related semiconductor masks
JP3502531B2 (ja) 1997-08-28 2004-03-02 株式会社ルネサステクノロジ 半導体装置の製造方法
DE19801095B4 (de) 1998-01-14 2007-12-13 Infineon Technologies Ag Leistungs-MOSFET
US5998835A (en) 1998-02-17 1999-12-07 International Business Machines Corporation High performance MOSFET device with raised source and drain
US6246083B1 (en) 1998-02-24 2001-06-12 Micron Technology, Inc. Vertical gain cell and array for a dynamic random access memory
US5963469A (en) 1998-02-24 1999-10-05 Micron Technology, Inc. Vertical bipolar read access for low voltage memory cell
US6097065A (en) 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6259142B1 (en) 1998-04-07 2001-07-10 Advanced Micro Devices, Inc. Multiple split gate semiconductor device and fabrication method
US6696746B1 (en) 1998-04-29 2004-02-24 Micron Technology, Inc. Buried conductors
US5972754A (en) 1998-06-10 1999-10-26 Mosel Vitelic, Inc. Method for fabricating MOSFET having increased effective gate length
US6767789B1 (en) 1998-06-26 2004-07-27 International Business Machines Corporation Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby
US6458925B1 (en) 1998-08-03 2002-10-01 University Of Maryland, Baltimore Peptide antagonists of zonulin and methods for use of the same
KR100304717B1 (ko) 1998-08-18 2001-11-15 김덕중 트렌치형게이트를갖는반도체장치및그제조방법
US6362506B1 (en) 1998-08-26 2002-03-26 Texas Instruments Incorporated Minimization-feasible word line structure for DRAM cell
JP3239109B2 (ja) 1998-08-28 2001-12-17 株式会社半導体理工学研究センター 強誘電体不揮発性メモリとその読み出し方法
JP4322330B2 (ja) 1998-09-04 2009-08-26 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
DE19845003C1 (de) 1998-09-30 2000-02-10 Siemens Ag Vertikaler Feldeffekttransistor mit innenliegendem ringförmigen Gate und Herstellverfahren
US6225669B1 (en) 1998-09-30 2001-05-01 Advanced Micro Devices, Inc. Non-uniform gate/dielectric field effect transistor
US6120952A (en) 1998-10-01 2000-09-19 Micron Technology, Inc. Methods of reducing proximity effects in lithographic processes
US6114205A (en) 1998-10-30 2000-09-05 Sony Corporation Epitaxial channel vertical MOS transistor
EP1003219B1 (en) 1998-11-19 2011-12-28 Qimonda AG DRAM with stacked capacitor and buried word line
US5977579A (en) 1998-12-03 1999-11-02 Micron Technology, Inc. Trench dram cell with vertical device and buried word lines
JP2000208762A (ja) 1999-01-13 2000-07-28 Sony Corp 絶縁ゲ―ト電界効果トランジスタおよびその製造方法
US6383861B1 (en) 1999-02-18 2002-05-07 Micron Technology, Inc. Method of fabricating a dual gate dielectric
JP3973819B2 (ja) 1999-03-08 2007-09-12 株式会社東芝 半導体記憶装置およびその製造方法
US6180494B1 (en) 1999-03-11 2001-01-30 Micron Technology, Inc. Integrated circuitry, methods of fabricating integrated circuitry, methods of forming local interconnects, and methods of forming conductive lines
KR100282452B1 (ko) 1999-03-18 2001-02-15 김영환 반도체 소자 및 그의 제조 방법
JP2001024161A (ja) * 1999-04-30 2001-01-26 Sony Corp 半導体メモリセル
US6297106B1 (en) 1999-05-07 2001-10-02 Chartered Semiconductor Manufacturing Ltd. Transistors with low overlap capacitance
WO2000070622A1 (fr) 1999-05-14 2000-11-23 Hitachi, Ltd. Circuit de memorisation
US6306755B1 (en) 1999-05-14 2001-10-23 Koninklijke Philips Electronics N.V. (Kpenv) Method for endpoint detection during dry etch of submicron features in a semiconductor device
DE19928781C1 (de) 1999-06-23 2000-07-06 Siemens Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
US6392271B1 (en) 1999-06-28 2002-05-21 Intel Corporation Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6187643B1 (en) 1999-06-29 2001-02-13 Varian Semiconductor Equipment Associates, Inc. Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI)
US6114735A (en) 1999-07-02 2000-09-05 Micron Technology, Inc. Field effect transistors and method of forming field effect transistors
US6214670B1 (en) 1999-07-22 2001-04-10 Taiwan Semiconductor Manufacturing Company Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance
US6630712B2 (en) 1999-08-11 2003-10-07 Advanced Micro Devices, Inc. Transistor with dynamic source/drain extensions
US6033963A (en) 1999-08-30 2000-03-07 Taiwan Semiconductor Manufacturing Company Method of forming a metal gate for CMOS devices using a replacement gate process
US6461915B1 (en) 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
US6403442B1 (en) 1999-09-02 2002-06-11 Micron Technology, Inc. Methods of forming capacitors and resultant capacitor structures
DE19943760C1 (de) 1999-09-13 2001-02-01 Infineon Technologies Ag DRAM-Zellenanordnung und Verfahren zu deren Herstellung
JP3450758B2 (ja) 1999-09-29 2003-09-29 株式会社東芝 電界効果トランジスタの製造方法
US6303518B1 (en) 1999-09-30 2001-10-16 Novellus Systems, Inc. Methods to improve chemical vapor deposited fluorosilicate glass (FSG) film adhesion to metal barrier or etch stop/diffusion barrier layers
US6255165B1 (en) 1999-10-18 2001-07-03 Advanced Micro Devices, Inc. Nitride plug to reduce gate edge lifting
TW432546B (en) 1999-11-25 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method of copper damascene
US6383879B1 (en) 1999-12-03 2002-05-07 Agere Systems Guardian Corp. Semiconductor device having a metal gate with a work function compatible with a semiconductor device
US6323506B1 (en) 1999-12-21 2001-11-27 Philips Electronics North America Corporation Self-aligned silicon carbide LMOSFET
JP4860022B2 (ja) 2000-01-25 2012-01-25 エルピーダメモリ株式会社 半導体集積回路装置の製造方法
JP4363736B2 (ja) 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
US6686616B1 (en) 2000-05-10 2004-02-03 Cree, Inc. Silicon carbide metal-semiconductor field effect transistors
US6399490B1 (en) 2000-06-29 2002-06-04 International Business Machines Corporation Highly conformal titanium nitride deposition process for high aspect ratio structures
US6348387B1 (en) * 2000-07-10 2002-02-19 Advanced Micro Devices, Inc. Field effect transistor with electrically induced drain and source extensions
DE10036725C2 (de) 2000-07-27 2002-11-28 Infineon Technologies Ag Verfahren zur Herstellung einer porösen Isolierschicht mit niedriger Dielektrizitätskonstante auf einem Halbleitersubstrat
DE10038728A1 (de) 2000-07-31 2002-02-21 Infineon Technologies Ag Halbleiterspeicher-Zellenanordnung und Verfahren zu deren Herstellung
WO2002019396A1 (en) 2000-08-29 2002-03-07 Boise State University Damascene double gated transistors and related manufacturing methods
US6495474B1 (en) 2000-09-11 2002-12-17 Agere Systems Inc. Method of fabricating a dielectric layer
US6391720B1 (en) 2000-09-27 2002-05-21 Chartered Semiconductor Manufacturing Ltd. Process flow for a performance enhanced MOSFET with self-aligned, recessed channel
US6340614B1 (en) 2000-10-03 2002-01-22 Vanguard International Semiconductor Corporation Method of forming a DRAM cell
JP2002151654A (ja) * 2000-11-10 2002-05-24 Sharp Corp 誘電体キャパシタ素子及びその製造方法
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US6348385B1 (en) 2000-11-30 2002-02-19 Chartered Semiconductor Manufacturing Ltd. Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant
GB0029315D0 (en) * 2000-12-01 2001-01-17 Koninkl Philips Electronics Nv Method of increasing the conductivity of a transparent conductive layer
US6621112B2 (en) 2000-12-06 2003-09-16 Infineon Technologies Ag DRAM with vertical transistor and trench capacitor memory cells and methods of fabrication
JP4635333B2 (ja) 2000-12-14 2011-02-23 ソニー株式会社 半導体装置の製造方法
US6864536B2 (en) 2000-12-20 2005-03-08 Winbond Electronics Corporation Electrostatic discharge protection circuit
KR100360414B1 (ko) 2001-01-05 2002-11-13 삼성전자 주식회사 트윈 비트 결함을 방지하는 실린더형 커패시터의 하부전극형성방법
US6300177B1 (en) 2001-01-25 2001-10-09 Chartered Semiconductor Manufacturing Inc. Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials
JP3944367B2 (ja) 2001-02-06 2007-07-11 松下電器産業株式会社 絶縁膜の形成方法及び半導体装置の製造方法
KR100388682B1 (ko) 2001-03-03 2003-06-25 삼성전자주식회사 반도체 메모리 장치의 스토리지 전극층 및 그 형성방법
US6759707B2 (en) 2001-03-08 2004-07-06 Micron Technology, Inc. 2F2 memory device system
DE10111755C1 (de) 2001-03-12 2002-05-16 Infineon Technologies Ag Verfahren zur Herstellung einer Speicherzelle eines Halbleiterspeichers
CA2340985A1 (en) 2001-03-14 2002-09-14 Atmos Corporation Interleaved wordline architecture
US6734510B2 (en) 2001-03-15 2004-05-11 Micron Technology, Ing. Technique to mitigate short channel effects with vertical gate transistor with different gate materials
JP4895430B2 (ja) 2001-03-22 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP3671854B2 (ja) 2001-04-05 2005-07-13 松下電器産業株式会社 シリコン系基板の表面処理方法
JP2002314072A (ja) 2001-04-19 2002-10-25 Nec Corp 高誘電体薄膜を備えた半導体装置及びその製造方法並びに誘電体膜の成膜装置
US6632723B2 (en) 2001-04-26 2003-10-14 Kabushiki Kaisha Toshiba Semiconductor device
US6498062B2 (en) 2001-04-27 2002-12-24 Micron Technology, Inc. DRAM access transistor
US6509612B2 (en) 2001-05-04 2003-01-21 International Business Machines Corporation High dielectric constant materials as gate dielectrics (insulators)
US6624486B2 (en) 2001-05-23 2003-09-23 International Business Machines Corporation Method for low topography semiconductor device formation
DE10125967C1 (de) 2001-05-29 2002-07-11 Infineon Technologies Ag DRAM-Zellanordnung mit vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
JP2002353445A (ja) 2001-05-30 2002-12-06 Sony Corp 溝ゲート型電界効果トランジスタの製造方法
US6888198B1 (en) 2001-06-04 2005-05-03 Advanced Micro Devices, Inc. Straddled gate FDSOI device
TWI230392B (en) 2001-06-18 2005-04-01 Innovative Silicon Sa Semiconductor device
JP4246929B2 (ja) 2001-06-29 2009-04-02 株式会社東芝 半導体記憶装置およびその製造方法
JP2003023150A (ja) 2001-07-10 2003-01-24 Sony Corp トレンチゲート型半導体装置及びその作製方法
KR100398955B1 (ko) 2001-08-02 2003-09-19 삼성전자주식회사 이이피롬 메모리 셀 및 형성 방법
DE10139827A1 (de) 2001-08-14 2003-03-13 Infineon Technologies Ag Speicherzelle mit Grabenkondensator und vertikalem Auswahltransistor und einem zwischen diesen geformten ringförmigen Kontaktierungsbereich
US6800899B2 (en) 2001-08-30 2004-10-05 Micron Technology, Inc. Vertical transistors, electrical devices containing a vertical transistor, and computer systems containing a vertical transistor
KR100431656B1 (ko) 2001-09-11 2004-05-17 삼성전자주식회사 반도체 장치의 제조 방법
JP2003092367A (ja) 2001-09-19 2003-03-28 Oki Electric Ind Co Ltd 半導体素子の製造方法
US6825093B2 (en) 2001-09-28 2004-11-30 Infineon Technologies Ag Process window enhancement for deep trench spacer conservation
KR100400323B1 (ko) 2001-11-01 2003-10-01 주식회사 하이닉스반도체 반도체 소자의 시모스(ｃｍｏｓ) 및 그의 제조 방법
KR100436287B1 (ko) 2001-11-17 2004-06-16 주식회사 하이닉스반도체 반도체 소자의 트랜지스터 및 그 제조 방법
US6724028B2 (en) 2001-12-10 2004-04-20 Hans Gude Gudesen Matrix-addressable array of integrated transistor/memory structures
US6630720B1 (en) 2001-12-26 2003-10-07 Advanced Micro Devices, Inc. Asymmetric semiconductor device having dual work function gate and method of fabrication
US6563183B1 (en) 2001-12-31 2003-05-13 Advanced Micro Devices, Inc. Gate array with multiple dielectric properties and method for forming same
US6858500B2 (en) 2002-01-16 2005-02-22 Fuji Electric Co., Ltd. Semiconductor device and its manufacturing method
US6656748B2 (en) 2002-01-31 2003-12-02 Texas Instruments Incorporated FeRAM capacitor post stack etch clean/repair
DE10208249B4 (de) 2002-02-26 2006-09-14 Infineon Technologies Ag Halbleiterspeicher mit vertikalem Auswahltransistor
US6515325B1 (en) 2002-03-06 2003-02-04 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same
US6661042B2 (en) * 2002-03-11 2003-12-09 Monolithic System Technology, Inc. One-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
US6586808B1 (en) 2002-06-06 2003-07-01 Advanced Micro Devices, Inc. Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric
AU2003247513A1 (en) 2002-06-10 2003-12-22 Amberwave Systems Corporation Growing source and drain elements by selecive epitaxy
DE10226583B4 (de) 2002-06-14 2010-07-08 Qimonda Ag DRAM-Speicherzelle für schnellen Schreib-/Lesezugriff und Speicherzellenfeld
US6756625B2 (en) 2002-06-21 2004-06-29 Micron Technology, Inc. Memory cell and method for forming the same
US7221596B2 (en) 2002-07-05 2007-05-22 Impinj, Inc. pFET nonvolatile memory
JP3934507B2 (ja) 2002-08-08 2007-06-20 株式会社東芝 半導体記憶装置および半導体記憶装置の製造方法
US7071043B2 (en) 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6914289B2 (en) 2002-08-15 2005-07-05 Intel Corporation Hourglass ram
US20040034587A1 (en) 2002-08-19 2004-02-19 Amberson Matthew Gilbert System and method for calculating intra-period volatility
US6838723B2 (en) 2002-08-29 2005-01-04 Micron Technology, Inc. Merged MOS-bipolar capacitor memory cell
US6818947B2 (en) 2002-09-19 2004-11-16 Fairchild Semiconductor Corporation Buried gate-field termination structure
US6645869B1 (en) 2002-09-26 2003-11-11 Vanguard International Semiconductor Corporation Etching back process to improve topographic planarization of a polysilicon layer
US7033891B2 (en) 2002-10-03 2006-04-25 Fairchild Semiconductor Corporation Trench gate laterally diffused MOSFET devices and methods for making such devices
US6753228B2 (en) 2002-10-15 2004-06-22 Semiconductor Components Industries, L.L.C. Method of forming a low resistance semiconductor device and structure therefor
TW588413B (en) 2002-11-07 2004-05-21 Winbond Electronics Corp Manufacturing method and device of memory with different depths of isolation trench
US6861689B2 (en) * 2002-11-08 2005-03-01 Freescale Semiconductor, Inc. One transistor DRAM cell structure and method for forming
KR100481867B1 (ko) 2002-11-11 2005-04-11 삼성전자주식회사 강유전체 커패시터 및 그 제조 방법
US6645818B1 (en) 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
US7250650B2 (en) 2002-11-21 2007-07-31 Infineon Technologies Ag Field-effect transistor structure and associated semiconductor memory cell
US7030436B2 (en) 2002-12-04 2006-04-18 Micron Technology, Inc. Embedded DRAM gain memory cell having MOS transistor body provided with a bi-polar transistor charge injecting means
KR100521369B1 (ko) 2002-12-18 2005-10-12 삼성전자주식회사 고속도 및 저전력 소모 반도체 소자 및 그 제조 방법
TW574746B (en) 2002-12-19 2004-02-01 Taiwan Semiconductor Mfg Method for manufacturing MOSFET with recessed channel
TWI231042B (en) 2002-12-27 2005-04-11 Wintek Corp Method and device to promote the yield rate and uniformity of AMOLED panel
KR20040061967A (ko) 2002-12-31 2004-07-07 동부전자 주식회사 반도체 소자의 제조방법
TW578274B (en) 2003-01-17 2004-03-01 Nanya Technology Corp Vertical flash memory cell with tip-shape floating gate and method therefor
JP4502173B2 (ja) 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2004247656A (ja) 2003-02-17 2004-09-02 Renesas Technology Corp 半導体装置及びその製造方法
US6956256B2 (en) 2003-03-04 2005-10-18 Micron Technology Inc. Vertical gain cell
JP2004281736A (ja) 2003-03-17 2004-10-07 Nec Electronics Corp 半導体記憶装置
TW578328B (en) 2003-03-28 2004-03-01 Gemtek Technology Co Ltd Dual-frequency inverted-F antenna
KR100480645B1 (ko) * 2003-04-01 2005-03-31 삼성전자주식회사 역자기 정합 방식을 이용한 트윈―ｏｎｏ 형태의ｓｏｎｏｓ 메모리 소자 제조 방법
US6720232B1 (en) 2003-04-10 2004-04-13 Taiwan Semiconductor Manufacturing Company Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
TW587338B (en) 2003-05-06 2004-05-11 Mosel Vitelic Inc Stop structure of trench type DMOS device and its formation method
JP3913709B2 (ja) 2003-05-09 2007-05-09 株式会社東芝 半導体記憶装置
JP2004335031A (ja) 2003-05-09 2004-11-25 Toshiba Corp 半導体記憶装置
KR100568854B1 (ko) 2003-06-17 2006-04-10 삼성전자주식회사 반도체 메모리에서의 리세스 채널을 갖는 트랜지스터 형성방법
US7105406B2 (en) 2003-06-20 2006-09-12 Sandisk Corporation Self aligned non-volatile memory cell and process for fabrication
US6818515B1 (en) 2003-06-23 2004-11-16 Promos Technologies Inc. Method for fabricating semiconductor device with loop line pattern structure
KR100521381B1 (ko) 2003-06-25 2005-10-12 삼성전자주식회사 모오스 전계 효과 트랜지스터의 제조 방법
KR100511045B1 (ko) 2003-07-14 2005-08-30 삼성전자주식회사 리세스된 게이트 전극을 갖는 반도체 소자의 집적방법
US7335934B2 (en) 2003-07-22 2008-02-26 Innovative Silicon S.A. Integrated circuit device, and method of fabricating same
US7326619B2 (en) 2003-08-20 2008-02-05 Samsung Electronics Co., Ltd. Method of manufacturing integrated circuit device including recessed channel transistor
US6784069B1 (en) 2003-08-29 2004-08-31 Micron Technology, Inc. Permeable capacitor electrode
US7067385B2 (en) 2003-09-04 2006-06-27 Micron Technology, Inc. Support for vertically oriented capacitors during the formation of a semiconductor device
US7125781B2 (en) 2003-09-04 2006-10-24 Micron Technology, Inc. Methods of forming capacitor devices
KR100546378B1 (ko) 2003-09-09 2006-01-26 삼성전자주식회사 리세스 채널을 가지는 트랜지스터 제조 방법
US6844591B1 (en) 2003-09-17 2005-01-18 Micron Technology, Inc. Method of forming DRAM access transistors
JP2005093808A (ja) 2003-09-18 2005-04-07 Fujio Masuoka メモリセルユニット、それを備えてなる不揮発性半導体記憶装置及びメモリセルアレイの駆動方法
US7184298B2 (en) 2003-09-24 2007-02-27 Innovative Silicon S.A. Low power programming technique for a floating body memory transistor, memory cell, and memory array
US7468311B2 (en) 2003-09-30 2008-12-23 Tokyo Electron Limited Deposition of silicon-containing films from hexachlorodisilane
JP2005142203A (ja) 2003-11-04 2005-06-02 Elpida Memory Inc 半導体装置およびその製造方法
US20050104156A1 (en) 2003-11-13 2005-05-19 Texas Instruments Incorporated Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes
KR100521383B1 (ko) 2003-11-17 2005-10-12 삼성전자주식회사 소자분리막 상에 형성된 소오스/드레인을 갖는 반도체소자 및 그 제조방법
JP2005175090A (ja) * 2003-12-09 2005-06-30 Toshiba Corp 半導体メモリ装置及びその製造方法
KR100518606B1 (ko) 2003-12-19 2005-10-04 삼성전자주식회사 실리콘 기판과 식각 선택비가 큰 마스크층을 이용한리세스 채널 어레이 트랜지스터의 제조 방법
US6974743B2 (en) 2004-02-02 2005-12-13 Infineon Technologies Ag Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates
JP4342970B2 (ja) 2004-02-02 2009-10-14 株式会社東芝 半導体メモリ装置及びその製造方法
KR100540371B1 (ko) 2004-03-02 2006-01-11 이태복 고 내압용 반도체 소자 및 그 제조방법
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
KR100614240B1 (ko) 2004-06-10 2006-08-18 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 형성방법
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7160788B2 (en) 2004-08-23 2007-01-09 Micron Technology, Inc. Methods of forming integrated circuits
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7202127B2 (en) 2004-08-27 2007-04-10 Micron Technology, Inc. Methods of forming a plurality of capacitors
US7151040B2 (en) 2004-08-31 2006-12-19 Micron Technology, Inc. Methods for increasing photo alignment margins
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7285812B2 (en) 2004-09-02 2007-10-23 Micron Technology, Inc. Vertical transistors
US7115525B2 (en) 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7655387B2 (en) 2004-09-02 2010-02-02 Micron Technology, Inc. Method to align mask patterns
JP4083160B2 (ja) 2004-10-04 2008-04-30 株式会社東芝 半導体記憶装置およびｆｂｃメモリセルの駆動方法
US20060108667A1 (en) 2004-11-22 2006-05-25 Macronix International Co., Ltd. Method for manufacturing a small pin on integrated circuits or other devices
US20060113588A1 (en) 2004-11-29 2006-06-01 Sillicon-Based Technology Corp. Self-aligned trench-type DMOS transistor structure and its manufacturing methods
KR100640616B1 (ko) 2004-12-21 2006-11-01 삼성전자주식회사 매몰 게이트 패턴을 포함하는 전계 효과 트랜지스터구조물 및 그것을 포함하는 반도체 소자의 제조방법
US20060167741A1 (en) 2005-01-25 2006-07-27 Cisco Technology, Inc. System and method for designing a supply chain
JP2006234780A (ja) 2005-01-25 2006-09-07 Fujitsu Component Ltd 評価基板及びケーブルアッセンブリ評価方法
DE102005008478B3 (de) 2005-02-24 2006-10-26 Infineon Technologies Ag Verfahren zur Herstellung von sublithographischen Strukturen
JP2006237455A (ja) 2005-02-28 2006-09-07 Toshiba Corp 半導体装置とその製造方法
US7244659B2 (en) 2005-03-10 2007-07-17 Micron Technology, Inc. Integrated circuits and methods of forming a field effect transistor
US7390746B2 (en) 2005-03-15 2008-06-24 Micron Technology, Inc. Multiple deposition for integration of spacers in pitch multiplication process
US7253118B2 (en) 2005-03-15 2007-08-07 Micron Technology, Inc. Pitch reduced patterns relative to photolithography features
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7611944B2 (en) 2005-03-28 2009-11-03 Micron Technology, Inc. Integrated circuit fabrication
JP4541220B2 (ja) 2005-04-13 2010-09-08 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
US7214621B2 (en) 2005-05-18 2007-05-08 Micron Technology, Inc. Methods of forming devices associated with semiconductor constructions
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7560390B2 (en) 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
US7396781B2 (en) 2005-06-09 2008-07-08 Micron Technology, Inc. Method and apparatus for adjusting feature size and position
US7176084B2 (en) * 2005-06-09 2007-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
JP2006352005A (ja) 2005-06-20 2006-12-28 Toshiba Corp 強誘電体記憶装置およびその製造方法
US7517741B2 (en) * 2005-06-30 2009-04-14 Freescale Semiconductor, Inc. Single transistor memory cell with reduced recombination rates
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7413981B2 (en) 2005-07-29 2008-08-19 Micron Technology, Inc. Pitch doubled circuit layout
US7199005B2 (en) 2005-08-02 2007-04-03 Micron Technology, Inc. Methods of forming pluralities of capacitors
DE102005040133A1 (de) 2005-08-03 2007-02-08 Amazonen-Werke H. Dreyer Gmbh & Co. Kg Grubber
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7696567B2 (en) 2005-08-31 2010-04-13 Micron Technology, Inc Semiconductor memory device
US7687342B2 (en) 2005-09-01 2010-03-30 Micron Technology, Inc. Method of manufacturing a memory device
US7867845B2 (en) 2005-09-01 2011-01-11 Micron Technology, Inc. Transistor gate forming methods and transistor structures
US7393789B2 (en) 2005-09-01 2008-07-01 Micron Technology, Inc. Protective coating for planarization
JP4773182B2 (ja) 2005-10-28 2011-09-14 エルピーダメモリ株式会社 半導体装置の製造方法
US7350441B2 (en) 2005-11-15 2008-04-01 3M Innovative Properties Company Cutting tool having variable movement at two simultaneously independent speeds in an x-direction into a work piece for making microstructures
KR100843139B1 (ko) 2005-12-15 2008-07-02 삼성전자주식회사 오픈 비트 라인 구조를 갖는 멀티레벨 동적 메모리 장치 및그 구동 방법
US7495294B2 (en) 2005-12-21 2009-02-24 Sandisk Corporation Flash devices with shared word lines
TWI293207B (en) 2006-01-11 2008-02-01 Promos Technologies Inc Dynamic random access memory structure and method for preparing the smae
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7476933B2 (en) 2006-03-02 2009-01-13 Micron Technology, Inc. Vertical gated access transistor
US7495946B2 (en) 2006-03-02 2009-02-24 Infineon Technologies Ag Phase change memory fabricated using self-aligned processing
US7349232B2 (en) 2006-03-15 2008-03-25 Micron Technology, Inc. 6F2 DRAM cell design with 3F-pitch folded digitline sense amplifier
US7351666B2 (en) 2006-03-17 2008-04-01 International Business Machines Corporation Layout and process to contact sub-lithographic structures
US7902074B2 (en) 2006-04-07 2011-03-08 Micron Technology, Inc. Simplified pitch doubling process flow
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7488685B2 (en) 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
JP2008004738A (ja) 2006-06-22 2008-01-10 Elpida Memory Inc 半導体装置及びその製造方法
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7755132B2 (en) 2006-08-16 2010-07-13 Sandisk Corporation Nonvolatile memories with shaped floating gates
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7732275B2 (en) 2007-03-29 2010-06-08 Sandisk Corporation Methods of forming NAND flash memory with fixed charge
US7495282B2 (en) 2007-01-12 2009-02-24 Sandisk Corporation NAND memory with virtual channel
US7619311B2 (en) 2007-02-02 2009-11-17 Macronix International Co., Ltd. Memory cell device with coplanar electrode surface and method
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8563229B2 (en) 2007-07-31 2013-10-22 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures
US7684245B2 (en) 2007-10-30 2010-03-23 Atmel Corporation Non-volatile memory array architecture with joined word lines
KR101374323B1 (ko) 2008-01-07 2014-03-17 삼성전자주식회사 반도체 소자 및 그 제조방법
US7759193B2 (en) 2008-07-09 2010-07-20 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8859367B2 (en) 2010-07-09 2014-10-14 Micron Technology, Inc. Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices

Also Published As

Publication number Publication date
WO2008010891A2 (en) 2008-01-24
US20080012056A1 (en) 2008-01-17
JP5181304B2 (ja) 2013-04-10
US9129847B2 (en) 2015-09-08
JP2009544166A (ja) 2009-12-10
US8551823B2 (en) 2013-10-08
EP2772942A2 (en) 2014-09-03
KR101149666B1 (ko) 2012-05-31
KR20090023496A (ko) 2009-03-04
EP2041796A2 (en) 2009-04-01
US20140021550A1 (en) 2014-01-23
US20090239343A1 (en) 2009-09-24
WO2008010891A3 (en) 2008-07-24
CN101479852B (zh) 2012-06-13
US7602001B2 (en) 2009-10-13
EP2772942A3 (en) 2014-12-31
TWI356471B (en) 2012-01-11
TW200818406A (en) 2008-04-16
SG173381A1 (en) 2011-08-29

Similar Documents

Publication Publication Date Title
CN101479852B (zh) 无电容器单晶体管浮体动态随机存取存储器单元及其形成方法
US6686624B2 (en) Vertical one-transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
EP0241948B1 (en) Semiconductor memory and method for fabricating the same
US4801988A (en) Semiconductor trench capacitor cell with merged isolation and node trench construction
KR100415973B1 (ko) Dram셀장치및그제조방법
US6077745A (en) Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
CN100511648C (zh) 用于形成半导体器件的方法
US6437401B1 (en) Structure and method for improved isolation in trench storage cells
US20070045697A1 (en) Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures
EP0713253B1 (en) Manufacturing method for a trench capacitor DRAM cell
KR20020083941A (ko) 반도체 장치
EP0366882A3 (en) An ultra dense DRAM cell array and its method of fabrication
KR960043226A (ko) 디램 셀(dram) 및 그 제조 방법
US5034787A (en) Structure and fabrication method for a double trench memory cell device
US7132751B2 (en) Memory cell using silicon carbide
KR20100051355A (ko) 커패시터 없는 디램 소자
US7642588B2 (en) Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same
JPH0640573B2 (ja) 半導体集積回路装置
JP3798659B2 (ja) メモリ集積回路
US8022499B2 (en) Semiconductor memory device including cell isolation structure using inactive transistors
CN113540088B (zh) 存储器结构及存储器结构的形成方法
US7320912B2 (en) Trench capacitors with buried isolation layer formed by an oxidation process and methods for manufacturing the same
US8349719B2 (en) Semiconductor device and method for fabricating the same
JPH0691216B2 (ja) 半導体記憶装置
Kubota et al. A new soft-error immune DRAM cell with a transistor on a lateral epitaxial silicon layer (TOLE cell)

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant