CN101496176A - 在cmosfet中最优化应变的结构与方法 - Google Patents

在cmosfet中最优化应变的结构与方法 Download PDF

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CN101496176A
CN101496176A CN200680002466.9A CN200680002466A CN101496176A CN 101496176 A CN101496176 A CN 101496176A CN 200680002466 A CN200680002466 A CN 200680002466A CN 101496176 A CN101496176 A CN 101496176A
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陈向东
杨海宁
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International Business Machines Corp
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Abstract

本发明公开了一种包括PMOSFET和NMOSFET的应变MOSFET半导体结构，以及用于制造应变MOSFET的方法，该方法最优化MOSFET中的应变，更具体地说，最大化在一类(P或N)MOSFET中的应变并且最小化并驰豫在另一类(N或P)MOSFET中的应变。在所述PMOSFET和所述NMOSFET两者上形成具有初始全厚度的应变引起CA氮化物覆层，其中应变引起覆层在一类半导体器件中产生最优化的全应变并且降低另一类半导体器件的性能。蚀刻应变引起CA氮化物覆层，以减小在另一类半导体器件上的厚度，其中，应变引起覆层的减小厚度在另一MOSFET中驰豫并产生较小的应变。

Description

在CMOSFET中最优化应变的结构与方法
技术领域
本发明通常涉及应变互补金属氧化物半导体场效应晶体管(CMOSFET)的半导体结构以及用于制造在MOSFET中最优化应变的应变CMOSFET的方法，更具体地说，涉及最大化MOSFET的一种类型/种类(N或P)中的应变和最小化并且驰豫MOSFET的另一种类型/种类(P或N)中的应变的结构和方法。
背景技术
因为应变可以提高MOSFET沟道中的载流子迁移率，所以最近引起应变的工艺吸引了大量的注意力。在向MOSFET的沟道中传递应变时，接触阻挡(CA)氮化物应力工程特别有效。另外，该工艺与现有制造工艺兼容并且可以在现有制造工艺中容易地执行。MOSFET的沟道中的应变与接触阻挡(CA)氮化物的厚度成比例，在MOSFET沟道中较厚的接触阻挡氮化物引起较高的应力。压缩CA氮化物或者拉伸CA氮化物可以提高一类MOSFET的性能并且降低另一类MOSFET的性能。更具体地说，压缩CA氮化物提高PMOSFET的性能同时降低NMOSFET的性能，而拉伸CA氮化物提高NMOSFET的性能同时降低PMOSFET的性能。如技术上公知的，可以通过改变等离子体沉积功率选择性沉积压缩氮化物膜或者拉伸氮化物膜。
执行掩蔽(阻挡PFET或者阻挡NFET)Ge或者As注入以驰豫一类(N或者P)MOSFET中的应力，从而减少性能降低，同时保留另一类(P或者N)MOSFET中的应变。厚CA氮化物可以在一类(N或者P)MOSFET的沟道中引起更高的应力。但是厚CA氮化物使得用Ge或者As的注入驰豫应力以提高另一类(P或者N)MOSFET的性能的变得困难。
发明内容
本发明提供了一种结构和方法，以在诸如CMOSFET的半导体器件中最优化应变并且广泛应用于常用半导体器件。本发明提供包括PMOSFET和NMOSFET两者的应变半导体结构以及用于制造应变MOSFET的制造方法，该方法最大化一种类型/种类(N或P)MOSFET的应变同时最小化和驰豫另一种类型/种类(N或P)MOSFET中的应变。
在所述PMOSFET和所述NMOSFET的其中之一上形成具有初始全厚度的应变引起CA氮化物覆层，其中应变引起覆层在一种半导体器件中产生最优化全应变。在PMOSFET和NMOSFET的另一个上形成具有小于全厚度的蚀刻减小的厚度的应变引起CA氮化物覆层，其中，应变引起覆层减小的厚度在另一个MOSFET中驰豫并产生较小的应变。
附图说明
通过参考随后联系附图对其几个实施例的详细描述，本领域的技术人员可以更容易地理解用于在MOSFET中最优化应变的结构和方法的本发明的前述方面和优点，在所有附图中，相似的元件用相似的标号标记，其中：
图1示出了MOSFET结构，其在PMOSFET上具有最大化PMOSFET中的应变的CA压缩氮化物的较大厚度并且在NMOSFET上具有最小化并驰豫NMOSFET中的应变的CA拉伸氮化物的较小厚度。
图2示出了MOSFET结构，其在NMOSFET上具有最大化NMOSFET中的应变的CA拉伸氮化物的较大厚度并且在PMOSFET上具有最小化并驰豫PMOSFET中的应变的CA拉伸氮化物的较小厚度。
具体实施方式
本发明提供了在NMOSFET和PMOSFET上具有不同厚度的接触阻挡(CA)氮化物，其用来最大化一种类型/种类(P或N)MOSFET的应变并且最小化和驰豫另一种类型/种类(N或P)MOSFET的应变，的MOSFET结构。
图1示出了在具有被隔离区域34分开的PMOSFET 30和NMOSFET32两者的半导体晶片之上的本发明的第一和第二代表性实施例。在本发明的第一和第二代表性实施例中，压缩CA氮化物被用来最大化PMOSFET30中的应变以及最小化并驰豫NMOSFET 32中的应变。
总之，在PMOSFET 30和NMOSFET 32两者上沉积厚
Figure A20068000246600071
压缩CA氮化物36后，用光致抗蚀剂构图晶片以便用光致抗蚀剂覆盖PMOSFET 30并且暴露NMOSFET 32并且没有用光致抗蚀剂覆盖NMOSFET 32。NMOSFET 32处的CA氮化物在38处被蚀刻到更薄同时光致抗蚀剂保护PMOSFET 30不被蚀刻。因此，NMOSFET 32处更薄的CA氮化物38导致在NMOSFET 32处的压缩应变低于PMOSFET 30处的压缩应变，并且减少了NMOSFET 32的性能降低。
图1还示出可以应用Ge或者As注入40以进一步驰豫应变并提高NMOSFET 32的性能。
在第一步中，在晶片上的PMOSFET 30和NMOSFET 32两者之上沉积压缩CA氮化物36的厚
Figure A20068000246600073
层。
然后，在晶片上沉积光致抗蚀剂的覆盖层，通过使用掩模构图光致抗蚀剂以便用光致抗蚀剂覆盖PMOSFET 30，同时NMOSFET 32保持暴露并且没有用光致抗蚀剂覆盖NMOSFET 32。
然后蚀刻NMOSFET 32处的CA氮化物，在38处薄到
Figure A20068000246600074
同时光致抗蚀剂保护PMOSFET 30处的CA氮化物不被蚀刻，以便PMOSFET 30顶上的CA氮化物36保持全沉积厚度。因此，NMOSFET 32顶上的38处更薄的CA氮化物导致在NMOSFET 32处的压缩应变低于PMOSFET 30处的压缩应变，并且减少由压缩CA氮化物引起的NMOSFET 32的性能降低。
随着以上步骤的完成，完成了本发明的第一实施例。图1还示出了第二实施例，其中在完成以上步骤后，通过在40处将Ge或者As注入到NMOSFET 32中，进一步减少了NMOSFET 32的性能降低。当PMOSFET30被掩模阻挡时执行注入40，(图中通过+B(阻挡)P(PFET)Ge/As注入40表明)，该掩模与构图光致抗蚀剂的掩模是同一个，以进一步驰豫应变并且提高NMOSFET 32的性能。
图2示出了本发明的第三和第四代表性实施例，其说明图1中的相同的结构和方法可以应用于拉伸CA氮化物。总之，在PMOSFET 30和NMOSFET 32两者之上沉积厚
Figure A20068000246600081
拉伸CA氮化物42后，用光致抗蚀剂构图晶片以便用光致抗蚀剂覆盖NMOSFET 32，同时PMOSFET30保持暴露并且没有用光致抗蚀剂覆盖PMOSFET 30。PMOSFET 30处的CA氮化物在44处被蚀刻减薄到
Figure A20068000246600082
同时光致抗蚀剂保护NMOSFET 32不被蚀刻。因此，PMOSFET 30处的薄CA氮化物44导致在PMOSFET 30处的压缩应变低于NMOSFET 32处的压缩应变，并且减少了PMOSFET 30的性能降低。图2还示出了在46处可以应用Ge或者As注入以进一步驰豫应变并且提高PMOSFET 30的性能。
在第一步中，在晶片上的PMOSFET 30和NMOSFET 32两者之上沉积拉伸CA氮化物42的厚
Figure A20068000246600083
层。
然后，通过使用掩模用光致抗蚀剂构图晶片，以便用光致抗蚀剂覆盖NMOSFET 32并且PMOSFET 30保持暴露而没有用光致抗蚀剂覆盖PMOSFET 30。
然后，PMOSFET 30处的CA氮化物在44处被蚀刻减薄到
Figure A20068000246600084
同时光致抗蚀剂保护NMOSFET 32处的CA氮化物42不被蚀刻，以便CA氮化物36保持在初始全厚度。因此，PMOSFET 30处的薄CA氮化物44导致在PMOSFET 30处的拉伸应变低于NMOSFET 32处的拉伸应变，并且减少由拉伸CA氮化物引起的PMOSFET 30的性能降低。
随着以上步骤的完成，完成了本发明的第三实施例。图2还示出了第四实施例，其中，在完成以上步骤之后，通过在46处向PMOSFET 30注入Ge或者As，进一步减小了PMOSFET 30的性能降低。当NMOSFET 32被掩模阻挡时执行注入46，(图中通过+B(阻挡)P(PFET)Ge/As注入表明)，该掩模与构图光致抗蚀剂的掩模可以是同一个，以进一步驰豫应变并且提高PMOSFET 30的性能。
用于在氮化物膜中驰豫应变的注入工艺条件可以是：
As或者Ge
剂量：5e14到2e15
能量：20K到50K
精确的注入条件依赖于膜的厚度和膜中的应力。
如技术上公知的，可以通过改变等离子体沉积的功率，选择性沉积压缩氮化物膜或者拉伸氮化物膜。
在可选实施例中，其它的应力材料可以用在本发明中代替氮化物膜，但是氮化物膜在一致性上具有优势。本发明的应力引起膜可以包括优选Si3N4或者TiN的氮化物、氧化物、诸如硼磷硅酸盐玻璃、Al2O3、HfO2、ZrO2、HfSiO的掺杂氧化物和对半导体工艺较普通的其它介质材料或者其任意组合。应力引起膜的厚度范围从大约10nm到大约100nm。应力引起膜在器件沟道中提供压缩应力以提高pFET的性能或者在器件沟道中提供拉伸应力以提高nFET的性能。
附图示出了在单个半导体衬底上形成的具有两个MOSFET器件区域的IC结构10。虽然对这样的实施例进行了说明，但是本发明不限制在半导体结构的表面上形成的MOSFET器件的任何具体数量。
在制造工艺的更详细说明中，IC结构10包括半导体衬底12、位于半导体衬底12中的源极/漏极区域14、位于半导体衬底12的表面上的左右两个栅极区域16L和16R。栅极区域16L和16R的每一个都包括栅极介质18、多晶硅导体20、介质覆层22、介质衬里23、隔离物24和位于半导体衬底12中的源极/漏极区域14。
结构10的半导体衬底12可以包括任意半导体材料，该半导体材料包括但不限于：Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP和所有其它III/V族化合物半导体。半导体衬底12还可以包括有机半导体或者诸如Si/SiGe、绝缘体上硅(SOI)或者绝缘体上SiGe(SGOI)的分层半导体。在本发明的一些实施例中，优选半导体衬底12由含硅半导体材料，即包括硅元素的半导体材料构成。半导体衬底12可以掺杂、未掺杂、或者其中包括掺杂和未掺杂区域。
半导体衬底12还包括第一掺杂(n-或p-)区域和第二掺杂(n-或p-)区域。这些掺杂区域公知为“阱”。第一掺杂区域和第二掺杂区域可以相同，或者它们可以具有不同的导电率和/或掺杂浓度。
优选利用本领域的技术人员公知的常规工艺，在本发明此处的在半导体衬底中已经形成沟槽隔离区域34。沟槽隔离区域位于本发明的附图所示的区域的左右外围以及两个栅极区域之间。
如果存在介质并且如果其为沉积介质，则在包括半导体衬底12的结构10的整个表面上和隔离区域顶上形成栅极介质18。通过诸如氧化、氮化、氧氮化的热生长工艺形成栅极介质18。可选地，可以利用如化学气相沉积(CVD)、等离子体辅助CVD、原子层沉积(ALD)、蒸镀、反应溅射、化学溶液沉积以及其它类似沉积工艺的沉积工艺形成栅极介质18。还可以利用以上工艺的任意组合形成栅极介质18。
栅极介质18由绝缘材料构成，该绝缘材料包括但不限于氧化物、氮化物、氧氮化物和/或包括金属硅酸盐和氮化金属硅酸盐的硅酸盐。在一个实施例中，优选栅极介质18由诸如SiO2、HfO2、ZrO2、Al2O3、TiO2、La2O3、SrTiO3、LaAlO3及其混合的氧化物构成。
栅极介质18的物理厚度可以改变，但优选栅极介质18具有从大约0.5到大约10nm的厚度，更优选具有从大约0.5到大约3nm的厚度。
栅极介质18形成之后，利用诸如物理气相沉积、CVD或者蒸镀的公知的沉积工艺，在栅极介质18之上形成图中所示的变为多晶硅栅极导体20的多晶硅(即多晶Si)覆层。多晶硅覆层可以掺杂或未掺杂。如果掺杂，可以在形成掺杂多晶硅覆层时使用原位掺杂沉积工艺。可选地，可以通过沉积、离子注入和退火形成掺杂多晶硅层。多晶硅层的掺杂将改变形成的金属硅化物栅极的功函数。掺杂剂离子的示意性实例包括As、P、B、Sb、Bi、In、Al、Ga、Tl或其混合。优选离子注入的剂量为1E14(＝1×1014)到1E16(＝1×1016)原子/cm2，或者更优选离子注入的剂量为1E15到5E15原子/cm2。本发明此处沉积的多晶硅层的厚度即高度可以依赖于所使用的沉积工艺改变。优选，多晶硅层具有从大约20到大约180nm的垂直厚度，更优选具有从大约40到大约150nm的厚度。
在沉积多晶硅覆层之后，利用诸如物理气相沉积或者化学气相沉积的沉积工艺在多晶硅栅极导体20的覆层之上形成介质覆层22。介质覆层22可以是氧化物、氮化物、氧氮化物或其任意组合。介质覆层22可以包括将在下面详细限定的不同于隔离物24的介质材料。在一个实施例中，诸如Si3N4的氮化物被用作介质覆层22。而在优选的另一个实施例中，介质覆层22为诸如SiO2的氧化物。介质覆层22的厚度即高度从大约20到大约180nm，更优选具有从大约30到大约140nm的厚度。
然后利用光刻和蚀刻构图覆盖多晶硅层和介质覆层以提供构图栅极叠层。构图栅极叠层可以具有相同的尺寸即长度，或者它们可以具有不同的尺寸以提高器件性能。本发明此处的每一个构图栅极叠层都包括多晶硅栅极导体20和介质覆层22。光刻步骤包括向介质覆层的上表面施加光致抗蚀剂，在期望的辐射图形中曝光光致抗蚀剂并且利用常规抗蚀剂显影剂显影曝光的光致抗蚀剂。然后利用一个或者多个干蚀刻步骤，将光致抗蚀剂中的图形转移到介质覆层和多晶硅覆盖层。在一些实施例中，在图形转移到介质覆层之后可以除去构图的光致抗蚀剂。在其它实施例中，在完成蚀刻之后，除去构图的光致抗蚀剂。
可以用于在本发明中形成构图栅极叠层的合适的干蚀刻工艺包括但不限于：反应离子蚀刻、离子束蚀刻、等离子体蚀刻或者激光烧蚀。优选所用的干蚀刻工艺对下面的栅极介质18具有选择性，因此这个蚀刻步骤没有典型地除去栅极介质。然而，在一些实施例中，此蚀刻步骤可以用来除去栅极介质18没有被栅极叠层保护的部分。也可以使用湿蚀刻工艺除去栅极介质18没有被栅极叠层保护的部分。
下一步，在所有含硅的暴露表面上，包括至少多晶硅栅极导体20上，形成介质衬里23。介质衬里23还可以延伸到半导体衬底12的水平表面上。介质衬里23可以包括任意介质材料，包含氧化物、氮化物、氧氮化物或其任意组合。通过诸如氧化、氮化、氮氧化的热生长工艺形成介质衬里23。介质衬里23为厚度优选从大约1到大约10nm的薄层。
在每个构图栅极叠层的暴露侧壁上以及介质衬里的顶部形成至少一个隔离物24。至少一个隔离物24由如氧化物，氮化物，氧氮化物和/或其任意组合的绝缘体构成，并且优选由不同于介质衬里23和介质覆层22的材料构成。优选形成氮化物隔离物。通过沉积和蚀刻形成至少一个隔离物24。注意，用来形成隔离物24的蚀刻步骤还可以从衬底顶部除去介质衬里23，以便暴露半导体衬底12的一部分。
隔离物24的宽度必须足够宽以便源极和漏极硅化物接触(随后形成)不会侵入到栅极叠层的边缘下面。典型地，从底部测量，当隔离物具有从大约15到大约80nm的宽度时，源极/漏极硅化物不会侵入到栅极叠层的边缘下面。
隔离物形成之后，在衬底12的暴露部分中形成源极/漏极扩散区域14。利用离子注入和退火步骤形成源极/漏极扩散区域14。退火步骤用于激活通过前面的注入步骤注入的掺杂剂。本领域的技术人员已公知用于离子注入和退火的条件。
下一步，如图1和2所示，在图1和2所示的整个结构上形成厚压缩或者拉伸CA氮化物膜30或者42并且进行如上面详细描述的进一步的制造和处理以形成薄压缩或者拉伸CA氮化物膜36或44以及可能地Ge/As注入40或46.
在制造图1和2所示结构之后，可以形成平整化介质层(未示出)。平整化介质层包括诸如高密度氧化物或者从TEOS沉积的氧化物的氧化物。可选地，平整化介质层可以包括诸如硼掺杂硅酸盐玻璃(BSG)、磷掺杂硅酸盐玻璃(PSG)的掺杂硅酸盐玻璃，诸如氢倍半硅氧烷(HSQ)的旋涂聚合物材料，或光致抗蚀剂。通过本领域的技术人员公知的常规技术形成平整化介质层。在此处形成的平整化介质层的厚度可以依赖于所用材料的类型改变。优选平整化介质层具有从大约50到大约100nm的厚度。
虽然这里详细描述了用于最优化CMOSFET中的应变的结构和方法的本发明的几个实施例和变化，但是应该明白，对本领域的技术人员，本发明的公开和教导旨在多种可选设计。

Claims (18)

1.一种制造具有p型半导体器件和n型半导体器件的半导体结构的方法，所述p型半导体器件和n型半导体器件中具有不同的应变量，所述方法包括如下步骤：
在衬底上形成p型半导体器件和n型半导体器件；
在所述p型半导体器件和所述n型半导体器件上形成具有初始厚度的应变引起覆层，其中所述应变引起覆层在所述p型半导体器件和所述n型半导体器件中产生应变；
保护应变引起覆层覆盖的p型半导体器件和n型半导体器件的一个，而另一个应变引起覆层覆盖的半导体器件保持暴露；
蚀刻所述暴露的应变引起覆层以减少应变引起覆层的厚度，从而驰豫在所述暴露的半导体器件中的应变，而被保护的半导体器件上的应变引起覆层仍被保护，以便所述被保护的半导体器件中的所述应变保持不变。
2.根据权利1的方法，其中在蚀刻之后，向暴露的半导体器件中注入应变减小掺杂剂以进一步驰豫在所述暴露的半导体器件中的应变。
3.根据权利要求2的方法，包括注入包括As或者Ge的应变减小掺杂剂。
4.根据权利要求3的方法，包括以大约5e14原子/cm2到大约2e15原子/cm2的剂量，以大约20KeV到大约50KeV的注入能量注入As或者Ge。
5.根据权利要求1的方法，其中所述保护步骤包括：
在所述衬底上的所述p型半导体器件和所述n型半导体器件上覆盖沉积光致抗蚀剂层；
将所述光致抗蚀剂层暴露于辐射图形并且将所述图形显影到所述光致抗蚀剂层中，以在所述被保护的半导体器件上提供阻挡掩模。
6.根据权利要求1的方法，其中所述应变引起覆层提供压缩应变以提高被保护的p型半导体器件的性能并且在暴露的n型半导体器件中驰豫所述压缩应变。
7.根据权利要求6的方法，其中所述p型半导体器件是p型MOSFET并且所述n型半导体器件是n型MOSFET。
8.根据权利要求1的方法，其中所述应变引起覆层提供拉伸应变以提高被保护的n型半导体器件的性能并且在暴露的p型半导体器件中驰豫所述压缩应变。
9.根据权利要求8的方法，其中所述p型半导体器件是p型MOSFET并且所述n型半导体器件是n型MOSFET。
10.根据权利要求1的方法，其中所述应变引起覆层包括Si3N4。
11.一种半导体结构，包括p型半导体器件和n型半导体器件，所述p型半导体器件和n型半导体器件中具有不同的应变量，所述结构包括：
所述半导体结构包括在衬底上形成的p型半导体器件和n型半导体器件；
在所述p型半导体器件和n型半导体器件的一个上形成具有初始全厚度的应变引起覆层，其中所述应变引起覆层在一个半导体器件中产生最优化全应变；
在所述p型半导体器件和所述n型半导体器件的另一个上形成具有小于全厚度的蚀刻减小的厚度的应变引起覆层，其中所述应变引起覆层的减小的厚度在另一个半导体器件中驰豫并产生比在所述一个半导体器件中更小的应变。
12.根据权利11的半导体结构，其中所述另一个半导体器件还具有注入的应变减小掺杂剂以进一步驰豫在所述另一个半导体器件中的应变。
13.根据权利要求12的半导体结构，其中所述注入的应变减小掺杂剂包括As或者Ge以进一步驰豫在所述另一个半导体器件中的应变。
14.根据权利要求11的半导体结构，其中所述应变引起覆层提供压缩应变以提高所述一个p型半导体器件的性能并且所述压缩应变在另一个n型半导体器件中驰豫。
15.根据权利要求11的半导体结构，其中所述p型半导体器件是p型MOSFET并且所述n型半导体器件是n型MOSFET。
16.根据权利要求11的半导体结构，其中所述应变引起覆层提供拉伸应变以提高所述一个n型半导体器件的性能并且所述压缩应变在另一个p型半导体器件中驰豫。
17.根据权利要求11的半导体结构，其中所述p型半导体器件是p型MOSFET并且所述n型半导体器件是n型MOSFET。
18.根据权利要求11的半导体结构，其中所述应变引起覆层包括Si3N4。
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