CN101512762A - 用于半导体电路小片的三维封装的可堆叠封装 - Google Patents

用于半导体电路小片的三维封装的可堆叠封装 Download PDF

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CN101512762A
CN101512762A CNA2007800320099A CN200780032009A CN101512762A CN 101512762 A CN101512762 A CN 101512762A CN A2007800320099 A CNA2007800320099 A CN A2007800320099A CN 200780032009 A CN200780032009 A CN 200780032009A CN 101512762 A CN101512762 A CN 101512762A
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lead
wire
section
sidewall
exterior section
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CN101512762B (zh
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肯·M·兰姆
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Atmel Corp
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Atmel Corp
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H—ELECTRICITY
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

一种用于封装半导体装置的设备和方法。所述设备包含无引线三维可堆叠半导体封装(300)的衬底条带组件(201A－201E)，其在例如四个外围边缘上具有安装接触件。所述衬底条带可经制造以用于安装单个电组件(例如，集成电路电路小片209)或可以X－Y矩阵模式布置多个衬底条带，所述多个衬底条带稍后可单体化(215)为单个封装条带以用于无引线封装。三维封装(350)是通过侧壁(203)的最上部分上的结合区域(301)实现的。所述条带的所述侧壁足够高以封闭覆盖稍后安装的集成电路电路小片和相关联结合导线(211)的囊封剂(213)。

Description

用于半导体电路小片的三维封装的可堆叠封装
技术领域
本发明涉及一种三维可堆叠半导体封装，且更特定来说，涉及一种用于涉及无引线封装的封装类型的三维可堆叠半导体封装。
背景技术
随着半导体集成电路芯片变得更加多功能且高度集成，芯片包含较多的结合焊垫(或端子焊垫)，且因此用于芯片的封装具有较多的外部端子(或引线)。当具有沿着封装周边的引线的常规塑料封装必须容纳大量电连接点时，封装的占据面积增加。然而，许多电子系统中的目标是最小化系统的总体尺寸。因此，为了容纳大量引脚而不增加封装的占据面积，封装的引脚间距(或引线间距)必须减小。然而，小于大约0.4mm的引脚间距带来许多技术问题。举例来说，对具有小于0.4mm的引脚间距的封装进行修整需要昂贵的修整工具，且引线容易在封装的处置期间弯曲。另外，此类封装的表面安装由于所需的关键的对准步骤而要求成本较高且复杂的表面安装工艺。
因此，为了避免与常规精细间距封装相关联的技术问题，已有人提出具有分区阵列(area array)或无引线外部端子的封装。这些封装包含球栅阵列封装、芯片级封装、四方扁平无引线(QFN)封装以及双列扁平无引线(DFN)封装。半导体行业目前使用若干芯片级封装。微球栅阵列封装(μBGA)和凸点芯片载体(BCC)是芯片级封装的实例。μBGA封装包含上面有形成导电图案的聚酰亚胺带且采用与常规塑料封装完全不同的制造工艺。凸点芯片载体封装包含衬底，所述衬底具有围绕铜合金板的顶面的中央部分形成的凹槽以及形成于凹槽中的电镀层。因此，芯片级封装使用专用的封装材料和工艺，其增加了封装制造成本。
图1A是现有技术的典型塑料囊封封装100(展示封装的俯视图100A、仰视图100B以及侧视图100C)。特定来说，囊封封装100是QFN封装。QFN封装100是无引线封装，其中对印刷电路板(PCB)的电接触是通过将封装100的底部100B表面上的焊接区(land)焊接到PCB而形成的，而不是以较传统形成的周边引线焊接到PCB。
图1B是使用中的现有技术QFN封装100的横截面图，且包含一铜焊接区101、多个焊料镀敷区域103、多个金引线导线105以及一向下结合区域107。铜焊接区101常常镀敷材料115(例如银)，所述材料经施加以便于金或铝导线结合(未图示)。集成电路电路小片109以合适的电路小片附接材料113(例如热环氧树脂)附接到QFN封装100。施加模制化合物111或其它覆盖材料以完成QFN封装100。
因此，使用常规封装材料和工艺的例如QFN或DFN的集成电路封装仅可通过仅存在于封装底面上的铜引线框101/镀敷区域103(图1B)的下部部分接入，以用于例如到印刷电路板的电互连。因此，在给定的印刷电路板占据面积中提供较高密度的集成电路封装需要一种允许集成电路封装以位于彼此之上乃至并排的方式容易地堆叠的方式。
发明内容
在一个示范性实施例中，本发明是一种无引线三维可堆叠半导体封装的衬底条带组件，其在例如四个外围边缘的顶部、底部和侧面上具有安装接触件。所述衬底条带可经制造以用于安装单个电组件(例如，集成电路电路小片)或可以X—Y矩阵模式布置多个衬底条带。所述条带矩阵稍后可单体化为各个封装条带以用于无引线封装。
每一衬底条带包含无引线外部部分，所述无引线外部部分具有多个彼此电隔离的区段。每一区段具有扁平导线结合区域以及基本上垂直于所述扁平导线结合区域的侧壁区域。所述侧壁区域以同心的方式定位于所述外部部分的最外周边上。
每一衬底条带还包含内部部分，其以同心的方式定位于所述外部部分内且与所述外部部分电隔离。所述内部部分比所述外部部分的所述侧壁区域薄，且经设计以充当用于集成电路电路小片或其它电组件的附接区域。所述内部部分与所述集成电路电路小片(或组件)的组合厚度小于所述侧壁区域的高度。此安装布置使所述侧壁区域的最上部分保持电暴露以用于在所述第一封装之上安装额外的无引线封装或其它组件。
在另一示范性实施例中，一种无引线三维可堆叠半导体封装的衬底条带组件在例如两个相对(例如，平行)边缘的顶部、底部和侧面上具有安装接触件。所述衬底条带可经制造以用于安装单个电组件(例如，集成电路电路小片)或可以X—Y矩阵模式布置多个衬底条带。所述条带矩阵稍后可单体化为各个封装条带以用于无引线封装。
在此实施例中，衬底条带具有一对平行的无引线外部部分。每一无引线外部部分具有多个彼此电隔离的区段。每一区段还具有扁平导线结合区域以及基本上垂直于所述扁平导线结合区域的侧壁区域，所述侧壁区域定位于每一所述外部部分的最外边缘上。
内部部分定位于所述对外部部分之间且与其电隔离。所述内部部分比所述平行外部部分的所述侧壁区域薄，且经设计以充当用于集成电路电路小片或其它电组件的附接区域。所述内部部分与所述集成电路电路小片(或组件)的组合厚度小于所述侧壁区域的高度。此安装布置使所述侧壁区域的最上部分保持电暴露以用于在所述第一封装之上安装额外的无引线封装或其它组件。
在另一示范性实施例中，本发明是一种封装半导体装置的方法。所述方法包含将电组件安装到内部部分电路小片焊垫，其中所述电路小片焊垫是第一无引线三维可堆叠半导体封装的衬底条带组件的一部分。将多个结合导线从所述电组件上的多个结合焊垫紧固到所述衬底条带组件的无引线外部部分上包含的多个导线结合焊垫中的对应导线结合焊垫。所述外部部分具有侧壁，所述侧壁具有大于所述电组件与所述内部部分电路小片焊垫的组合高度的高度。
随后以囊封材料覆盖所述电组件、结合导线以及所述电路小片焊垫的任何暴露部分直到位于或接近所述无引线外部部分上的所述侧壁的最上部分的水平面。
附图说明
图1A和1B展示现有技术的QFN芯片载体封装。
图2A到2F展示根据本发明的可堆叠集成电路电路小片和离散组件载体的示范性横截面或平面图。
图3A和3B展示呈单个和堆叠配置的经单体化的封装。
图4A到4D展示允许用于单体化的不同布局布置的各种横截面实施例。
图5展示根据本发明一般实施例的QFN和DFN封装的特定实施例的完成的外部视图。
图6A和6B展示以单独集成电路电路小片和离散组件堆叠的经单体化的封装。
具体实施方式
在图2A中，将衬底条带201A选择为具有接近于完成封装的最终“高度”的厚度。为衬底条带201A选择的高度将基于放置在最终封装中的特定组件，但将通常从0.2mm到2mm变化。下文中将更详细论述确定用于给定封装的实际高度的额外细节。
本文描述的工艺涉及其中许多封装是以X—Y矩阵形成的示范性实施例，但也可容易通过相同工艺形成单个封装。用于衬底条带201A的X—Y矩阵大小可经选择以适合特定卖主的加工。在特定示范性实施例中，衬底的X—Y尺寸可为205mm×60mm，且将构造材料选择为铜。在其它示范性实施例中，衬底201A可为另一类型的金属或非金属材料。所述材料可为导电的或不导电的。另外，非矩形矩阵形状是预期的。
在图2B中，衬底条带201A经图案蚀刻，从而留下经蚀刻的衬底条带201B。在图案蚀刻过程期间，衬底条带201A的底部厚度减小，同时留下基本上完整高度的侧壁203。图案形成和图案蚀刻步骤是此项技术中已知的且将取决于选择的材料而变化。侧壁203之间的区域是厚度减小的区域。这些区域的若干部分将在后续步骤中充当电路小片焊垫安装区域。因此，侧壁203是大体上垂直于厚度减小的区域的区域。侧壁的高度选择为足够的，使得包含在封装内的任何安装的集成电路和结合引线均将位于或低于侧壁203的最上部。底部厚度的其它部分稍后将充当结合指形物。在特定示范性实施例中，经蚀刻的衬底条带201B的底部部分的高度减小到大约0.12mm(大约5密耳)。
参看图2C，经蚀刻的衬底条带201B进一步经图案蚀刻以形成引线框衬底条带201C。引线框衬底条带201C包含电路小片附接焊垫205，且侧壁203进一步经蚀刻从而界定如平面图207中所见的单独的结合指形物特征。平面图207展示示范性205mm×60mm衬底的一部分。如横截面和平面图中共同所见，结合指形物具有一体式侧壁203，其大体上保持引线框衬底条带201C的全高度。电路小片附接焊垫205由于图案蚀刻步骤而与结合指形物/一体式侧壁203电隔离。在特定示范性实施例中，引线框衬底条带201C的暴露区域是以例如银完全镀敷或点镀敷。在其它示范性实施例中，引线框衬底条带201C以可导线结合的金属和可焊接金属层完全镀敷。举例来说，引线框衬底条带201C可为具有镍-钯-金(Ni-Pd-Au)镀敷的引线框。可使用高温聚酰亚胺带将所有封装部分紧固在适当位置。
在图2D中，通过将各个集成电路小片209粘结(例如，经由标准热环氧树脂或粘合带)到电路小片附接焊垫205来装填经蚀刻的引线框衬底条带201D。各种粘结技术和工艺是本行业中已知的。随后附接结合导线211以电连接到经蚀刻的引线框衬底条带201D的若干部分。
参看图2E，随后以环氧树脂模制化合物213囊封经装填的引线框条带201E。囊封技术是此项技术中众所周知的。在囊封之后，随后以例如锡(Sn)、锡合金、Ni/Au或拥有导电且可焊接特性的其它镀敷材料来镀敷经装填的引线框条带201E的暴露部分。镀敷在将最终封装安装到PCB或另一电路小片封装时允许良好电连接。如果引线框衬底条带经预镀敷，那么此最终镀敷步骤是不必要的。
在图2F中，随后沿着多个锯切线215通过例如锯切或激光切割的标准技术将经装填的引线框条带201E单体化。在单体化过程之后，产生多个QFN型封装。作为所形成的结合指形物特征(图2C)的完整高度的一体式部分的侧壁203的每一者将电信号从封装的下部部分携载到封装的上部部分。因此，所有电信号在最终封装的上部部分和下部部分两者上均可用，因此封装的三维堆叠是可能的。
或者，所属领域的技术人员可容易设想对上述其中产生DFN型封装的工艺的修改。DFN型封装在封装的两个平行相对边缘上而不是像QFN型封装中那样在所有四个边缘上具有外部连接点。
参看图3A，以横截面展示经单体化的DFN型或QFN型封装300。(请注意QFN型或DFN型封装从横截面看上去彼此类似。)经单体化的DFN型或QFN型封装300可用作单个封装且直接安装到PCB或其它结构。或者，如图3B所示，三个经单体化的DFN型或QFN型封装300以三维结构350堆叠。经单体化的封装300中的每一者通过例如焊接接缝301彼此电连接。
图4A到4D指示上文中参看图2A到2F详细解释的衬底条带的替代实施例。单体化锯401(或激光或其它单体化方法)的放置提供了对侧壁的某些各种布置的指示。出于比较目的，图4A的共同侧壁方法是上文中参看图2A到2F描述的相同的实心共同壁方法。
图4B是侧壁设计的替代配置。位于两个单体化锯401之间的“间隙”在引线框衬底条带蚀刻过程(图2C)期间形成。留下间隙导致用于单体化锯401的较少金属侧壁，因此减少了锯切时间，同时减少了刀片磨损。
图4C指示其中在侧壁的下侧上保留间隙的壁布置。此布置可通过例如两侧蚀刻来实现。或者，下侧间隙可通过例如冲孔或冲压的机械方式形成。
图4D的双侧壁布置以类似于参看图4C描述的形成方法的方式形成。
参看图5，其展示根据本文所述的本发明优选实施例制造的已完成的QFN型(左方，501、503、505)和DFN型(右方，551、553、555)封装的各种视图。给出俯视图501、551、侧视图503、553和仰视图505、555以分别参考QFN型和DFN型封装来视觉化已完成的封装。关于仰视图505、555应特别注意，通过使电路小片附接焊盘的底部部分暴露来实现每一封装类型的热增强。如此布置的电路小片附接焊盘在直接焊接到PCB时提供了有效的热传导路径。或者，也可通过例如热传导环氧树脂来实现热传导。此热增强可通过使用向下结合物或通过经由导电电路小片附接材料的电连接而另外提供稳定的接地。
在图6A的替代性三维堆叠布置中，集成电路电路小片601直接附接在经单体化的封装300(图3A)上。集成电路电路小片601通过多个结合导线603电附接到经单体化的封装。可在集成电路电路小片601和所述多个结合导线603上添加任选的囊封剂605。可通过模制或分配技术施加囊封剂605，所述两种技术在此项技术中是已知的。在特定示范性实施例中，囊封剂605可为半透明的，使得可通过半透明囊封剂605(例如，LED、激光器或EPROM)取用集成电路电路小片601的任何光学性质。
在图6B的另一替代性堆叠布置中，集成电路电路小片或离散组件607可预先安装在电路衬底(例如，小型子插件板)上。另外，一个或一个以上任选的离散组件611可安装到电路衬底609。集成电路电路小片或离散组件607以及所述一个或一个以上任选的离散组件611通过多个衬底结合导线613或到电路衬底609的直接电连接(未图示)而电连接到电路衬底609。电路衬底609又通过多个封装结合导线615电连接到经单体化的封装。可在集成电路电路小片或离散组件607、所述一个或一个以上任选的离散组件611、电路衬底609以及所述多个结合导线613、615上添加任选的囊封剂617。可通过模制或分配技术施加囊封剂617，所述两种技术在此项技术中是已知的。在特定示范性实施例中，囊封剂617可为半透明的，使得可通过半透明囊封剂617(例如，LED、激光器或EPROM)取用集成电路电路小片或离散组件607、611的任何光学性质。
在上述说明书中，已参考本发明的特定实施例描述本发明。然而所属领域的技术人员将明了，在不脱离如所附权利要求书中陈述的本发明的较宽精神和范围的情况下可对本发明做出各种修改和改变。举例来说，所属领域的技术人员将了解，本发明的实施例可容易应用于
Figure A200780032009D00091
(薄阵列塑料封装)、(超薄焊接区栅格阵列)、(凸点芯片载体)或其它类似封装类型的经修改版本。因此说明书和图式应在说明性意义上而不是在限制性意义上来看待。

Claims (17)

1.一种无引线三维可堆叠半导体封装的衬底条带组件，所述衬底条带包括：
一个或一个以上区域，上面用以安装集成电路电路小片，所述一个或一个以上区域中的每一者具有：
无引线外部部分，所述无引线外部部分包含多个区段，所述区段彼此电隔离且具有扁平导线结合区域以及基本上垂直于所述扁平导线结合区域的侧壁区域，所述侧壁区域以同心方式定位于所述外部部分的最外周边上；以及
内部部分，其以同心方式定位于所述外部部分内且与所述外部部分电隔离，所述内部部分比所述外部部分的所述侧壁区域薄，且经配置以充当用于所述集成电路电路小片的附接区域，所述内部部分与所述集成电路电路小片的组合厚度小于所述侧壁区域的高度。
2.根据权利要求1所述的衬底条带，其中所述一个或一个以上区域以矩阵模式布置。
3.根据权利要求1所述的衬底条带，其中所述外部部分和所述内部部分每一者由铜组成。
4.根据权利要求3所述的衬底条带，其中所述铜的至少若干部分以锡镀敷。
5.根据权利要求3所述的衬底条带，其中所述铜的至少若干部分以锡合金镀敷。
6.根据权利要求3所述的衬底条带，其中所述铜的至少若干部分以镍-金合金镀敷。
7.一种无引线三维可堆叠半导体封装，其包括：
无引线外部部分，其包含多个区段，所述区段彼此电隔离且具有扁平导线结合区域以及基本上垂直于所述扁平导线结合区域的侧壁区域，所述侧壁区域以同心方式定位于所述外部部分的最外周边上；
内部部分，其以同心方式定位于所述外部部分内且与所述外部部分电隔离，所述内部部分比所述外部部分的所述侧壁区域薄，且经配置以充当用于集成电路电路小片的附接区域，所述内部部分与所述集成电路电路小片的组合厚度小于所述侧壁区域的高度；以及
囊封剂，其大体上形成于所述无引线外部部分和所述内部部分两者上，同时使所述侧壁的最上部分和最下部分保持暴露。
8.根据权利要求24所述的无引线三维可堆叠半导体封装，其中所述侧壁的所述暴露部分以导电且非氧化材料镀敷。
9.一种封装半导体装置的方法，所述方法包括：
将电组件安装到内部部分电路小片焊垫，所述电路小片焊垫是第一无引线三维可堆叠半导体封装的衬底条带组件的一部分；
将多个结合导线从所述电组件上的多个结合焊垫紧固到所述衬底条带组件的无引线外部部分上包含的多个导线结合焊垫中的对应导线结合焊垫；
将所述多个导线结合焊垫中每一者的侧壁选择为大于所述电组件与所述内部部分电路小片焊垫的组合高度；以及
以囊封材料覆盖所述电组件、结合导线以及所述电路小片焊垫的任何暴露部分直到所述无引线外部部分上的所述侧壁的最上部分。
10.根据权利要求9所述的方法，其进一步包括以导电且非氧化材料镀敷所述侧壁的所述最上部分的任何暴露区域。
11.根据权利要求10所述的方法，其中将所述导电且非氧化材料选择为锡。
12.根据权利要求10所述的方法，其中将所述导电且非氧化材料选择为锡合金。
13.根据权利要求10所述的方法，其中将所述导电且非氧化材料选择为镍-金合金。
14.根据权利要求9所述的方法，其进一步包括以导电且非氧化材料镀敷所述电路小片焊垫的最下部分的任何暴露区域。
15.根据权利要求9所述的方法，其进一步包括：
在所述囊封材料上安装一个或一个以上额外的电组件；以及
将多个结合导线从所述一个或一个以上额外的电组件紧固到所述侧壁的所述最上部分。
16.根据权利要求15所述的方法，其中在将所述一个或一个以上额外的电组件安装于所述囊封材料上之前首先将其安装到电路衬底。
17.根据权利要求9所述的方法，其进一步包括在所述第一无引线三维可堆叠半导体封装上安装电接触的额外无引线三维封装。
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CN105280580A (zh) * 2014-06-02 2016-01-27 英飞凌科技股份有限公司 引线封装体和电子部件的三维堆叠
CN105097569A (zh) * 2015-07-30 2015-11-25 南通富士通微电子股份有限公司 半导体叠层封装方法
CN105161425A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN105161424A (zh) * 2015-07-30 2015-12-16 南通富士通微电子股份有限公司 半导体叠层封装方法
CN109691242A (zh) * 2016-10-14 2019-04-26 欧姆龙株式会社 电子装置及其制造方法
CN108198797A (zh) * 2017-12-29 2018-06-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198761A (zh) * 2017-12-29 2018-06-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198804A (zh) * 2017-12-29 2018-06-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108206170A (zh) * 2017-12-29 2018-06-26 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198790A (zh) * 2017-12-29 2018-06-22 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108109972A (zh) * 2017-12-29 2018-06-01 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺

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TW200818458A (en) 2008-04-16
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