CN101567307A - 宽引线框架半导体封装制造装置及半导体封装形成方法 - Google Patents
宽引线框架半导体封装制造装置及半导体封装形成方法 Download PDFInfo
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Abstract
一种用于制造半导体封装的装置包括:引导轨,沿正向和反向传送引线框架,该引线框架具有第一表面以及与第一表面相对的第二表面;加载部分,连接到引导轨的端部,向引导轨提供引线框架;框架驱动部分,连接到引导轨的所述端部的相对端部,绕第一表面的法向旋转引线框架;和导线键合部分,使用导线键合,将引线框架与附接到提供给引导轨的引线框架上的半导体芯片电连接。
Description
本申请要求2008年4月25日在韩国知识产权局递交的韩国专利申请No.10-2008-0038989的权益,其公开整体结合于此以作参考。
技术领域
本发明涉及一种制造半导体封装的装置和方法,更具体地,涉及一种通过对宽引线框架执行导线(wire)键合(bonding)处理从而来形成半导体封装的装置和方法。
背景技术
随着移动电话和膝上电脑的使用不断增加,这些电子设备已经被开发得更加紧凑、更轻,并具有更多功能。因此,这些电子设备中所使用的电子部件需要制造得更小,并具有更高的集成密度。为了满足这些需要,与高度集成半导体芯片以减小其尺寸的方法一起,还广泛使用通过多芯片封装技术来安装半导体芯片的方法。
图1是示出了常规双管芯封装(DDP)结构的截面图。参照图1,在引线框架20上安装两个半导体芯片,即,第一和第二半导体芯片11和13。引线框架20包括管芯垫(pad)21和引线指(finger)23。第一和第二半导体芯片11和13分别通过第一和第二粘附层25和26附接在管芯垫21的上、下表面上。第一和第二半导体芯片11和13通过导线键合(wire bond)27和28电连接到引线指23。第一和第二半导体芯片11和13、导线键合27和28、以及它们的结合部分通过制模(molding)树脂15(如环氧树脂模塑料)密封,从而免受外部环境的影响。
图2是示出了常规四管芯封装(QDP)结构的截面图。参照图2,在包括管芯垫41和引线指43的引线框架40上安装四个半导体芯片。即,第一和第二半导体芯片31和33通过附接至第一和第二粘附层45、47,而顺序放置管芯垫41的上表面上。第三和第四半导体芯片35和37通过附接至第三和第四粘附层46、48,而顺序放置在管芯垫41的下表面上。第一至第四半导体芯片31、33、35和37通过导线键合51、53、55和57电连接到引线指43。第一至第四半导体芯片31、33、35和37,导线键合51、53、55和57,以及它们的结合部分通过制模树脂61(如环氧制模树脂)密封。
制造单半导体芯片封装,以及制造使用图1和2中所示的DDP和QDP结构的引线框架的半导体封装的工艺包括:导线键合处理,用于从集成电路(IC)所形成于的晶片中分离出单位半导体芯片,并将分离出的单位半导体芯片附接至引线框架;导线键合处理,用于使用导电金属线,键合半导体芯片和引线框架,从而在它们之间进行电连接;制模处理,利用制模树脂对电连接的部件进行制模,以保护其免受外部环境影响;修整/成形处理,用于剪切和弯曲伸出在外的引线指;以及测试处理,用于测试成品IC芯片封装的可靠性。
在常规半导体封装制造工艺中,引线框架用来提供安装半导体芯片的场所,并用作进行电连接的装置。在这一方面,随着市场竞争和半导体器件技术发展的深入,产率以及成本降低成为更加重要的问题。通常,将引线框架制造成条状,使得可同时制造八至十个半导体封装。然而,为了增加使用单个引线框架制造而成的半导体封装数目,已经开发出宽度较宽的宽引线框架,从而不仅可在引线框架的长度方向、而且还可以在引线框架的宽度方向制造多个半导体封装。
然而,为了使用宽引线框架,必须使用半导体封装制造设备,而开发及制造这种设备的成本很高。另外,用于多芯片封装的半导体芯片封装制造工艺需要人工操作,从而由于处理延迟而增加处理时间,并因此产率下降。
发明内容
为了解决上述和/或其他问题,本发明提供了一种用于使用宽引线框架制造半导体芯片封装的装置。
此外,本发明提供了一种使用宽引线框架形成半导体芯片封装的方法,从而降低制造成本,并改进了产率。
根据本发明的一个方面,一种用于制造半导体封装的装置包括:引导轨,沿正向和反向传送引线框架,该引线框架具有第一表面以及与第一表面相对的第二表面;加载部分,连接到引导轨的端部,向引导轨提供引线框架;框架驱动部分,连接到引导轨的所述端部的相对端部,绕第一表面的法向旋转引线框架;和导线键合部分,使用导线键合,将引线框架与附接到提供给引导轨的引线框架上的半导体芯片电连接。
导线键合部分包括:键合头,具有键合换能器,使用导线,将引线框架与附接至引线框架的半导体芯片连接;和传送模块,在引导轨之上传送键合头。
传送模块使键合头在引导轨的宽度方向上从引导轨在宽度方向的一端至少移动到引导轨的宽度中心位置。
该装置还包括卸载部分,该卸载部分连接到框架驱动部分,以将引线框架取出到装置外部,其中,框架驱动部分根据引线框架的状态,选择性地将引线框架传送到卸载部分,或将引线框架返回引导轨。
为了绕第一表面的法向旋转引线框架,框架驱动部分包括:框架加载轨,支撑引线框架;旋转台,支撑框架加载轨;旋转轴,在沿第一表面法向的方向,连接到旋转台;和旋转驱动装置,向旋转轴提供旋转驱动力。
框架加载轨支撑引线框架,使得框架驱动部分一次旋转一个引线框架。
框架驱动部分将引线框架旋转180°。
加载部分具有卸载功能,以将从引导轨传送来的引线框架取出到装置外部。
框架驱动部分还包括翻转装置,该翻转装置将引线框架翻转,使得引线框架的第一和第二表面中朝上的一个表面朝下。
根据本发明的另一方面,一种用于制造半导体封装的装置包括:第一导线键合装置和第二导线键合装置,均包括沿正向和反向传送引线框架的引导轨、以及使用导线键合将引线框架与附接至引线框架的半导体芯片电连接的导线键合部分,其中该引线框架具有第一表面以及与第一表面相对的第二表面;加载部分,连接到第一导线键合装置的端部,向第一导线键合装置提供引线框架;卸载部分,连接到第二导线键合装置的端部,从第二导线键合装置取出引线框架;和框架驱动部分,连接在第一和第二导线键合装置的端部中相对的端部之间,绕第一表面的法向旋转引线框架。
框架驱动部分根据引线框架的状态,选择性地将引线框架传送至第一导线键合装置或第二导线键合装置。
根据本发明的另一方面,一种制造半导体封装的方法包括:向导线键合部分提供引线框架,该引线框架具有第一表面以及与第一表面相对的第二表面,在第一表面上附接有多个半导体芯片,且第一表面朝上,其中沿第一方向移动引线框架;在导线键合部分中,将引线框架与附接至引线框架的第一表面的一些半导体芯片电连接(第一导线键合操作);绕第一表面的法向旋转引线框架;和在导线键合部分中,将引线框架与附接至引线框架的第一表面、尚未进行导线键合的半导体芯片电连接(第二导线键合操作)。
该方法还包括:翻转引线框架,使得引线框架的第二表面朝上,其中多个半导体芯片附接在第二表面上;在导线键合部分中,将引线框架与附接至引线框架的第二表面的一些半导体芯片电连接(第三导线键合操作);绕第二表面的法向旋转引线框架;和在导线键合部分中,将引线框架与附接至引线框架的第二表面、尚未进行导线键合的半导体芯片电连接(第四导线键合操作)。
在第一导线键合操作中,使用导线键合,将引线框架与引线框架第一表面上相对于第一表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该中心线沿第一方向延伸。在第二导线键合操作中,使用导线键合,将引线框架与引线框架第一表面上相对于第一表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该中心线沿第一方向延伸。
在第三导线键合操作中,使用导线键合,将引线框架与引线框架第二表面上相对于第二表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该中心线沿第一方向延伸。在第四导线键合操作中,使用导线键合,将引线框架与引线框架第二表面上相对于第二表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该中心线沿第一方向延伸。
附图说明
通过参照附图对本发明的示例性实施例进行详细描述,本发明的以上和其他特征和优势将变得更加明显,其中:
图1是示出了常规双管芯封装(DDP)结构的截面图;
图2是示出了常规四管芯封装(QDP)结构的截面图;
图3是根据本发明实施例用于制造半导体封装的宽引线框架的平面图;
图4和5分别是根据本发明实施例用于制造半导体封装的装置的平面图和截面图;
图6和7分别是根据本发明实施例的旋转台的平面图和截面图;
图8~11示出了根据本发明实施例的导线键合处理;
图12和13示出了根据本发明另一实施例的导线键合处理;以及
图14是根据本发明另一实施例用于制造半导体封装的装置的平面图。
具体实施方式
现在将参照附图更为全面地描述本发明,在附图中示出了本发明的示例性实施例。然而,本发明可以多种不同形式来实现,而不应解释为局限于此处所述的实施例;相反,提供这些实施例,只是为了使得本公开充分和完整,并向本领域的技术人员充分传达本发明的思想。在附图中,为清楚的目的,对层和区域的厚度进行了放大。还应理解的是,当一层被称作在另一层或衬底“上”时,这一层可直接位于该另一层或衬底之上,或者也可存在中间层。附图中相同的标号表示相同的元件。这里所使用的术语仅用于解释本发明的目的,而不是为了限制由所附权利要求限定的本发明的意义或范围。
图3是根据本发明实施例用于制造半导体封装的宽引线框架70的平面图。参照图3,在宽引线框架70上沿其长度方向L和宽度方向W均重复设置多个单位引线框架80。宽引线框架70的长度方向L意味着在导线键合处理中宽引线框架70沿着移动的方向。半导体芯片210附接至每个单位引线框架80。要制造多个半导体封装的宽引线框架70经历与半导体芯片210的电连接处理,以及在制模区域72上堆积制模树脂的处理。然后,宽引线框架70被分离为单独的半导体封装,从而制造出多个半导体封装。因此,由于宽引线框架70包括更多数目的单位引线框架80,所以将被丢弃的宽引线框架70的边缘部分的尺寸减小,从而制造成本降低,且产率增加。
如随后将详细描述的那样,为了将宽引线框架70与半导体芯片210电连接,通过键合头(未示出)将导线(未示出)移向宽引线框架70。一般而言,宽引线框架70在长度方向L上沿着引导轨(index rail)(未示出)移动。虽然键合头沿宽引线框架70的长度方向L移动,但是键合头通常沿宽引线框架70的宽度方向W移动,以对宽引线框架70与半导体芯片210进行导线键合。宽引线框架70的宽度中心线C是一条假想线,其连接宽引线框架70在宽度方向W上的中心,并沿长度方向L延伸。
由于必须准确执行导线键合处理,所以用于移动半导体芯片的键合头运动应该非常精确。键合头可在置于引导轨120上的引线框架70上移动、且以所需精度执行导线键合处理的距离被称作有效移动距离。因此,当宽引线框架70的宽度W大于键合头在宽度方向W上的有效移动距离WB时,不可能以所需精度在宽引线框架70上对半导体芯片210执行导线键合处理。所需精度根据宽引线框架70或所附接的半导体芯片的类型和规格来确定。当不满足所需精度时,成品半导体封装带缺陷的可能性较高。
在制造键合头的有效移动距离增大的半导体封装制造装置时,需要昂贵的成本。这是因为需要大量的成本来开发并制造可高精度移动较长距离的精确受控设备。因此,与成本降低和产率提升的效果相比,需要相对较高的成本。
图4是根据本发明实施例用于制造半导体封装的装置100的平面图。参照图4,用于制造半导体封装的装置100包括加载部分110、引导轨120、导线键合部分130和框架驱动部分140。加载部分110提供在产品架(magazine)中容纳、且包含多个引线框架的宽引线框架70。引导轨120将加载部分110所提供的宽引线框架70传送至框架驱动部分140。因此,宽引线框架70沿长度方向L移动。导线键合部分130使用导线(例如,金线),对沿引导轨120传送来的宽引线框架70与附接至宽引线框架70的半导体芯片进行导线键合,从而电连接宽引线框架70和半导体芯片210。
通过导线键合部分130附接至宽引线框架70的半导体芯片可由晶片仓(cassette)加载部分160和晶片台150提供。由晶片仓加载部分160提供的具有多个半导体芯片的晶片被放置在晶片台150上。晶片在放置在晶片台150上时可能已被分离为单独的半导体芯片,或者可在放置在晶片台150上之后在晶片台150上被分离单独的半导体芯片。也就是说,在将粘附带粘附至晶片的后表面之后,晶片可完全分离为单独半导体芯片或者在单独半导体芯片之间形成沟槽,而放置在晶片台150上。可选地,在粘附带粘附至晶片的后表面的情况下将晶片放置在晶片台150上之后,可以将半导体芯片完全分离为单独的半导体芯片,或者可在单独半导体芯片之间形成沟槽。通过拉伸粘附带,可增大单独半导体芯片之间的间隔。此外,可向晶片台150提供真空压,以将单独半导体芯片从粘附带分开。
框架驱动部分140可将沿引导轨120传送的宽引线框架70绕相对于宽引线框架70的上或下表面的垂直线进行旋转,或者翻转宽引线框架70使得宽引线框架70的上表面朝下。框架驱动部分140可具有旋转和翻转两种功能,或者具有这些功能之一。框架驱动部分140可根据宽引线框架70的状态,选择性地旋转或翻转宽引线框架70,或将宽引线框架70返回到引导轨120。
加载部分110可向产品架填充导线键合了半导体芯片210的宽引线框架70,并移走产品架。此外,卸载部分170单独连接至框架驱动部分140,以向产品架填充导线键合了半导体芯片210的宽引线框架70,并移走产品架。也就是说,加载部分110可具有加载和卸载两种功能,或者可单独使用具有卸载功能的卸载部分170。当使用卸载部分170时,框架驱动部分140可根据宽引线框架70的状态,选择性地旋转或翻转宽引线框架70,将宽引线框架70返回到引导轨,或将宽引线框架传送至卸载部分170。换言之,可根据诸如工作移动之类的工作效率或者对进行过导线键合的宽引线框架70与并未进行过导线键合的宽引线框架70进行区分的方便性,来选择性确定是在加载部分110中加入卸载功能,还是单独连接卸载部分170。
图5是沿图4中V-V线的截面图,示出了根据本发明实施例用于制造半导体封装的装置。参照图5,导线键合部分130包括键合头132和传送轨134。键合头132包括键合换能器(transducer)132a和头模块132b。键合换能器132a连接到头模块132b,并上下运动以传送导线键合所需的能量,例如,使用超声波的能量。键合探针220可连接到键合换能器132a的顶端。键合探针220可利用导线230(例如,金线)形成导线键合232,将半导体芯片210和宽引线框架70电连接。传送模块134包括传送轴134a和传送驱动装置134b,并可在宽引线框架70上移动键合头132。键合头132的有效移动距离表示在键合头132移动时可形成导线键合232的距离。引导轨120的宽度WI表示可放置在引导轨120上的宽引线框架70的宽度。
参照图3和5,当引导轨120可容纳多种宽度的宽引线框架70时,引导轨120的宽度WI表示可放置在引导轨120上的任意宽引线框架中宽度最大的宽引线框架的宽度。因此,引导轨120的宽度WI不小于宽引线框架70的宽度W(WI≥W)。然而,在如下描述中,为了便于解释,宽引线框架70表示引导轨120上可容纳的宽度最大的宽引线框架。因此,除非另外指出,引导轨120的宽度WI与宽引线框架70的宽度W相同(WI=W)。
键合头132的有效移动距离WB是从引导轨120在宽度方向WI的端部至少到宽引线框架70的宽度中心线C,并且没有覆盖宽引线框架70的整个宽度W(WI/2≤WB<WI)。也就是说,虽然传送模块134可使键合头132以所需精度在引导轨120宽度WI的一半上移动,但是键合头132不能以所需精度在引导轨120的整个宽度WI上移动。因此,虽然导线键合部分130可在宽引线框架70沿其宽度方向的至少一半部分中形成导线键合232,但是其不能在引导轨120宽度WI的与上述一半部分相对的另一半部分中完整或局部形成导线键合232。
换言之,虽然导线键合部分130可形成导线键合232来将宽引线框架70与从宽引线框架70沿宽度方向的一个端部到宽引线框架70的宽度中心线C之间存在的所有半导体芯片210电连接,但是其并不能形成导线键合232来将宽引线框架70与宽引线框架70上的所有半导体芯片210电连接。不能形成导线键合232意味着不能以宽引线框架70所需的精度,即在预定误差范围内,来形成导线键合232。
在通过导线键合部分130形成将半导体芯片210与宽引线框架70电连接的导线键合232时,吸收块125从宽引线框架70下方提供压力或热量,以帮助将半导体芯片210附接至宽引线框架70。
图6是根据本发明实施例的旋转台142的平面图。参照图4和6,框架驱动部分140包括旋转台142。框架加载轨144耦合至旋转台142,该框架加载轨144每次支撑一个从引导轨120传送来的宽引线框架70。还可以向框架加载轨144耦合框架固定装置146,用于压住宽引线框架70以将其固定在框架加载轨144上。置于框架加载轨144上的宽引线框架70可与旋转台142一起旋转。
图7是旋转台142沿图6中线VII-VII的截面图。参照图7,旋转装置148连接到旋转台142下部。旋转装置148包括旋转轴148a和旋转驱动装置148b。旋转轴148a在沿着与旋转台142耦合的框架加载轨144的上表面(即,置于框架加载轨144上的宽引线框架70的上表面)的法向的方向,连接到旋转台142。因此,当旋转驱动装置148b旋转旋转轴148a时,框架加载轨144与旋转台142一起旋转,从而宽引线框架70可绕宽引线框架70的上表面的法向旋转。旋转驱动装置148b可使用气缸(air cylinder)(未示出)向旋转轴148a提供旋转驱动力。因此,旋转装置148可将宽引线框架70平滑旋转180°。然而,旋转装置148可根据与周围装置的连接,以不同角度来旋转宽引线框架70。可根据例如相对于旋转轴148a向左或向右的必要性,来选择旋转轴148a的旋转方向。
图8~11示出了根据本发明实施例的导线键合处理。图8示出了在宽引线框架70的一部分上表面上形成导线键合232的情况。参照图8,形成导线键合232,将宽引线框架70与宽引线框架70相对于宽度中心线C的一半部分中存在的半导体芯片210电连接。可形成导线键合232,将宽引线框架70与在宽引线框架70的一半部分中存在的半导体芯片210、以及另一半部分中存在的一些半导体芯片210电连接。但是,并非宽引线框架70另一半部分中的所有半导体芯片210可通过导线键合232电连接到宽引线框架70。在通过导线键合232将宽引线框架70一半部分中的所有半导体芯片210与宽引线框架70电连接之后,将宽引线框架70传送至框架驱动部分140。
在下面的描述中,表述“在宽引线框架70的一半部分中形成导线键合232”表示宽引线框架70相对于宽度中心线C的至少一半部分中存在的所有半导体芯片210、以及宽引线框架70的另一半部分中存在的一些半导体芯片210(但并非宽引线框架70另一半部分中存在的所有半导体芯片210)可通过导线键合232电连接到宽引线框架70。
图9示出了根据本发明实施例旋转宽引线框架70的情况。参照图9,宽引线框架70置于框架加载轨144上,并可由框架固定装置146压住以固定在框架加载轨144上。当旋转台142旋转时,宽引线框架70一起旋转。
图10示出了宽引线框架70旋转后的情况。参照图10,宽引线框架70绕宽引线框架70上表面的法向旋转180°。因此,宽引线框架70被翻转,使得宽引线框架70已经对全部半导体芯片210进行了导线键合的一半部分的位置与宽引线框架70局部或未全部对半导体芯片210进行导线键合的另一半部分的位置得以交换。然后,将宽引线框架70提供给引导轨120。
图11示出了在宽引线框架70的整个上表面上形成导线键合232的情况。参照图11,通过引导轨120将宽引线框架70传送至导线键合部分130。因为宽引线框架70由于其旋转而在宽度方向的位置被交换,所以可在宽引线框架70的另一半部分中形成导线键合232,在该另一半部分中,局部或并未全部形成用于将宽引线框架70与半导体芯片210电连接的导线键合232。因此,形成了导线键合232,使得宽引线框架70上表面上的所有半导体芯片210可电连接到宽引线框架70。
通过导线键合232与所有半导体芯片210电连接的宽引线框架70被传送至加载部分110并卸载,或者通过框架驱动部分140传送至卸载部分170并卸载。结果,可使用适于宽度相对较窄的引线框架且相对便宜的导线键合部分130,来对宽度相对较大的宽引线框架执行导线键合处理。
图12和13示出了根据本发明另一实施例的导线键合处理。图12示出了根据本发明另一实施例附接到宽引线框架70上表面上的半导体芯片210与宽引线框架70通过导线键合232电连接的情况。参照图12,在框架驱动部分140中,翻转装置180连接到与旋转台142耦合的框架加载轨144。图7中的旋转装置148可连接到旋转台142。也就是说,框架驱动部分140可以按需仅包括旋转装置148,仅包括翻转装置180,或者包括旋转装置148和翻转装置180两者。
翻转装置180包括:翻转旋转轴182,沿置于框架加载轨144上的宽引线框架70的长度方向延伸;以及翻转驱动装置184,连接到翻转旋转轴182。当翻转旋转轴182由翻转驱动装置184旋转时,置于框架加载轨144上的宽引线框架70被翻转,使得宽引线框架70的上表面朝下。因此,宽引线框架70优选地由框架固定装置146压住,从而不会与框架加载轨144分离。
图13示出了根据本发明另一实施例通过导线键合232与宽引线框架70电连接的半导体芯片210位于宽引线框架的下表面上的情况。参照图13,宽引线框架70被翻转装置180翻转,使得宽引线框架70的上表面朝下。因此,用于电连接宽引线框架70与半导体芯片210的导线键合232位于宽引线框架70的下表面上。将宽引线框架70提供给引导轨120,使得在宽引线框架70并未形成导线键合232的上表面上形成导线键合,从而将半导体芯片210与宽引线框架70电连接。
图14是根据本发明另一实施例用于制造半导体封装的装置的平面图。参照图14,半导体封装制造装置500包括加载部分110、第一导线键合装置510、框架驱动部分140、以及第二导线键合装置520。半导体封装制造装置500还可包括卸载部分170。第一和第二导线键合装置510和520中每一个包括引导轨120和导线键合部分130。由于加载部分110、引导轨120、导线键合部分130、框架驱动部分140、晶片台150、晶片仓加载部分160和卸载部分170与图4~13中所示的相同,因此这里省略对它们的详细描述。此外,第一和第二导线键合装置510和520具有相同的结构。
在半导体封装制造装置500中,加载部分100向第一导线键合装置510提供宽引线框架70。第一导线键合装置510在宽引线框架70上表面的一半部分中形成导线键合232。然后,在框架驱动部分140中将宽引线框架70绕其上表面的法向旋转,并将其提供给第二导线键合装置520。第二导线键合装置520形成宽引线框架70与宽引线框架70上表面上由于未形成导线键合232而并没有电连接到宽引线框架70的所有半导体芯片210之间的导线键合232。通过卸载部分170将针对全部半导体芯片210形成了导线键合232的宽引线框架70取出。
可选地,半导体芯片封装制造装置可通过串行连接多个导线键合装置来配置,其中每个导线键合装置包括引导轨120和导线键合部分130,从而执行导线键合处理。
此外,虽然在附图中并没有示出,但是包括引导轨120和导线键合部分130的导线键合装置、加载部分110、框架驱动部分140和卸载部分170可按需组合,以配置多种类型的半导体封装制造装置。例如,可通过顺序组合具有卸载功能的加载部分110、第一导线键合装置510、具有旋转功能的框架驱动部分140、第二导线键合装置520、以及具有翻转功能的框架驱动部分140,来配置半导体封装制造装置。在这种情况下,加载部分110提供宽引线框架70。通过第一导线键合装置510在宽引线框架70的第一表面的一半部分中形成导线键合232。通过第二导线键合装置520在第一表面的另一半部分中形成导线键合232。然后,通过具有翻转功能的框架驱动部分140,将宽引线框架70翻转,从而第一表面朝下。通过第二导线键合装置520在宽引线框架70的第二表面的一半部分中形成导线键合232。通过具有旋转功能的框架驱动部分140,将宽引线框架70旋转。通过第一导线键合装置510在第二表面的另一半部分中形成导线键合232。然后,通过具有卸载功能的加载部分110,卸载宽引线框架70。这样,可以在宽引线框架70的两个表面上完整地形成导线键合232。
在另一示例中,顺序连接具有卸载功能的加载部分、第一导线键合装置、具有旋转功能的第一框架驱动部分、第二导线键合装置、具有翻转功能的第二框架驱动部分、第三导线键合装置、具有旋转功能的第三框架驱动部分、第四导线键合装置、以及卸载部分,从而可在宽引线框架70的两个表面上完整地形成导线键合232。
虽然在以上描述中,通过对附接至宽引线框架的一层半导体芯片进行导线键合,来将半导体芯片电连接到宽引线框架,但是本发明不局限于此。例如,本发明可应用于多芯片封装技术,用于将多个半导体芯片分层附接在宽引线框架上。也就是说,本发明可应用于如下情况:通过形成导线键合,将形成一层的多个半导体芯片与宽引线框架彼此电连接,然后在该层上附接其他半导体芯片,形成另一层。
根据本发明的半导体封装制造装置和方法,可在保持高精度的同时以相对低的成本对宽引线框架执行导线键合处理。因此,可以节省原材料成本,并可提升产率。此外,在宽引线框架的导线键合过程中,由于宽引线框架无需由操作工手动翻转,所以可缩短工时,并可减少缺陷。
另外,由于可以根据所需半导体封装的类型(例如,多芯片封装或双面封装)来自由调整装置的配置,所以无论产品或封装技术如何改变,都可有效使用该装置,并可以快速响应市场上的变化。
尽管已经参照本发明的示例性实施例具体示出和描述了本发明,但是本领域技术人员应理解,不脱离所附权利要求所限定的本发明的精神和范围,可以对这些实施例进行形式和细节上的各种改变。
Claims (20)
1.一种用于制造半导体封装的装置,该装置包括:
引导轨,沿正向和反向传送引线框架,该引线框架具有第一表面以及与第一表面相对的第二表面;
加载部分,连接到引导轨的端部,向引导轨提供引线框架;
框架驱动部分,连接到引导轨的所述端部的相对端部,绕第一表面的法向旋转引线框架;和
导线键合部分,使用导线键合,将引线框架与附接到提供给引导轨的引线框架上的半导体芯片电连接。
2.如权利要求1所述的装置,其中,导线键合部分包括:
键合头,具有键合换能器,使用导线,将引线框架与附接至引线框架的半导体芯片连接;和
传送模块,在引导轨之上传送键合头。
3.如权利要求2所述的装置,其中,传送模块使键合头在引导轨的宽度方向上从引导轨在宽度方向的一端至少移动到引导轨的宽度中心位置。
4.如权利要求1所述的装置,还包括卸载部分,该卸载部分连接到框架驱动部分,以将引线框架取出到装置外部,其中,框架驱动部分根据引线框架的状态,选择性地将引线框架传送到卸载部分,或将引线框架返回引导轨。
5.如权利要求1所述的装置,其中,为了绕第一表面的法向旋转引线框架,框架驱动部分包括:
框架加载轨,支撑引线框架;
旋转台,支撑框架加载轨;
旋转轴,在沿第一表面法向的方向,连接到旋转台;和
旋转驱动装置,向旋转轴提供旋转驱动力。
6.如权利要求5所述的装置,其中,框架加载轨支撑引线框架,使得框架驱动部分一次旋转一个引线框架。
7.如权利要求1所述的装置,其中,框架驱动部分将引线框架旋转180°。
8.如权利要求1所述的装置,其中,加载部分具有卸载功能,以将从引导轨传送来的引线框架取出到装置外部。
9.如权利要求1所述的装置,其中,框架驱动部分还包括翻转装置,该翻转装置将引线框架翻转,使得引线框架的第一和第二表面中朝上的一个表面朝下。
10.一种用于制造半导体封装的装置,该装置包括:
第一导线键合装置和第二导线键合装置,均包括沿正向和反向传送引线框架的引导轨、以及使用导线键合将引线框架与附接至引线框架的半导体芯片电连接的导线键合部分,其中该引线框架具有第一表面以及与第一表面相对的第二表面;
加载部分,连接到第一导线键合装置的端部,向第一导线键合装置提供引线框架;
卸载部分,连接到第二导线键合装置的端部,从第二导线键合装置取出引线框架;和
框架驱动部分,连接在第一和第二导线键合装置的端部中相对的端部之间,绕第一表面的法向旋转引线框架。
11.如权利要求10所述的装置,其中,导线键合部分包括:
键合头,使用金线,将引线框架与附接至引线框架的半导体芯片连接;和
传送模块,在引导轨之上传送键合头。
12.如权利要求11所述的装置,其中,键合头沿传送轨在引导轨的宽度方向上从引导轨在宽度方向的一端至少移动到引导轨的宽度中心位置。
13.如权利要求10所述的装置,其中,框架驱动部分根据引线框架的状态,选择性地将引线框架传送至第一导线键合装置或第二导线键合装置。
14.如权利要求13所述的装置,其中,框架驱动部分还包括翻转装置,该翻转装置将引线框架翻转,使得引线框架的第一和第二表面中朝上的一个表面朝下。
15.一种制造半导体封装的方法,该方法包括:
向导线键合部分提供引线框架,该引线框架具有第一表面以及与第一表面相对的第二表面,在第一表面上附接有多个半导体芯片,且第一表面朝上,其中沿第一方向移动引线框架;
在导线键合部分中,将引线框架与附接至引线框架的第一表面的一些半导体芯片电连接-第一导线键合操作;
绕第一表面的法向旋转引线框架;和
在导线键合部分中,将引线框架与附接至引线框架的第一表面、尚未进行导线键合的半导体芯片电连接-第二导线键合操作。
16.如权利要求15所述的方法,其中,在第一导线键合操作中,使用导线键合,将引线框架与引线框架第一表面上相对于第一表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该第一表面中心线沿第一方向延伸。
17.如权利要求15所述的方法,其中,在第二导线键合操作中,使用导线键合,将引线框架与引线框架第一表面上相对于第一表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该第一表面中心线沿第一方向延伸。
18.如权利要求15所述的方法,还包括:
翻转引线框架,使得引线框架的第二表面朝上,其中多个半导体芯片附接在第二表面上;
在导线键合部分中,将引线框架与附接至引线框架的第二表面的一些半导体芯片电连接-第三导线键合操作;
绕第二表面的法向旋转引线框架;和
在导线键合部分中,将引线框架与附接至引线框架的第一表面、尚未进行导线键合的半导体芯片电连接-第四导线键合操作。
19.如权利要求18所述的方法,其中,在第三导线键合操作中,使用导线键合,将引线框架与引线框架第二表面上相对于第二表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该第二表面中心线沿第一方向延伸。
20.如权利要求18所述的方法,其中,在第四导线键合操作中,使用导线键合,将引线框架与引线框架第二表面上相对于第二表面中心线的至少一半部分中所附接的所有半导体芯片电连接,其中该第二表面中心线沿第一方向延伸。
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CN103151277A (zh) * | 2012-12-31 | 2013-06-12 | 深圳市气派科技有限公司 | 一种提高集成电路封装中键合机台效率的方法 |
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KR100967526B1 (ko) * | 2008-04-25 | 2010-07-05 | 에스티에스반도체통신 주식회사 | 광폭 리드 프레임을 위한 반도체 패키지 제조 장치 및 이를이용한 반도체 패키지 제조 방법 |
KR101619782B1 (ko) * | 2015-04-14 | 2016-05-12 | 제엠제코(주) | 반도체 기판의 초음파 웰딩 접합 장치 |
CN105489531B (zh) * | 2015-12-09 | 2018-06-05 | 华南师范大学 | 一种cob固晶焊线系统和方法 |
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Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5815240A (ja) * | 1981-07-20 | 1983-01-28 | Hitachi Ltd | 半導体製造装置 |
JPS59172731A (ja) * | 1983-03-22 | 1984-09-29 | Toshiba Corp | リ−ドフレ−ム搬送装置 |
DE3701652A1 (de) * | 1987-01-21 | 1988-08-04 | Siemens Ag | Ueberwachung von bondparametern waehrend des bondvorganges |
JPH0513517A (ja) | 1991-07-08 | 1993-01-22 | Hitachi Ltd | ワイヤボンデイング装置及びワイヤボンデイング方法 |
US5238174A (en) * | 1991-11-15 | 1993-08-24 | Kulicke And Soffa Investments, Inc. | Smart indexing head for universal lead frame work station |
JP3178567B2 (ja) * | 1993-07-16 | 2001-06-18 | 株式会社カイジョー | ワイヤボンディング装置及びその方法 |
US5465899A (en) * | 1994-10-14 | 1995-11-14 | Texas Instruments Incorporated | Method and apparatus for fine pitch wire bonding using a shaved capillary |
KR100208481B1 (ko) | 1996-07-30 | 1999-07-15 | 구본준 | 반도체 리드프레임 로딩장치 |
KR100199293B1 (ko) * | 1996-11-08 | 1999-06-15 | 윤종용 | 반도체 패키지 제조 장치 |
JPH10303241A (ja) | 1997-04-30 | 1998-11-13 | Toshiba Corp | ワイヤボンダー |
US6827247B1 (en) * | 1999-12-08 | 2004-12-07 | Asm Technology Singapore Pte Ltd. | Apparatus for detecting the oscillation amplitude of an oscillating object |
JP3176599B2 (ja) | 1999-12-22 | 2001-06-18 | エヌイーシーマシナリー株式会社 | ダイボンダ |
JP2002164361A (ja) | 2000-11-29 | 2002-06-07 | Mitsubishi Electric Corp | 半導体製造装置および半導体製造方法 |
US6705001B2 (en) * | 2001-11-28 | 2004-03-16 | Asm Technology Singapore Pte Ltd. | Apparatus for assembling integrated circuit packages |
KR100524974B1 (ko) | 2003-07-01 | 2005-10-31 | 삼성전자주식회사 | 양면 스택 멀티 칩 패키징을 위한 인라인 집적회로 칩패키지 제조 장치 및 이를 이용한 집적회로 칩 패키지제조 방법 |
JP2006140329A (ja) * | 2004-11-12 | 2006-06-01 | Renesas Technology Corp | 半導体装置の製造方法 |
US7568606B2 (en) * | 2006-10-19 | 2009-08-04 | Asm Technology Singapore Pte Ltd. | Electronic device handler for a bonding apparatus |
KR100967526B1 (ko) * | 2008-04-25 | 2010-07-05 | 에스티에스반도체통신 주식회사 | 광폭 리드 프레임을 위한 반도체 패키지 제조 장치 및 이를이용한 반도체 패키지 제조 방법 |
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