CN101577278B - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN101577278B
CN101577278B CN2008101751290A CN200810175129A CN101577278B CN 101577278 B CN101577278 B CN 101577278B CN 2008101751290 A CN2008101751290 A CN 2008101751290A CN 200810175129 A CN200810175129 A CN 200810175129A CN 101577278 B CN101577278 B CN 101577278B
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CN101577278A (zh
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张正宏
余振华
叶震南
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体结构及其形成方法，该结构包括一半导体衬底，一平面晶体管，位于半导体衬底的第一部分，其中半导体衬底的第一部分具有第一上表面。一多栅晶体管，位于半导体衬底的第二部分。半导体衬底的第二部分从第一上表面凹入，以形成多栅晶体管的鳍状物，且鳍状物借助一绝缘物与半导体衬底电性隔离。本发明降低了鳍式场效应晶体管的击穿电流、改善了鳍式场效应晶体管的载流子迁移率、以及降低了制作成本。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体元件，且尤其涉及一种鳍式场效应晶体管(Finfield-effect transistor；FinFET)结构及其制法。
背景技术
为了配合集成电路持续的微缩化，业界发展出所谓的鳍式场效应晶体管(FinFET)以获得更高的驱动电流与更小的尺寸。图1与图2显示传统鳍式场效应晶体管的立体图。鳍状物4为从衬底2延伸而上的垂直硅鳍，用来形成源极/漏极区6与两者之间的沟道区(未显示)。垂直栅极8与鳍状物4的交叉处具有沟道区。虽然图1与图2未显示，但实际上在沟道区与垂直栅极8之间尚包括一栅极介电层。鳍状物4的两端经过源极/漏极掺杂后具有导电性。
图1所示的结构为绝缘层上覆硅(Silicon on Insulator，SOI)的鳍式场效应晶体管，所使用的SOI衬底包括半导体衬底2、氧化埋层10、以及一覆硅层。此覆硅层经过图案化后形成鳍状物4，之后便在鳍状物4上制作鳍式场效应晶体管。虽然SOI鳍式场效应晶体管具有优异的电性，但制作成本较高。
图1所示的结构为块材(bulk)鳍式场效应晶体管，所使用的衬底为硅衬底块材(bulk silicon substrate)。块材鳍式场效应晶体管的制作成本低于SOI鳍式场效应晶体管。然而击穿电流(漏电流)可能出现在栅极8无法控制的区域，如图3的区域12所示，其中图3为图2中沿A-A’剖线所形成的剖面图。传统上，为了降低击穿电流(punch through current)，是以高能量对区域12进行高浓度的掺杂，例如1019/cm3，其中掺杂物的导电形态与源极/漏极区的导电形态相反。上述掺杂步骤是在鳍状物4形成后、栅极8形成前进行，因此整个鳍状物4都会被掺杂。虽然该方法此用高掺杂浓度可以降低击穿电流，但却导致载流子迁移率(carrier mobility)的下降。此外，该结构的鳍状物高度会受到STI上表面的位置影响，但此位置会随着后续制造工艺的数次清洗步骤而有各种差异。因此鳍状物的高度差非常大，最后造成元件性能的差异。
图4～图6显示另一种公知的鳍式场效应晶体管。在图4中，氮化条(nitridestrip)18形成在硅衬底16上，用来凹蚀(recessing)硅衬底16以形成鳍状物20。在图5中，形成氮化间隙壁24以覆盖鳍状物20的侧壁。之后，进行氧化以形成场氧化物26，如图6所示。鳍状物20的顶部在氧化时被保护住，且借助场氧化物26与硅衬底16电性隔离。形成在鳍状物20上的鳍式场效应晶体管没有击穿电流的问题，这点与SOI鳍式场效应晶体管类似。此外，尽管场氧化物26的上表面可能会因为后续制造工艺而降低，鳍状物20的高度并不会受到后续制造工艺的影响。然而，形成在同一半导体芯片上的平面式晶体管(planar transistor)却没有良好的隔离性能。
因此，业界急需一种鳍式场效应晶体管的结构与制作方法，其除了具有高驱动电流的优点外，同时又能克服公知技术的缺点。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，以改善公知技术的缺点。
本发明提供一种半导体结构，包括：一半导体衬底；一平面晶体管，位于该半导体衬底的第一部分，其中该半导体衬底的第一部分具有第一上表面；一多栅晶体管，位于该半导体衬底的第二部分，其中该半导体衬底的第二部分从该第一上表面凹入，以形成该多栅晶体管的鳍状物，且该鳍状物借助一绝缘物与该半导体衬底电性隔离。
本发明又提供一种半导体结构，包括：一半导体衬底，其包含一块材部分；一半导体鳍状物位于该块材部分上。该半导体鳍状物具有第一宽度，且与该半导体衬底为相同材料。该半导体结构还包括一绝缘物将该半导体鳍状物分成电性隔离的顶部与底部，其中该底部与该半导体衬底实体连接。
本发明还提供一种半导体结构，包括：一半导体衬底；一隔离区，位于该半导体衬底上且具有一下表面，其中该隔离区包括第一部分与第二部分，其中第二部分的第二上表面低于第一部分的第一上表面；一第一有源区，邻接该隔离区的第一部分，其中该第一有源区的上表面大抵与该第一上表面齐平；一第二有源区，邻接该隔离区的第二部分，其中该第二有源区的上表面高于该第二上表面；一绝缘物，将该第二有源区隔成电性隔离的顶部与底部；一平面晶体管，位于该第一有源区；以及一多栅晶体管，以该第二有源区的顶部作为源极/漏极区与沟道区。
本发明也提供一种半导体结构的形成方法，包括：提供一半导体衬底；形成一隔离区于该半导体衬底中，其中该隔离区围绕一有源区；凹蚀该隔离区的顶部以露出该有源区的侧壁；于该有源区的上表面与该隔离区的下表面之间，氧化该有源区的中间区域以形成一绝缘物，将该有源区分成顶部与底部。
本发明又提供一种半导体结构的形成方法，包括：提供一半导体衬底；形成多个具有第一高度的绝缘区，上述绝缘区定义一有源区；凹蚀上述绝缘区以露出该有源区的侧壁；形成一硬掩模以覆盖该有源区，其中该硬掩模露出部分绝缘区；凹蚀绝缘区露出的部分以露出该有源区的侧壁；以及，氧化该有源区露出的侧壁以形成一绝缘物，将该有源区的顶部与半导体衬底完全隔离。
本发明还提供一种半导体结构的形成方法，包括：提供一半导体衬底，其包含一平面元件区与一鳍式场效应晶体管区；形成多个绝缘区以在该平面元件区定义出第一有源区，且在该鳍式场效应晶体管区定义出第二有源区；对上述绝缘区进行第一凹蚀以露出第二有源区的侧壁，其中第一有源区的侧壁保持未露出；形成一硬掩模以覆盖第二有源区的露出侧壁；对上述绝缘区露出的部分进行第二凹蚀以露出硬掩模下第二有源区的侧壁；以及，氧化第二有源区露出的侧壁以形成一绝缘物，将第二有源区的顶部与半导体衬底隔离。
本发明的优点包括降低鳍式场效应晶体管的击穿电流、改善鳍式场效应晶体管的载流子迁移率、以及低制作成本。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合附图，作详细说明如下：
附图说明
图1显示一形成在SOI衬底上的传统鳍式场效应晶体管。
图2显示一形成在块材衬底上的传统鳍式场效应晶体管。
图3为图2所示的鳍式场效应晶体管的剖面示意图。
图4～图6为一系列剖面图，用以说明公知鳍式场效应晶体管的制作流程。
图7～图21为一系列剖面图，用以说明本发明第一实施例的制作流程，其包括平面晶体管与鳍式场效应晶体管。
图22为第一实施例所形成的平面晶体管与鳍式场效应晶体管的立体图。
图23～图33为一系列剖面图，用以说明本发明第二实施例的制作流程，其包括平面晶体管与鳍式场效应晶体管。
图34为第二实施例所形成的平面晶体管与鳍式场效应晶体管的立体图。
图35～图38为一系列剖面图，用以说明击穿停止区的制作流程。
图39～图41为一系列剖面图，用以说明击穿停止区的另一种制作流程。
图42为一剖面图，其显示因图案密度不同而造成击穿停止区具有不同的位置。
其中，附图标记说明如下：
2～衬底                 4～鳍状物
6～源极/漏极区          8～垂直栅极
10～氧化埋层            12～区域
16～硅衬底              18～氮化条
20～鳍状物              26～场氧化物
30～半导体衬底          32～垫层
34～掩模层              36～光致抗蚀剂
38～开口                39～介电材料
40～浅沟槽隔离(STI)区   42～光致抗蚀剂
46～缓冲氧化物          48～硬掩模
50～凹孔                52～击穿停止区
52’～底切氧化区        53～击穿停止区的顶部
56～氧化物              57～硬掩模的剩余部分
58～光致抗蚀剂          60～交接处
62～开口                64～区域
100～有源区             110～平面式晶体管
112～栅极堆叠           200～鳍状物
210～鳍式场效应晶体管   212～栅极堆叠
300、400、500～区域
具体实施方式
以下提供平面式晶体管与鳍式场效应晶体管(也称为多栅晶体管或三栅晶体管)的集成电路制造工艺，并说明本发明一优选实施例与变化例的中间步骤。在各图示与实施例中，类似的元件将以类似的符号标示。
请参照图7，提供一半导体衬底30。在优选实施例中，半导体衬底30为块材(bulk)硅衬底。半导体衬底30中也可包含其他常用的材料，例如碳、锗、镓、砷、氮、铟、磷等。半导体衬底30可为单晶或化合物材料，且可包括一外延层。
在半导体衬底30上形成垫层32与掩模层34。垫层32优选为一热工艺所形成的薄膜，因此包含氧化硅。垫层32可用来缓冲半导体衬底30与掩模层34之间的应力，并可作为蚀刻掩模层34时的蚀刻停止层。在优选实施例中，掩模层34为低压化学气相沉积法(LPCVD；Low Pressure Chemical VaporDeposition)所形成的氮化硅。在其他实施例中，掩模层34可由硅的热氮化工艺、等离子体加强化学气相沉积法(PECVD；Plasma Enhanced CVD)、或使用氮气-氢气的等离子体阳极氮化所形成。掩模层34的厚度约60nm～120nm。应注意的是，本说明书所提到的尺寸仅为举例说明，实际尺寸可随着所使用的工艺技术而改变。
请参照图8，在掩模层34上形成光致抗蚀剂36，并经过图案化在光致抗蚀剂36中形成开口38。沿着开口38对掩模层34与垫层32进行蚀刻以露出下方的半导体衬底30。接着，蚀刻半导体衬底30因而使开口38延伸进入半导体衬底30中。在一实施例中，半导体衬底30凹蚀的深度D1约100nm～300nm。
在优选实施例中，如图9所示，将介电材料39填入开口38中。介电材料39优选是次压化学气相沉积法(SACVD；Sub-Atmosphere CVD)所形成的氧化硅。在其他实施例中，介电材料39是由高密度等离子体化学气相沉积法(HDPCVD；High Density Plasma CVD)或旋涂式玻璃(SOG)所形成。接着，以化学机械研磨(CMP)对晶片表面进行平坦化以形成浅沟槽隔离(STI)区40，如图10所示。掩模层34可作为CMP停止层。浅沟槽隔离区40定义出用来形成平面式晶体管的有源区100以及用来形成鳍式场效应晶体管的有源区200。在一实施例中，有源区100的宽度W’与有源区200的宽度W1的比值大于1。
请参照图11，在有源区100与其周围的STI区40上形成光致抗蚀剂42，但露出有源区200与其周围的STI区40。之后，对露出的浅沟槽隔离区40进行凹蚀，使得部分的有源区200高出周围的STI区40，而此部分的有源区200又称为鳍状物200。凹蚀的距离D2例如是介于约30～90nm。去除光致抗蚀剂42后，在氢气环境下进行回火，其温度例如是约850～1050℃。氢气回火步骤会造成硅原子的迁移，使鳍状物200露出的侧壁平滑化。
请参照图12，进行氧化步骤以在鳍状物200的侧壁形成缓冲氧化物46，其厚度约2～6nm，形成温度约650～1050℃。接着如图13所示，形成硬掩模48，其材料也可为氮化硅，其厚度例如约10～50nm。形成硬掩模48可包括LPCVD、PECVD等，形成例如约400～900℃。
请参照图14，进行干蚀刻以去除硬掩模48的水平部分，留下垂直的部分并露出STI区40。接着，进行一湿蚀刻(或其他的各向同性蚀刻)，如图15所示。在一实施例中，湿蚀刻是使用HF与NH4F的混合溶液，其具有约20：1的SiO2/SiN选择比。因此，硬掩模48的剩余部分实质上仍保持未蚀刻。由于湿蚀刻为各向同性，因此凹孔50会延伸到硬掩模48剩余部分的下方，并露出鳍状物200的侧壁。
请参照图16，进行氧化步骤将鳍状物200露出的侧壁进一步氧化而形成氧化区52。优选地，形成在鳍状物200相对侧壁的氧化区52相互连结而使得鳍状物200的顶部与衬底30完全隔离。此外，氧化区52也可以是实质上(虽然不是完全)隔离鳍状物200顶部与衬底30。由于氧化造成体积增加，氧化区52的宽度W2约为鳍状物200宽度W1的两倍到三倍。应注意的是，宽度W2大小取决于氧化区52的含氧量以及工艺条件。STI区40的高度D1与氧化区52的高度H比约1.4～30。氧化区52可用来阻止击穿电流，因此也可称为击穿停止区。如图16所示，鳍状物200的底部可能位于氧化区52的下方，且仍未氧化。有利的是，即使鳍状物200周围的STI区40的上表面高度因为后续的清洁步骤而降低，鳍状物200的高度仍维持固定(其独立于STI区40的上表面高度)，因此可使得鳍式场效应晶体管有更稳定的性能。在一实施例中，鳍状物200的高度约30～90nm。
请参照图17，以氧化物56填入凹孔50，直到氧化物56的上表面超过掩模层34的上表面。在优选实施例中，氧化物56可使用旋涂式玻璃(SOG)，因为其具有良好的填沟能力。除此之外，也可使用其他具有良好填沟能力的方法，例如SACVD或HDPCVD来形成氧化物56。之后以CMP去除多余的氧化物56直到露出掩模层34，其中掩模层34作为CMP停止层。最后所得的结构如图18所示。
请参照图19，在有源区上形成光致抗蚀剂58，凹蚀鳍状物200周围的氧化物56。蚀刻优选停在鳍状物200的底部，或位于鳍状物200底部上方不超过约20nm的任何位置。在图20与图21中，去除残余的硬掩模34、48，并去除缓冲氧化物46，所得的结构如图21所示，其中有源区100可用来形成平面式晶体管，鳍状物200可用来形成鳍式场效应晶体管。有利的是，鳍状物200完全与衬底30电性隔离。
之后，如图22所示，形成平面式晶体管与鳍式场效应晶体管的栅极堆叠。栅极堆叠可用公知的栅极优先(gate-first)或栅极最后(gate-last)方式形成。所形成的平面式晶体管110与鳍式场效应晶体管210如图22所示。以下将简要说明形成栅极堆叠的工艺。应注意的是，在后续步骤中，击穿停止区52的顶部53(图21中虚线部分)可能会被清洗步骤所使用的酸去除，使得鳍式场效应晶体管的栅极有一部分位于鳍状物200的边缘下方，而形成一奥米加(Omega)晶体管。
在栅极优先的工艺中，形成图21的结构之后，进行阱区注入以掺杂有源区100与鳍状物200，其中所用的掺杂物与源极/漏极的导电形态相反。接着形成栅介电层与栅极层(未显示)，其中栅介电层例如是高介电常数材料，而栅极层可为金属、金属硅化物、多晶硅、金属氮化物等。将栅介电层与栅极层图案化后形成栅极堆叠112与栅极堆叠212。之后，形成轻掺杂源极/漏极(LDD)区，并形成栅极间隔物(未显示)。对露出的有源区100与鳍状物200进行注入与回火以形成源极/漏极区。形成硅化物(未显示)后，依序形成接触蚀刻停止层、内层介电层、与接触插塞(也未显示)，其制造工艺皆为公知技术，在此不予赘述。
在栅极最后的工艺中，形成图21的结构之后，进行阱区注入以掺杂有源区100与鳍状物200，其中所用的掺杂物与源极/漏极的导电形态相反。接着形成闲置栅极(dummy gate)，优选为多晶硅。之后，形成轻掺杂源极/漏极(LDD)区与栅极间隔物(未显示)。对露出的有源区100与鳍状物200进行注入与回火以形成源极/漏极区。形成源极/漏极硅化物(未显示)后，依序形成接触蚀刻停止层、内层介电层。研磨内层介电层露出闲置栅极后，蚀刻闲置栅极，并以具有适当功函数的含金属栅极取代闲置栅极。之后，形成接触插塞。
图23～图33显示本发明另一实施例的制造工艺剖面图。除非特别说明，否则本实施例的材料与元件的形成方法基本上与图7～图21所示的实施例相同。本实施例的起始步骤基本上与图7～图10相同。请参照图23，凹蚀STI区40，其凹蚀的深度基本上同图11所示。此凹蚀步骤并未使用光致抗蚀剂或其他掩模。另外，也可形成光致抗蚀剂(未显示)以覆盖用来形成平面式晶体管及鳍式场效应晶体管以外的所有区域。如此一来，露出有源区100、200的侧壁。在图24中，优选借助热氧化法形成缓冲氧化物46。接着，如图25、图26所示，形成硬掩模48，并以干蚀刻去除其水平部分，剩余的硬掩模48覆盖有源区100、200的侧壁(其中缓冲氧化物46介于硬掩模48与有源区100、200之间)。
接着，如图27所示，进行各向同性蚀刻，优选为湿蚀刻，去除STI区40的顶部，以露出有源区100、200的侧壁。在图28中，进行氧化步骤以形成击穿停止区52与底切氧化区52’。同样的，击穿停止区52最好完全使鳍状物200与衬底30电性隔离。另一方面，由于有源区100比鳍状物200更宽，因此有源区100相对侧壁的底切氧化区52’并未互相连结。
请参照图29，形成氧化物56覆盖于衬底30上，并将之平坦化直到露出硬掩模48的上表面，如图30所示。在图31中，以如同图19的方式，凹蚀氧化物56。接着去除硬掩模34、48，如图32所示。去除垫层32后，得到图33所示的结构。形成栅极堆叠与源极/漏极区后，所得的结构立体图如图34所示。应注意的是，此实施例在氧化物56中留下硬掩模48的剩余部分57(也称为应力源57，也参照图33)。应力源57围绕有源区100而形成一环形，如图34所示。应力源57与有源区100之间以缓冲氧化物46隔开。
图35～图38显示形成击穿停止区52的另一实施例。本实施例的起始步骤基本上与图7～图13相同。图35显示图13中右侧的结构。一般而言，由于工艺上的因素，硬掩模48的垂直部分与水平部分的交接处60比起其他部分有更多的孔隙，因此可利用各向同性蚀刻来去除。如图36所示，在硬掩模48的垂直部分与水平部分被完全蚀刻之前会先形成开口62而露出缓冲氧化物46。之后进行氧化步骤，例如干式氧化，以形成图37的结构，其中击穿停止区52靠近开口62。之后如图38所示，去除硬掩模48。剩余的工艺步骤基本上同图21所示。
图39～图41显示形成击穿停止区52的再一实施例。本实施例的起始步骤基本上与图7～图13及图35、图36相同。接着，如图39所示，将氧离子注入开口62中。此离子注入最好具有一倾斜角，使得氧离子穿过开口62与缓冲氧化物46，注入到有源区200。图40显示区域64中具有集中的氧离子，且硬掩模48已被去除。接着，如图41所示，进行干式氧化(或回火)，可在无氧或有氧的环境下进行。在干式氧化(或回火)期间，区域64中的氧离子与有源区200中的硅反应，形成击穿停止区52。
应注意的是，前述实施例与STI区40的制造工艺相关。如本领域所熟知，STI区40的密度会影响凹蚀步骤的效率，如图11的步骤。此外，各种清洗程序也可能影响到STI区40的去除速率，进而影响鳍状物200的高度。因此，在图案密集区与图案疏离区中，STI区40的上表面并非等高。图42显示三个区域300、400、500，相对于区域300，区域400具有较高的图案密度，因此其间隔(pitch)P2小于区域300的间隔P1。另一方面，相对于区域300，区域500具有较低的图案密度，因此其间隔(pitch)P3大于区域300的间隔P1。不同的图案密度会造成STI区40的上表面有不同程度的差异，并导致击穿停止区52的位置有所差别。区域400的STI区40的上表面与击穿停止区52的位置相对于区域300较低，而区域500的STI区40的上表面与击穿停止区52的位置相对于区域300较高。由于击穿停止区52的位置会影响鳍状物200的高度，因此鳍状物200的高度差在设计时需纳入考虑。
本发明的实施例具有许多优点，由于形成了击穿停止区52，其将源极/漏极区与可能的击穿电流路径完全隔离，因此本发明实施例所形成的鳍式场效应晶体管可减少，甚至完全消除击穿电流的问题，而且其制造工艺并不需要使用昂贵的SOI衬底。此外，其沟道区并不需要高掺杂(阱区)浓度，且鳍状物的高度不会随着STI区的上表面高度而变化，这使得鳍式场效应晶体管的性能差异性较小。再者，鳍式场效应晶体管的制造工艺完全与平面式晶体管的制造工艺相容。
虽然本发明已以数个优选实施例揭示如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。

Claims (14)

1.一种半导体结构，包括：
一半导体衬底；
一平面晶体管，位于该半导体衬底的第一部分，其中该半导体衬底的第一部分具有第一上表面；以及
一多栅晶体管，位于该半导体衬底的第二部分，其中该半导体衬底的第二部分从该第一上表面凹入，以形成该多栅晶体管的鳍状物，且该鳍状物借助一绝缘物与该半导体衬底电性隔离，其中该绝缘物将该鳍状物与其下方的一额外鳍状物电性隔离，且其中该鳍状物与该额外的鳍状物为同一鳍状物的不同部分。
2.如权利要求1所述的半导体结构，其中该多栅晶体管为一鳍式场效应晶体管。
3.如权利要求1所述的半导体结构，其中该多栅晶体管为一奥米加场效应晶体管。
4.如权利要求1所述的半导体结构，还包括一底切氧化区，位于该平面晶体管的一有源区的上表面下方，其中该底切氧化区延伸至该有源区的侧壁，且该底切氧化区并未隔离该有源区与该半导体衬底。
5.如权利要求1所述的半导体结构，其中该鳍状物具有一第二上表面与该第一上表面齐平。
6.如权利要求1所述的半导体结构，还包括第一组多栅晶体管，其具有第一间隔，以及第二组多栅晶体管，其具有大于第一间隔的第二间隔，且第一组多栅晶体管的鳍状物高度大于第二组多栅晶体管的鳍状物高度。
7.如权利要求1所述的半导体结构，还包括：
一应力源区，其围绕该平面晶体管的一有源区而形成一环形；
一缓冲氧化物，介于该应力源区与该平面晶体管的有源区之间；以及
一隔离区，围绕该应力源区，其中该隔离区与该应力源区由不同材料形成。
8.如权利要求1所述的半导体结构，其中该绝缘物具有不均匀的厚度。
9.一种半导体结构，包括：
一半导体衬底；
一隔离区，位于该半导体衬底上且具有一下表面，其中该隔离区包括第一部分与第二部分，其中第二部分的第二上表面低于第一部分的第一上表面；
一第一有源区，邻接该隔离区的第一部分，其中该第一有源区的上表面与该第一上表面齐平；
一第二有源区，邻接该隔离区的第二部分，其中该第二有源区的上表面高于该第二上表面；
一绝缘物，将该第二有源区隔成电性隔离的顶部与底部，该顶部与底部为同一鳍状物的不同部分；
一平面晶体管，位于该第一有源区；以及
一多栅晶体管，以该第二有源区的顶部作为源极/漏极区与沟道区。
10.如权利要求9所述的半导体结构，还包括一底切氧化区，低于该第一有源区的上表面，其中该底切氧化区延伸至该第一有源区的侧壁，且该底切氧化区并未隔离该第一有源区与该半导体衬底。
11.如权利要求9所述的半导体结构，还包括：
一氮化硅环，围绕该第一有源区，且该氮化硅环邻接该隔离区的第一部分；以及
一缓冲氧化物，介于该氮化硅环与第一有源区之间。
12.一种半导体结构的形成方法，包括：
提供一半导体衬底；
形成一隔离区于该半导体衬底中，其中该隔离区围绕一有源区；
凹蚀该隔离区的顶部以露出该有源区的侧壁；以及
于该有源区的上表面与该隔离区的下表面之间，氧化该有源区的中间区域以形成一绝缘物，将该有源区分成顶部与底部，该顶部与底部为同一鳍状物的不同部分。
13.如权利要求12所述的半导体结构的形成方法，其中氧化该有源区的步骤包括：
形成一掩模层覆盖该有源区的顶部侧壁；
蚀刻该隔离区的顶部以露出该有源区未被该掩模层覆盖的侧壁；以及
氧化该有源区露出的侧壁以形成该绝缘物。
14.如权利要求12所述的半导体结构的形成方法，其中在氧化该有源区之前还包括：
毯覆性地沉积一掩模层；
去除该掩模层的垂直部分与水平部分的交接处，以形成一开口，其中该垂直部分位于该有源区的侧壁；以及
经由该开口注入氧离子至该有源区的中间区域。
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