CN101594189B - Transmission method and receiving device of frame synchronizing signal - Google Patents
Transmission method and receiving device of frame synchronizing signal Download PDFInfo
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- CN101594189B CN101594189B CN200810067475A CN200810067475A CN101594189B CN 101594189 B CN101594189 B CN 101594189B CN 200810067475 A CN200810067475 A CN 200810067475A CN 200810067475 A CN200810067475 A CN 200810067475A CN 101594189 B CN101594189 B CN 101594189B
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- synchronizing signal
- frame synchronizing
- sampling head
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Abstract
The invention discloses a transmission method and a receiving device of a frame synchronizing signal. The transmission method comprises the following steps: (A) a main control board generates a synchronizing clock and a frame synchronizing signal to be sent to each single board; (B) after each single board receives the synchronizing clock and the frame synchronizing signal, the synchronizing clock is used as a work clock, at least one sampling head is realized, and the sampling head for most stable sampling for the frame synchronizing signal is selected; and (C) each single board samples the frame synchronizing signal according to the selected sampling head and tracks the sampling head. The invention keeps the external synchronous transmission mode and the topological structure of the synchronizing clock and the frame synchronizing signal to realize the simplicity of the system, does not depend on hardware wiring and the individual performance of each apparatus to reduce the design difficulty and the cost of the hardware, can quickly track frame synchronizing signals of various change periods to automatically adapt different frame period time and synchronizing time, and has the advantages of higher flexibility and universality, easy realization and high reliability.
Description
Technical field
The present invention relates to communication field, relate in particular to a kind of transmission method and receiving system of frame synchronizing signal.
Background technology
In communication system; It is synchronous that system may carry out timing to each sub-systems through a frame synchronizing signal; And these subsystems possibly be to be in different printed substrates (PCB physically; Printed circuit board) goes up in the perhaps different machine frames, even be in the different rack unit, use backboard or cable to link to each other to each other.
Frame synchronizing signal is an one-period property signal, often need be accompanied by synchronised clock and between each layer machine frame of whole frame and each veneer, transmit.It is very high to the accuracy requirement in frame synchronizing signal cycle to be strict with synchronous system; Such as: in TD-SCDMA (tdd CDMA) system; Each frame period is 10ms, if synchronised clock is 61.44Mhz, then requires frame synchronizing signal to occur once 614400 clock cycle.
See also the transmission topology diagram of frame synchronizing signal shown in Figure 1 and synchronised clock, this figure is an example with the TD-SCDMA system, and frame synchronizing signal and synchronised clock produce on master control borad, and sends to each veneer of frame by master control borad.Wherein, frame synchronizing signal belongs to the signal in synchronised clock territory, and the cycle generation (10ms) according to fixing is accompanied by synchronised clock and sends to together on each veneer of frame.
At present, adopt the mode of control hardware wiring sequential to guarantee the reliability that frame synchronizing signal is sampled usually.In this method; If require shake is not appearred in the sampling of frame synchronizing signal, then must guarantee the settling time of the receiving device (possibly be programmable logic device (FPGA) or special-purpose succession circuit (ASIC)) that clock and frame synchronizing signal at receiving terminal can satisfy physics.The time-delay that transmitting terminal device Tco is arranged that this wherein need consider, the time-delay of starting to hold chip for driving, the time-delay of all path PCB, the time-delay of receiving terminal chip for driving; Time-delay of receiving chip Tsu or the like; The delay difference of the path length difference that also need consider between each layer machine frame or veneer, to transmit, each device batch, temperature effect or the like variable factor, sometimes even need to consider fiber optic stretch or the like problem.Under synchronised clock frequency condition with higher, if lean on hardware designs merely, then need stay enough allowances for above-mentioned all differences in the cycle at a synchronised clock, this is difficulty very, and required cost is also very high.
If do not use pure hardware designs to guarantee the cycle accuracy, the solution that adopts usually is:
Use coded system that frame synchronizing signal and synchronised clock are transmitted on same physical pathway, be called internal synchronization mode.The shortcoming of this mode be need be comparatively complicated and special-purpose codec unit, on the terseness of handling time-delay, system and overall cost, do not possess advantage.In this method, on each sub-systems, use the synchronised clock that transmits arrival to calculate the frame period separately, the frame synchronizing signal that main control unit sends is only kept watch on usefulness, not Direct Sampling as proofreading and correct.Because directly not use frame synchronizing signal, the shortcoming of this mode is to follow the tracks of the strict periodicity signal, can't follow the tracks of the frame synchronizing signal that the cycle changes, and tracking circuit must design separately with synchronised clock to the frame period of appointment, versatility is relatively poor.
It is thus clear that technology in the past has big, the defectives such as cost is high, complex design, versatility difference of the difficulty of realization when solving the frame synchronizing signal problem of transmission.
Summary of the invention
Technical problem to be solved by this invention provides a kind of transmission method and receiving system of frame synchronizing signal.
For solving the problems of the technologies described above, the present invention realizes through following technical scheme:
A kind of transmission method of frame synchronizing signal may further comprise the steps:
A, master control borad produce synchronised clock and frame synchronizing signal, send it to each veneer;
B, each veneer are work clock with said synchronised clock after receiving synchronised clock and frame synchronizing signal, realize at least one sampling head, and from wherein choosing the most stable sampling head of frame synchronizing signal sampling;
C, each veneer are sampled to said frame synchronizing signal according to selected sampling head, and this sampling head is followed the tracks of.
Wherein, in the said steps A, master control borad adopts external sync mode through bus-type or Star Network said synchronised clock and frame synchronizing signal to be sent to each veneer.
Wherein, said step B further comprises:
A, each veneer produce the pulse signal of a single clock cycle at the rising edge of frame synchronizing signal after receiving synchronised clock and frame synchronizing signal;
B, realize at least one sampling head, and choose one therein the most stable sampling head of frame synchronizing signal sampling according to said pulse signal.
Wherein, Said choosing method to the most stable sampling head of frame synchronizing signal sampling is: the difference of calculating sampling head of realizing in first frame period and the sampling head of realizing in each frame period afterwards; If in the predetermined threshold value scope, then choosing the sampling head of realizing in said first frame period, this difference is the most stable sampling head that frame synchronizing signal is sampled.
Wherein, among the said step C, each veneer is a certain amount of to obtain new sampling head with selected sampling head skew, constantly frame synchronizing signal is sampled at said new sampling head place.
Wherein, Among the said step C; Tracking to sampling head is: after said frame synchronizing signal is sampled; The difference of the sampling head of realizing in the sampling head of realizing in each frame period after calculating and first frame period is if this difference not in the predetermined threshold value scope, is then chosen new sampling head.
A kind of receiving system of frame synchronizing signal, this device is arranged in each veneer, comprises that rising edge extracts circuit, circulating sampling counter, sampling head selection circuit, sample circuit and tap tracking circuit;
Said rising edge extracts circuit, is used for after receiving synchronised clock and frame synchronizing signal, and with the synchronised clock work clock, behind the rising edge of frame synchronizing signal, produce the pulse signal of a single clock cycle;
Said circulating sampling counter is a work clock with the synchronised clock, is used for realizing at least one sampling head according to said pulse signal;
Said sampling head is selected circuit, is used for selecting the most stable sampling head of frame synchronizing signal sampling at said sampling head;
Said sample circuit is used for according to sampling head frame synchronizing signal being sampled;
Said tap tracking circuit is used for the selected the most stable sampling head of frame synchronizing signal sampling is followed the tracks of.
The present invention has following beneficial effect:
1) the present invention has kept the outer synchronous transfer module and the topological structure of synchronised clock and frame synchronizing signal, has realized the terseness of system;
2) the present invention does not rely on the individual performance of hardware wiring and each device, has reduced the design difficulty and the cost of hardware;
3) owing to adopted rising edge to extract circuit among the present invention; Is the pulse signal of a clock cycle through this circuit with the frame synchronizing signal unification of various wide level; Thereby the frame synchronizing signal that can follow the tracks of multiple period of change rapidly, can adapt to different time in frame period and lock in time automatically, have higher flexibility and versatility; And be easy to realize that reliability is high.
Description of drawings
Fig. 1 is the transmission topology diagram of frame synchronizing signal and synchronised clock;
Fig. 2 is the functional block diagram of the receiving system of frame synchronizing signal of the present invention;
Fig. 3 is the operation principle sketch map that rising edge extracts circuit in the receiving system of the present invention, and wherein Fig. 3 a is its functional block diagram, and Fig. 3 b is sampling shake sketch map;
Fig. 4 is the operation principle sketch map of circulating sampling counter in the receiving system of the present invention;
Fig. 5 is the operation principle sketch map of sample circuit in the receiving system of the present invention;
Fig. 6 is the output sketch map after the present invention samples to on-fixed periodic frame synchronizing signal.
Embodiment
To combine accompanying drawing and specific embodiment that the present invention is described in further detail below:
The present invention proposes a kind of transmission method of frame synchronizing signal, may further comprise the steps:
The first step: master control borad produces synchronised clock and frame synchronizing signal, and with synchronous circuit mode beyond it, is sent to each veneer that is positioned at each layer machine frame with bus-type or Star Network;
Second step: each veneer received frame synchronizing signal and synchronised clock are work clock with the synchronised clock, realize a plurality of sampling heads, and from wherein choosing the most stable sampling head of frame synchronizing signal sampling;
The 3rd step: each veneer is sampled to the frame synchronizing signal from master control borad according to selected sampling head, and to this sampling head tracking lock.
See also Fig. 2, the invention allows for a kind of device that is applied to the received frame synchronizing signal in the said method, this device is arranged in each veneer, comprising:
Rising edge extracts circuit, is used for after receiving synchronised clock and frame synchronizing signal, and with the synchronised clock work clock, behind the rising edge of frame synchronizing signal, produce the pulse signal of single clock cycle; This circuit can be the pulse signal of a clock cycle with the frame synchronizing signal unification of various wide level.
The circulating sampling counter is a work clock with the synchronised clock, is used for realizing a plurality of sampling heads according to the pulse signal that rising edge extraction circuit produces.
Sampling head is selected circuit, is used for selecting a tap the most stable to the frame synchronizing signal sampling, as can not bring shake at a plurality of sampling heads.
Sample circuit and tracking circuit are used for according to selected sampling head frame synchronizing signal being sampled, and this sampling head are followed the tracks of, and prevent the losing lock that the phase change of frame synchronizing signal itself causes.
To describe respectively the each several part of above-mentioned receiving system below:
Rising edge extracts circuit; See also Fig. 3, the receiving circuit that is in each veneer begins the place, forms (shown in Fig. 3 a) by some triggers and NAND gate; Use synchronised clock as work clock, behind the rising edge of frame synchronizing signal, produce the pulse signal of a single clock cycle.Because the difference of synchronised clock bang path and frame synchronizing signal bang path; May cause synchronised clock just in time to drop near the edge of frame synchronizing signal; Small clock phase shake, the pulse interval that can cause two frame periods to be extracted departs from strict 1 clock cycle of frame period (cycle).This situation is called the sampling shake, shown in Fig. 3 b.
The circulating sampling counter sees also Fig. 4, and this counter is a core component, is operated on the synchronised clock territory, is a preset circulation accumulator in cycle that overflows, it overflow the sum that the mould value is exactly a sampling head, each count value is all represented a sampling head.The result who when the circulation accumulator is N, frame synchronizing signal is sampled is exactly the sampled value of tap N.Such as, the accumulator of a 3bit of realization, count value then can realize 8 sampling heads altogether between 0 to 7, subsequent conditioning circuit can be sampled to frame synchronizing signal in any one tap of these 8 taps.
Circuit is selected in sampling, is a state machine circuit that is operated on the synchronised clock territory.This circuit at first writes down initial frame in the cycle, and the value of circulating sampling counter was labeled as a when rising edge extracted the pulse arrival; In ensuing several frame periods, write down the value b of new rising edge pulse due in circulating sampling counter then; Relatively a value and b value is poor, if this difference within several frame periods all less than a predetermined thresholding, can think that then the rising edge of frame synchronizing signal is just near circulating sampling Counter Value a.For example; In the sample sequence of one 8 tap; The initial frame cycle finds the rising edge pulse with tap 2 alignment; If preset thresholding is 2 taps, and next the rising edge pulse in several frame periods all is between tap 0 and the tap 4, can think that then the rising edge of frame synchronizing signal is near tap 2.
Sample circuit is used for according to selected sampling head frame synchronizing signal being sampled.See also Fig. 5; If the rising edge that sampling selection circuit has found frame synchronizing signal is just near circulating sampling Counter Value a; On a value, adding a side-play amount c so, suppose a+c=d, is moment of d frame synchronizing signal to be sampled at the circulating sampling counter; Can think reliably, the sampling shake can not occur.Such as in the sample sequence of one 8 tap, if found the rising edge pulse, can confirm so in tap 6, frame synchronizing signal to be sampled if add 4 tap deviants with tap 2 alignment, then can not produce the sampling shake.See also Fig. 6, this figure is depicted as the frame synchronizing signal sketch map of sample circuit to the frame synchronizing signal sampling back output of non-regular periods.
The tap tracking circuit; This circuit also can select the additional several states of state machine of circuit realize by the realization sampling head, after getting into lock-out state, and the value b of circulating sampling counter when state machine continuation detection rising edge extracts pulse arrival; And relatively the difference of b and a value whether within thresholding; If exceed thresholding, then need reappear the driving condition machine, select new sampling head.
Said method and device are compared with prior art; The low cost of outer Synchronous Transfer Mode and total linear topological structure and simple and reliable advantage have been kept; Avoided the delay difference and time domain shake of terminal sampling again, guaranteed that cycle of frame-synchronizing impulse of reception is accurate; Simultaneously can have very high flexibility to the frame synchronizing signal self adaptation in various cycles again.Expense then is on each veneer, to have increased some processing modules; Owing to tend to be with programming device on the veneer in the present communication system; And above-mentioned processing module is simple in structure, resource cost seldom, can be easily realize, so cost is lower by cpld or fpga; Another expense is exactly the delay difference that has increased the frame synchronizing signal between each veneer slightly; Though huge base station system is very harsh to the requirement of frame signal cycle accuracy; But because transmission path is long, delay inequality just exists originally, so often there has been handled mechanism in the prior art; This expense has only several clock cycle usually, and influence is little.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the transmission method of a frame synchronizing signal is characterized in that, may further comprise the steps:
A, master control borad produce to step clock and frame synchronizing signal, send it to each veneer;
B, each veneer are after receiving synchronised clock and frame synchronizing signal; With said synchronised clock is work clock; Realize at least one sampling head; And from wherein choosing the most stable sampling head of frame synchronizing signal sampling, wherein, said choosing method to the most stable sampling head of frame synchronizing signal sampling is: the difference of calculating sampling head of realizing in first frame period and the sampling head of realizing in each frame period afterwards; If in the predetermined threshold value scope, then choosing the sampling head of realizing in said first frame period, this difference is the most stable sampling head that frame synchronizing signal is sampled;
C, each veneer are sampled to said frame synchronizing signal according to selected sampling head, and this sampling head is followed the tracks of.
2. the transmission method of frame synchronizing signal as claimed in claim 1 is characterized in that, in the said steps A, master control borad adopts external sync mode through bus-type or Star Network said synchronised clock and frame synchronizing signal to be sent to each veneer.
3. the transmission method of frame synchronizing signal as claimed in claim 1 is characterized in that, said step B further comprises:
A, each veneer produce the pulse signal of a single clock cycle at the rising edge of frame synchronizing signal after receiving synchronised clock and frame synchronizing signal;
B, realize at least one sampling head, and choose one therein the most stable sampling head of frame synchronizing signal sampling according to said pulse signal.
4. the transmission method of frame synchronizing signal as claimed in claim 1; It is characterized in that; Among the said step C, each veneer is a certain amount of to obtain new sampling head with selected sampling head skew, constantly frame synchronizing signal is sampled at said new sampling head place.
5. the transmission method of frame synchronizing signal as claimed in claim 1; It is characterized in that; Among the said step C, be to the tracking of sampling head: after said frame synchronizing signal is sampled, the difference of the sampling head of realization in the sampling head of realizing in each frame period after calculating and first frame period; If this difference not in the predetermined threshold value scope, is then chosen new sampling head.
6. the receiving system of a frame synchronizing signal is characterized in that, this device is arranged in each veneer, comprises that rising edge extracts circuit, circulating sampling counter, sampling head selection circuit, sample circuit and tap tracking circuit;
Said rising edge extracts circuit, is used for after receiving synchronised clock and frame synchronizing signal, and with the synchronised clock work clock, behind the rising edge of frame synchronizing signal, produce the pulse signal of a single clock cycle;
Said circulating sampling counter is a work clock with the synchronised clock, is used for realizing at least one sampling head according to said pulse signal;
Said sampling head is selected circuit; Be used for selecting the most stable sampling head of frame synchronizing signal sampling at said sampling head; Wherein, Said choosing method to the most stable sampling head of frame synchronizing signal sampling is: calculate the difference of the sampling head of realizing in the sampling head realized in first frame period and each frame period afterwards, if this difference in the predetermined threshold value scope, is then chosen the sampling head realized in said first frame period for to the most stable sampling head of frame synchronizing signal sampling;
Said sample circuit is used for according to the most stable said sampling head frame synchronizing signal being sampled;
Said tap tracking circuit is used for the selected the most stable sampling head of frame synchronizing signal sampling is followed the tracks of.
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| CN200810067475A CN101594189B (en) | 2008-05-27 | 2008-05-27 | Transmission method and receiving device of frame synchronizing signal |
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| CN200810067475A CN101594189B (en) | 2008-05-27 | 2008-05-27 | Transmission method and receiving device of frame synchronizing signal |
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| CN101594189B true CN101594189B (en) | 2012-09-05 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8743912B2 (en) * | 2009-12-18 | 2014-06-03 | Nec Corporation | Transmission system, transmitting device, receiving device, transmission method, and computer program |
| CN103096457B (en) * | 2013-01-18 | 2016-06-29 | 苏州智铸通信科技有限公司 | TDD base station synchronization method based on external reference clock and sub-frame sync signal |
| CN106998584B (en) * | 2016-01-25 | 2020-05-26 | 大唐移动通信设备有限公司 | Signal transmission method and device, and base station |
| CN109633228B (en) * | 2018-12-28 | 2021-06-15 | 深圳市鼎阳科技股份有限公司 | Sampling method and device in oscilloscope and oscilloscope |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6345057B1 (en) * | 1997-05-22 | 2002-02-05 | D.S.P.C. Technologies Ltd. | Bi-directional channel analysis |
| CN1538699A (en) * | 2003-04-17 | 2004-10-20 | ������������ʽ���� | Frame synchronization |
| CN101032139A (en) * | 2004-01-28 | 2007-09-05 | 高通股份有限公司 | Frame synchronization and initial symbol timing acquisition system and method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6345057B1 (en) * | 1997-05-22 | 2002-02-05 | D.S.P.C. Technologies Ltd. | Bi-directional channel analysis |
| CN1538699A (en) * | 2003-04-17 | 2004-10-20 | ������������ʽ���� | Frame synchronization |
| CN101032139A (en) * | 2004-01-28 | 2007-09-05 | 高通股份有限公司 | Frame synchronization and initial symbol timing acquisition system and method |
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