CN101645436A - 具有电磁干扰防护体的半导体封装件及其形成方法 - Google Patents
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Abstract
一种具有电磁干扰防护体的半导体封装件及其形成方法。在一实施例中,半导体封装件包括一基板单元、一半导体组件、一封装体及一电磁干扰防护体。基板单元包含有一接地组件,其邻近基板单元的一周边设置且至少部份地延伸于基板单元的一上表面与一下表面之间。半导体组件邻近基板单元的上表面设置。封装体邻近基板单元的上表面设置并覆盖半导体组件。电磁干扰防护体邻近封装体的外表面设置。封装体的一周边侧向地凹陷,以使接地组件的连接面暴露出来并电性连接于电磁干扰防护体。其中,接地组件提供一电性路径以将电磁干扰防护体上的电磁放射放电至接地端。
Description
技术领域
本发明是有关于一种半导体封装件及其形成方法,且特别是有关于一种具有电磁干扰防护体(electromagnetic interference shielding)的半导体封装件及其形成方法。
背景技术
受到提升工艺速度及尺寸缩小化的需求,半导体组件变得甚复杂。当工艺速度的提升及小尺寸的效益明显增加时,半导体组件的特性也出现问题。特别是指,较高的工作时脉(clock speed)在信号电平(signal level)之间导致更频繁的转态(transition),因而导致在高频下或短波下的较高强度的电磁放射(electromagneticemission)。电磁放射可以从半导体组件及邻近的半导体组件开始辐射。假如邻近的半导体组件的电磁放射的强度较高,此电磁放射负面地影响半导体组件的运作,请参考与电磁干扰(electromagnetic interference,EMI)有关的资料。若整个电子系统内具有高密度分布的半导体组件,则半导体组件之间的电磁干扰更显严重。
一种降低EMI的方法是,将一组半导体封装件内的半导体组件屏蔽(shield)起来。特别一提的是,由电子传导壳体或盖体与半导体封装件以外部接地的方式来完成屏蔽。当来自于半导体封装件内部的电磁放射作用在壳体的内表面时,至少部份的电磁放射的可被电性短路(short),以降低电磁放射的程度,避免电磁放射通过壳体而负面地影响邻近的半导体组件的运作。相似地,当来自于邻近的半导体组件的电磁放射作用在壳体的外表面时,一可降低半导体封装件内半导体组件的电磁干扰的电性短路发生。
然而,可降低EMI的电性传导壳体带来许多缺点。特别是在已知技术中,壳体通过黏贴(adhesive)与半导体封装件的外部连接。不幸地,由于黏贴方式易受温度、湿度及其它环境条件影响,使壳体容易剥离。此外,当连接壳体至半导体封装件时,壳体的大小与外型及半导体封装件的大小与外型只有在较精准的公差级数下才能匹配。因此壳体与半导体封装件的加工尺寸、外型及组合精度使得制造成本及工时增加。且,因为加工尺寸及外型的关系,不同的半导体封装件的尺寸及外型,可能需要不同的壳体。如此,为了容纳不同的半导体封装件,更增加了制造成本及工时。
为了改善已知问题,有必要提升半导体封装件及相关方法的发展。
发明内容
根据本发明的一方面,提出一种具有电磁放射防护体的半导体封装件。在一实施例中,半导体封装件包括一基板单元、一半导体组件、一封装体及一电磁干扰防护体。基板单元包括一上表面、一下表面及一接地组件。接地组件邻近基板单元的一周边(periphery)设置,且至少部份地延伸于基板单元的上表面与下表面之间。接地组件具有一连接面(connection surface),其邻近于基板单元的上表面设置。半导体组件邻近基板单元的上表面设置并电性连接基板单元。封装体邻近基板单元的上表面设置并覆盖半导体组件,封装体的一周边相对基板单元的周边侧向地凹陷,以使接地组件的连接面暴露出来,以作为电性连接之用,封装体并具有数个外表面。电磁干扰防护体邻近封装体的外表面设置并电性连接接地组件的连接面。其中,接地组件提供一电性路径(electrical pathway)以将电磁干扰防护体上的电磁放射(electromagnetic emission)放电至接地端。
在另一实施例中,半导体封装件包括一基板单元、一半导体组件、一封装体及一电磁干扰防护体。基板单元具有相对应的一第一表面及一第二表面且包括一接地组件。接地组件至少部份地延伸于基板单元的第一表面与第二表面之间,接地组件对应至一接地孔的一余留部份并具有一邻近于基板单元的第一表面的一周边部份(peripheral portion)设置的连接面。半导体组件邻近基板单元的第一表面设置并电性连接基板单元。封装体邻近基板单元的第一表面设置并覆盖半导体组件。封装体的一周边相对基板单元的一周边侧向地凹陷,以使接地组件的连接面从邻近于基板单元的第一表面的周边部份暴露出来,以作为电性连接之用,封装体并具有数个外表面。电磁干扰防护体邻近封装体的外表面设置并电性连接接地组件的连接面。
本发明的另一方面关于一具有电磁干扰防护体的半导体封装件的形成方法。在一实施例中,一方法包括以下步骤。提供一基板,基板具有一上表面、一下表面及数个接地孔,接地孔至少部份地延伸于上表面与下表面之间;电性连接一半导体组件至基板的上表面;设置一封装材料至基板的上表面,以形成一封装结构(moldedstructure),封装结构覆盖接地孔及半导体组件;形成一第一组切割槽(cutting slit),第一组切割槽通过封装结构,以使(a)封装结构被切割成一包含有半导体组件的封装体,封装体包括数个侧面,该些侧面定义出封装体的一周边,以及(b)部份的该些接地孔越过封装体的周边设置并具有数个连接面;形成一电磁干扰涂布体,电磁干扰涂布体覆盖封装体及连接面;形成一第二组切割槽,第二组切割槽通过电磁干扰涂布体及基板,以使(a)电磁干扰涂布体被切割成一邻近封装体及该些连接面设置的电磁干扰防护体、(b)基板被切割成一包含一上表面的基板单元,半导体组件邻近基板单元的上表面设置以及(c)该些连接面邻近基板单元的该表面的一周边部位设置。
为让本发明的上述内容能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下:
附图说明
图1绘示半导体封装件100的立体图。
图2绘示图1中半导体封装件沿着方向A-A的剖视图。
图3绘示图1及图2中半导体封装件的部份放大示意图。
图4绘示依照本发明另一实施例的半导体封装件的示意图。
图5绘示图4中部份的半导体封装件的示意图。
图6A至6H绘示依照本发明的一实施例的半导体封装件的形成方法。
图7A至7D绘示依照本发明的一实施例中邻近基板单元的接地组件之间的多种预设距离的实施态样示意图。
主要组件符号说明:
100、400:半导体封装件
102、102′、402:基板单元
104、404、604、610:上表面
106、406、614:下表面
108a、108b、108c、430:半导体组件
110a、110b、110c:电性连接部
112:焊线
114、114′、414、704、704′:封装体
118a、118b、408a、408b、602c、602d、602e、602f、700、700′:接地组件
120、122、142、144、420、422、442、444:侧面
124、424:电磁干扰防护体
126、426:上方部
128、428:侧向部
140:架体
146a、146b:孔接垫
148a、148b:镀层信道
150:电性连接机制
300:内层结构
302:外层结构
410a、410b:孔接垫余留部
412a、412b:镀层信道余留部
500、502:表面
600:基板
608:封装材料
612a、612b、612c、620a、620b、620c:切割槽
616:电磁干扰涂布体
618、630:切割锯
640:封装结构
C1、C2:宽度
D:侧向尺寸
H、H1、H2:高度
L1、L2、L3:距离
S1、S2、S1′、S2′、S3、S3′、S4、S4′:连接面
W1、W2:侧面尺寸
具体实施方式
以下的阐述是应用至依照本发明的一些实施例。以下详细说明该些阐述。
此处所用的单数型态”一”及”该”也意图包括数个型态,除非文中清楚指明不是。例如,若提及一接地组件,表示也包含数个接地组件,除非文中清楚指明不是。
此处所用的”组”表示一或多个组件的集合。例如,一组层结构可包含单层结构或多层结构。一组中的组件可以是指该组的成员。一组中的组件可以相同或不同的。在一些例子中,一组中的组件可具有一或多个共同特征。
此处所用的”邻近”表示接近或连接在一起。相邻的组件可以互相分开或直接互相连接。在一些例子中,相邻的组件可以指互相连接或彼此间一体成型的组件。
此处所用的”内部”、”外部”、”在...上”、”往上地”、”在...之下”、”往下地”、”垂直”、”侧面”、”侧面地”表示数个组件之间的相关位置。例如,该些相关位置依据图标而定而非指制造或使用时,此些组件的特定方位。
此处所用的”连接”表示一操作上的耦接(coupling)或连结(linking)。连接的组件可指为直接互相连接或间接连接,间接连接例如通过另一组件作间接连接。
此处所用的”实质上”表示一相当重要的程度或范围。当”实质上”发生一事件或状况时,指该事件或该状况精确地发生或以甚接近的程度发生。例如,此处所提及的制造过程中的典型公差等级。
此处所用的”电性传导(electrical conductive)”及”导电性(electricalconductivity)”表示传输电流的能力。电性传导材料传统上指些微或甚至不会阻碍电流流动的材料。电导率(conductivity)的量测以西门子/公尺(S·m-1)为单位。一般而言,一电性传导材料指具有大于104S·m-1的电导率的材料,例如的其电导率至少约105S·m-1或至少约106S·m-1。材料的电导率可随温度改变,除非有特别指明,不然材料的电导率指室温下的电导率。
请参照图1及图2,其绘示依照本发明一实施例的半导体封装件示意图。图1绘示半导体封装件100的立体图,图2绘示图1中半导体封装件沿着方向A-A的剖视图。
在本实施例中,半导体封装件100包括一架体(ledge)140,其邻近半导体封装件100的一周边(periphery)设置,且从半导体封装件100的侧面往外延伸。特别一提,架体140实质上环绕着半导体封装件100的整个周边延伸。在其它实施态样中,架体140环绕半导体封装件100的范围也可以是其它形式。如图1及图2所示,架体140邻近半导体封装件100的一底部设置并与半导体封装件100的侧面连接,以定义出一实质上可环绕着半导体封装件100的整个周边延伸的L字型。通过改变架体140的外形及半导体封装件100的侧面,或改变架体140相对半导体封装件100的侧面的位置,半导体封装件100的侧面轮廓可以成为多种外形中的任何一种。半导体封装件100的侧面轮廓可以是曲面、倾斜面或粗糙结构(roughlytextured)。在其它实施态样中,架体140的一侧向尺寸(lateral extent)D可介于约50微米(μm)与约500μm之间,例如是从约50μm至约400μm,或从约100μm至约300μm。
请参照图1及图2,半导体封装件100包括一基板单元102,基板单元102具有一上表面104、一下表面106及沿着基板单元102的侧向设置的侧面142及144。在本实施例中,侧面142及144实质上为平面且具有一实质上与上表面104或下表面106呈直角的方位。在其它实施态样中,侧面142及144的外形及方位可以有不同的变化。基板单元102可通过多种方法完成并具有电性连接机制150,其于上表面104与下表面106之间提供电性路径(electrical pathway)。电性连接机制150例如是一组电性传导层,其被包含在一组介电层(dielectric layer)内。电性传导层可通过内部贯孔互相连接,且其内可插入一由适当的树脂所制成的基板中间层(core)。该适当的树脂例如是由双马来亚醯胺(bismaleimide)及三氮杂苯(triazine)所组成的树脂或由环氧树脂(epoxy)及聚氧化丙烯(polyphenylene oxide)所组成的树脂。举例来说,基板单元102可包含一实质上板状中间层(slab-shaped core),其被设置于一组邻近中间层(core)的上表面的电性传导层与另一组邻近中间层(core)的下表面的电性传导层之间。对于某些实施态样,大部份或所有的电性传导层可设置于基板单元102的内部,以降低邻近侧面142及144的电性传导层的暴露程度。举例来说,电性传导层中至多一者,例如是最底层的电性传导层可从侧面142及144暴露出来。如此,即使是为了保护电性传导层免受氧化、湿气及其它环境侵害,而将电性传导层设于基板单元102内,然,电性传导层仍可于上表面104与下表面106之间提供出电性路径。
在某些实施例中,基板单元102的厚度,即基板单元102的上表面104与下表面106间的距离可介于约0.1毫米(mm)至约2mm之间。例如,从约0.2mm至约1.5mm或从约0.3mm至约1mm。虽然未绘示于图2,一绿漆(solder mask)层可邻近于基板单元102的上表面104与下表面106的一者或二者设置。此外,一保护层(protective layer)邻近基板单元102的侧面142及144设置,以保护任何暴露出的电性传导层。
如图2所示,基板单元102包括接地组件118a及118b,接地组件118a及118b邻近基板单元102的一周边(periphery)设置。接地组件118a及118b为细长结构,其至少部份地延伸于上表面104与下表面106之间。更进一步地说,接地组件118a及118b提供如下述的电性路径,以降低EMI。在本实施例中,接地组件118a及118b由接地孔(grounding via)形成。每个接地孔包括一孔接垫(via pad)146a或146b,以及镀层信道(plated channel)148a或148b。孔接垫146a、146b邻近基板单元102的上表面104设置,镀层信道148a、148b延伸于孔接垫146a或146b之间。基板单元102包含电性连接机制150。在某些实施例中,接地组件118a及118b的一高度H,即接地组件118a及118b的垂直延伸部份略小于基板单元102的厚度,且可介于约0.1mm与1.5mm之间,例如,从约0.1mm至约1mm,或者,从约0.2mm至约0.5mm。然而,在其它实施态样中,接地组件118a及118b也可以有不同的变化。请继续参照图2,接地组件118a及118b分别包含连接面(connection surface)S1及S2,其暴露于基板单元102的上表面104,以作为电性连接之用。在本实施例中,连接面S1及S2分别对应于孔接垫146a及146b的电性暴露面(electrically exposed surface),以作为电性连接之用。较大的连接面S1及S2的面积有助于提升电性连接的可靠度及效率,以降低EMI。
如图2所示,半导体封装件100更包括半导体组件108a、108b及108c,其邻近基板单元102的上表面104设置,以及电性连接部110a、110b及110c,其邻近基板单元102的下表面106设置。半导体组件108a通过一组焊线(wire)112打线连接(wore-bonded)至基板单元102,该组焊线由金(gold)或另一适当的电性传导材料所制成。并且,半导体组件108b及108c以表面接触的方式固接至基板单元102。在本实施例中,半导体组件108a及108c可以是被动组件,例如是电阻、电容或电感时,而半导体组件108b可以是一半导体芯片。电性连接部110a、110b及110c提供半导体封装件100的输出及输入的电性连接。并且,电性连接部110a、110b及110c中至少一部份通过基板单元102内的电性连接机制150,电性连接至半导体组件108a、108b及108c。在本实施例中,电性连接部110a、110b及110c中至少一者为接地电性连接部,且通过基板单元102内的电性连接机制150,电性连接至接地组件118a及118b。虽然图2绘示三个半导体组件,在其它实施态样中,半导体组件的数量也可以是更多或更少。并且,半导体组件可以是主动组件、任何被动组件,或主动组件及被动组件的组合。在其它实施态样中,电性连接部的数量也可以与图2不同。
请继续参照图2,半导体封装件100更包括封装体114,其邻近基板单元102的上表面104设置并与基板单元102连接。封装体114实质上覆盖或密封半导体组件108a、108b、108c及焊线112,以提供机械稳定性(mechanical stability)及抗氧化、抗湿气及对抗其它环境侵害的作用。封装体114由封装材料所制成且具有数个外表面,例如是侧面120及122,其邻近于封装体114的侧面。在本实施例中,侧面120及122实质上为平面并具有一实质上与上表面104或下表面106呈直角的方位。侧面120及122亦可为曲面、倾斜面、阶梯面或粗糙结构(rough1y textured)。如图2所示,此外,侧面120及122实质上分别与侧面142及144平行。此外,封装体114中由侧面120及122所定义出的一周边,其相对于基板单元102中由侧面142及144所定义出的周边侧向地凹陷进去。特别一提的是,侧向凹陷的封装体114可降低基板单元102的上表面104的一周边部位与封装体114的覆盖范围,藉以露出部份的孔接垫146a及146b,使连接面S1及S2暴露出来,以作为电性连接之用。在其它实施态样中,只要连接面S1及S2至少部份地暴露出来,侧面120、122及其凹陷部位相对于侧面142及144的外形也可以不同于图2。
如图1及图2所示,半导体封装件100更包括一电磁干扰防护体124,其邻近封装体114的外表面及基板单元102的上表面104的周边部位设置。电磁干扰防护体124由电性传导材料所制成且实质上环绕半导体封装件100内的半导体组件108a、108b及108c,以提供对EMI的防护作用。在本实施例中,电磁干扰防护体124包含一上方部(upper portion)126及一侧向部(lateral portion)128,其环绕着封装体114的整个外缘延伸并定义出半导体封装件100中呈L字型的侧面。如图2所示,侧向部128从上方部126往下地延伸并侧向地往基板单元102的周边部位延伸,且实质上终止于基板单元102的周边。然而,在侧向部128的延伸范围也可以是其它态样。
如图2所示,电磁干扰防护体124电性连接至接地组件118a及118b的连接面S1及S2。当电磁放射从半导体封装件100的内部冲击电磁干扰防护体124时,至少部份的电磁放射可通过接地组件118a及118b有效地放电至接地端,以降低通过电磁干扰防护体124的电磁放射强度及降低对邻近的半导体组件的影响程度。相似地,当来自于邻近的半导体组件的电磁放射冲击到电磁干扰防护体124时,一相似的接地放电效果发生,以降低对半导体组件108a、108b及108c产生的电磁干扰。在操作的过程中,半导体封装件100可设置于一电路板(Printed circuit board,PCB)且通过电性连接部110a、110b及110c与PCB电性连接。如前述,电性连接部110a、110b及110c中至少一者为接地电性连接部,该接地电性连接部电性连接于电路板的接地电压,使电磁放射可通过电磁干扰防护体124放电至接地端。该电磁放射经过一包括接地组件118a、接地组件118b及基板单元102的电性连接机制150及接地电性连接部的电性路径。
在本实施例中,电磁干扰防护体124为一全覆盖(conformal)防护体且为一组涂布体、层结构或薄膜的形式,此有助于电磁干扰防护体124在不需要使用黏结方式的情况下,邻近或直接形成于半导体封装件100的外部,以增进可靠度及抗氧化、抗湿气及对抗其它环境侵害的作用。此外,由于电磁干扰防护体124的全覆盖(conformal)特性,使相似的电磁干扰防护体及相似的制造过程可轻易地应用至不同尺寸及外型的半导体封装件,以使在容纳不同的半导体封装件时可降低制造成本及时间。在其它实施例中,电磁干扰防护体124的厚度可介于约1微米(μm)至约500μm之间,例如是从约1μm至约200μm、从约1μm至约100μm、从约10μm至约100μm、从约1μm至约50μm或从约1μm至约10μm。相较于已知的例子,厚度如此薄的电磁干扰防护体124使半导体封装件整体尺寸缩小,此为本实施例的优点之一。
如图3所示,其绘示图1及图2中半导体封装件的部份放大示意图。特别一提的是,图3绘示邻近封装体114设置的电磁干扰防护体124的一实施态样。
如图3所示,电磁干扰防护体124为多层结构且包含一内层结构300及一外层结构302。内层结构300邻近封装体114设置,而外层结构302邻近内层结构300设置且暴露于半导体封装件100的外部。一般而言,内层结构300与外层结构302中的每一者可由金属、金属合金、具有金属的金相或一散布有金属合金的结构或其它适当的电性传导材料所制成。举例来说,内层结构300与外层结构302中的每一者可由铝、铜、铬、锡、金、银、镍、不锈钢或上述材料的组合所制成。内层结构300与外层结构302可由相同的电性传导材料或相异的电性传导材料所制成。举例来说,内层结构300与外层结构302可皆由金属,例如是镍所制成。在其它实施例中,内层结构300与外层结构302可各别由相异的电性传导材料所制成,以提供互补的功能。举例来说,内层结构300可由一具有高电性传导率的金属,例如是铝、铜、金或银所制成,以提供电磁放射防护功能,在此情况下,外层结构302可由一低电性传导率的金属,例如是镍所制成,以保护内层结构300免于受到氧化、湿气及其它环境因子的侵害。此外,外层结构302也可同时提供保护功能及电磁放射防护的功能。虽然图2绘示双层结构,然于其它实施态样中亦可为多于或少于双层的结构。
图4绘示依照本发明另一实施例的半导体封装件的示意图。半导体封装件400采用相似于前述的图1至3的半导体封装件100的技术手段,在此便不再赘述。
如图4所示,半导体封装件400包含一基板单元402。基板单元402包括一上表面404、一下表面406及沿着基板单元402的侧向设置的侧面442及444。在本实施例中,上表面404的一周边部位往下弯曲,以定义出一切除部(cut-out portion),切除部实质上沿着基板单元402的整个周边延伸。在其它实施例中,环绕基板单元402的整个周边延伸的切除部也可以是其它的变化。
切除部的一实施态样如图5所示,其绘示图4中部份的半导体封装件的示意图。特别一提的是,图5绘示基板单元402中邻近侧面444的轮廓。为了不使图标过于复杂,图5省略半导体封装件400的细部结构。在本实施例中,上表面404的周边部位包含一组表面,即表面500及表面502,其定义出基板单元402的切除部。表面500实质上为平面并具有一实质上与上表面404或下表面406呈垂直的方位,而表面502实质上为一曲面。如下所述,基板单元402的切除部的形成可由一组切割工艺完成。在某些实施例中,切除部的整个垂直高度H1可介于约1μm至约100μm间。例如,从约1μm至约80μm,或者,从约1μm至约40μm。表面500的整个垂直高度H2可介于垂直高度H1的约1%至约95%间。例如,从约20%至约80%,或约40%至约60%。在其它实施例中,表面500及502的尺寸及范围也可以是其它变化。
回到图4,半导体封装件400更包括接地组件408a及408b,其至少部份地延伸于基板单元402的上表面404与下表面406之间且邻近基板单元402的周边设置。值得一提的是,接地组件408a及408b实质上设置于基板单元402的周边并分别邻近于侧面442及444设置。在本实施例中,接地组件408a及408b由接地孔,且特别是接地孔于一组切割工艺之后的余留部份(remnant)所形成,该组切割工艺将叙述于后。如图4所示,接地组件408a及408b中每一者包含一孔接垫余留部(viapad remnant)410a或410b及一镀层信道余留部(plated channel remnant)412a或412b。孔接垫余留部410a或410b邻近基板单元402的上表面404设置,而镀层信道余留部412a或412b沿着孔接垫余留部410a或410b与基板单元402内的电性连接机制之间延伸。接地组件408a及408b分别包含连接面S1’及S2’,其暴露于上表面404中弯曲的周边部位,以作为电性连接之用。如图4所示,连接面S1’及S2’对应于孔接垫余留部410a、410b及镀层信道余留部412a、412b中具有电性连接用途的电性暴露面。较大的连接面S1’及S2’的面积有助于提升电性连接的可靠度及效率,以降低EMI。
如图4所示,半导体封装件400更包括一半导体组件430,其一邻近于基板单元402的上表面404设置的半导体芯片。在本实施例中,半导体组件430为结合于基板单元402的上表面404的覆晶式芯片(flip chip)。例如,半导体组件430可通过一组锡铅凸块(solder bump)结合至基板单元402。或者,半导体组件430也可通过另一技术手段,例如是通过打线结合(wire-bonding)技术与基板单元402结合。
请继续参照图4,半导体封装件400更包括封装体414,其邻近基板单元402的上表面404设置。封装体414具有数个外表面,例如是侧面420及422,侧面420及422沿着封装体414的侧面设置。在本实施例中,侧面420及422实质上为平面并具有一实质上呈垂直的方位,并实质上平行于基板单元402的侧面442及444。此外,封装体414中由侧面420及422所定义出的周边,其相对于基板单元402中由侧面442及444所定义出的周边侧向地凹陷进去,如此可降低基板单元402的上表面404的一周边部位与封装体414的相覆盖的范围,使连接面S1’及S2’暴露出来,以作为电性连接之用。在其它实施态样中,只要连接面S1’及S2’至少部份地暴露出来,侧面420、422及凹陷部位的外形也可以不同于图4。
半导体封装件400更包括一电磁干扰防护体424,其电性连接接地组件408a及408b的连接面S1’及S2’。如图4所示,电磁干扰防护体424邻近封装体414的外表面及基板单元402的上表面404中弯曲的周边部位设置。电磁干扰防护体424包含一上方部(upper portion)426及一侧向部(lateral portion)428,其实质上环绕着封装体414的整个外缘延伸并定义出半导体封装件400的J字型轮廓。在本实施例中,侧向部428从上方部426往下地延伸且更侧向地沿着上表面404的弯曲的周边部位延伸,且实质上终止于基板单元402的周边。然而,在其它实施态样中,侧向部428的延伸范围也可以是其它变化。
请参照图6A至6H,其绘示依照本发明的一实施例的半导体封装件的形成方法。为了不使图标过于复杂,以下的形成方法以图1至3的半导体封装件100为例作说明。然而,形成方法亦可应用于其它半导体封装件,例如是体4至5的半导体封装件400。
如图6A至6B所示,提供一基板600。为了增进制造生产量,基板600包括数个基板单元。该些基板单元包含基板单元102及一相邻的基板单元102’。在一适当的工艺方法中,包含多个基板单元的基板600仍可快速地被制造。基板600可呈带形(strip),多个基板单元连续地呈直线排列。或者,多个基板单元沿着二维方向排列成数组形(array)。为了不使图标过于复杂,以下的形成方法以基板单元102及其相关组件为例作说明。然而,形成方法亦可应用于其它基板单元及其相关组件。
如图6A至6B所示,数个接地组件邻近基板单元的一周边设置。特别一提的是,接地组件118a、接地组件118b、接地组件602c、602d及602e邻近基板单元102的侧面设置。在本实施例中,接地组件可由接地孔形成。每个接地孔包含一孔接垫及一镀层信道(plated channel)。孔接垫例如是孔接垫146a或146b,而镀层信道例如是148a或148b。接地组件可由多种方法中任一种形成。例如,应用光蚀刻法(photolithography)、化学蚀刻、激光钻孔或机械加工来形成开孔,且开孔的镀层采用金属、金属合金、具有金属的金相或一散布有金属合金的结构或其它适当的电性传导材料所制成。在一些实施例中,电性传导材料于被涂布后流进开孔,并以实质上填满电性传导材料的开孔。举例来说,电性传导材料可包含一金属或电性传导黏结剂(electrically conductive adhesive)。该金属例如是铜、锡球(solder)。锡球例如是由多种易熔金属合金中任一种所制成,该多种易熔金属合金的熔点介于约90℃至约450℃之间。
在本实施例中,孔接垫,例如是孔接垫146a或146b具有一环状(annular)外形,而镀层信道,例如是镀层信道148a或148b为一具有实质上呈圆形剖面的圆柱形(circular cylinder)。孔接垫及镀层信道也可以是多种形状种类中的任何一种。例如,镀层信道可以是其它种类的圆柱形(cylindrical shape)以及非圆柱型(non-cylindrical shape)。该其它种类的圆柱形例如是椭圆柱形(elliptic cylindricalshape)、正方柱形(square cylindrical shape)及矩形柱形(rectangular cylindricalshape)。该非圆柱型例如是锥形(cone)、漏斗形(funnel)及其它渐缩外形(taperedshape)。镀层信道的侧面轮廓可以是曲面或粗糙结构。在其它实施态样中,每个镀层信道的侧面尺寸W1(亦可称为孔尺寸)可介于约50μm至约300μm之间,例如从约100μm至约200μm,或从约120μm至约180μm。在此情况下,每个孔接垫的侧面尺寸W2(亦可称为孔接垫尺寸)可介于约100μm至约600μm之间,例如从约200μm至约400μm,或从约240μm至约360μm。在其它实施例中,侧面尺寸W1或W2也可与沿着直角方向上的侧面长度的平均值相对应。
为了提升可靠度及电性连接效率以降低EMI。接地组件邻近每个基板单元中全部的四个侧面或部份的四个侧面设置。或者,接地组件也可以邻近每个基板单元中全部的四个角落或部份的四个角落设置。在其它实施态样中,基板单元中最接近的接地组件之间的距离L1(亦可称为孔节距)可介于约0.1mm与约3mm之间,例如从约0.5mm至约2mm,或从约0.7mm至约1.3mm。如图6B所示,基板单元内的虚线边界定义出一主动区域,半导体组件设于主动区域内。在半导体组件的制造过程中,为了降低或减少反冲击,基板单元的接地组件可与主动区域隔开一距离L2(亦可称为缓冲距离)。在其它实施例,距离L2可介于约50μm至约300μm,例如从约50μm至约200μm,或约100μm至约150μm。继续参照图6B,相邻的基板单元中最接近的接地组件之间相隔一距离L3。例如,基板单元102的接地组件118b与相邻的基板单元102’的接地组件602f相隔一距离L3。接地组件的数目及其位于基板600的位置也可以与图6A及图6B不同。数排接地组件也可邻近基板单元的周边设置。
在提供基板600后,半导体组件108a、108b及108c邻近基板600的上表面604设置且电性连接基板单元102。特别一提的是,半导体组件108b经由焊线112并应用打线连接技术(wire-bonded)连接至基板单元102。并且,半导体组件108b及108c以表面接触的方式固接至基板单元102。
接着,如图6C所示,涂布(apply)一封装材料608至基板600的上表面604,以实质上覆盖或密封接地组件118a及118b、半导体组件108a、108b及108c以及焊线112。封装材料608可包括例如一酚醛清漆树脂(Novolac Resin)、一环氧树脂(epoxy-based resin)、一硅氧树脂(silicone-based resin)或其它适当的封装材料。该其它适当的填充剂可包含例如是粉状二氧化硅(SiO2)。封装材料608可应用于多种封装技术,例如压缩成形(compression molding)、射出成形(injectionmolding)及转移成形(transfer molding)中的任一种。一旦封装材料608设置于基板600后,可将温度降低至低于封装材料608的熔点,以使封装材料608硬化或固化而形成一封装结构640。为了利于基板600于切割工艺(singulation)中的定位,基准标记(fiducial mark)可形成于封装结构640,基准标记的形成方式例如是应用激光方式制作。此外,基准标记也可邻近基板600的一周边。
接下来,从封装结构640的上表面610切割封装结构640(呈直立方位(uprightorientation)的姿态)。如此的切割方式称为”正面(front-side)”切割。如图6D至6E所示,正面切割由一切割锯(saw)630执行,以形成切割槽612a、612b及612c。特别一提的是,切割槽612a、612b及612c往下地延伸并完全贯穿封装结构640,以将封装结构640切割成数个包含及封装体114及相邻的封装体114’的分离单元。在本实施例中,切割槽612a、612b及612c往下地延伸并实质上终止基板600的上表面604。在此情况下,接地组件118a及118b的连接面S1及S2从基板单元102的周边的环绕部份暴露出来。在一些实施例中,每个切割槽612a、612b及612c的宽度C1(亦可称为半穿切宽度(half-cut width))可介于约100μm与约2000μm之间,例如从约300μm至约1200μm,或从约500μm至约900μm。
在其它实施例中,切割槽612a、612b及612c可延伸至基板600的上表面604之下。此外,通过调整切割锯630的外型,可切割出导圆角的外型,使切割槽612a、612b及612c产生如图4至5所示的切除部的曲面。虽然图6D至6E未绘示,在正面切割的过程中,一黏胶膜(tape)可被用来固接基板600的下表面614。该黏胶膜可以是一单侧或双侧具有黏性的黏胶膜。
接着,如图6F所示,一电磁干扰涂布体616邻近封装体114及114’的外表面形成且暴露出基板600的上表面604的一部份。电磁干扰涂布体616的制成可采用多种涂布技术中任一种完成。例如,通过化学蒸镀(Chemical Vapor Deposition,CVD)、无电镀(electroless plating)、电镀、印刷(printing)、喷布(spraying)、溅镀或真空沉积(vacuum deposition)。举例来说,电磁干扰涂布体616可包含一通过无电镀法制成的镍金属单层结构,其厚度至少约5μm,例如从约5μm至约50μm或从约5μm至约10μm。若电磁干扰涂布体616为多层结构,不同层结构的形成可采用相同的技术或相异技术完成。举例来说,可通过无电镀技术形成一材质为铜的内层结构,及可通过无电镀技术或电镀技术形成一材质为镍的外层结构。在另一实施例中,通过溅镀或无电镀技术形成一材质为铜的内层结构(作为基底用途)及通过溅镀技术形成一材质为不锈钢、镍或铜的外层结构(作为抗氧化用途)。该内层结构的厚度至少约1μm,例如从约1μm至约50μm或从约1μm至约10μm。该外层结构的厚度不大于约1μm,例如从约0.01μm至约1μm或从约0.01μm至约0.1μm。在这些实施例中,被电磁干扰涂布体616涂布的表面可先进行预处理,以增进外层结构及内层结构的成形性。该预处理包含表面粗糙化(surface roughening)及形成种子层(seed layer)。该表面粗糙化可采用如化学蚀刻(chemical etching)或机械磨损(mechanical abrasion)的技术形成,而该种子层可采用例如是无电镀技术形成。
在电磁干扰涂布体616形成后,形成有电磁干扰涂布体616的基板600被倒置(invert)且从基板600(呈倒置方位(inverted orientation)的姿态)的下表面614切割基板600。如此的切割方式称为”背面(back-side)”切割。如图6G及图6H所示,背面切割由一切割锯(saw)618执行,以形成切割槽620a及620b及620c。特别一提的是,切割槽620a及620b及620c往下地延伸并完全贯穿基板600及电磁干扰涂布体616(呈倒置方位的姿态),以将基板600及电磁干扰涂布体616切割成数个包含基板单元102及电磁放射防护体124的分离单元。如此,形成半导体封装件100。在一些实施态样中,切割槽620a、620b及620c(有时被称为一全穿切宽度(full-cut width)中每一者的宽度C2可介于约100μm至约600μm之间,例如是从约200μm至约400μm或从约240μm至约360μm。虽然图6G及6H未绘示,在背面切割的过程中,一黏胶膜可被用来固接半导体封装件100及相邻的半导体封装件。该黏胶膜可以是一单侧或双侧具有黏性的黏胶膜。
请参照图7A至7D,其绘示依照本发明的一实施例中最接近的接地组件700及700’间的一适当距离L3。为了不使图标过于复杂,假定于正面切割工艺中切出一宽度C1,且于背面切割工艺中切出一宽度C2。距离L3较佳地至少等于宽度C2且不大于宽度C1。在其它实施态样中,距离L3的关系可以表示成:C2≤L3≤C1。
如图7A所示,距离L3大于宽度C1,亦即,在正面切割工艺后,接地组件700与700’相距一大于宽度C1的距离。此外,在正面切割工艺后,接地组件700及700’实质上仍分别地被封装体704及704’覆盖。如图7B所示,距离L3约等于宽度C1,亦即,在正面切割工艺后,接地组件700与700’相距一约等于宽度C1的距离。此外,在正面切割工艺后,接地组件700及700’至少部份地暴露且提供电性路径以降低EMI。如图7B所示,接地组件700与700’分别包括连接面S3及S3’。
如图7C所示,距离L3约等于宽度C2,亦即,在背面切割工艺后,接地组件700与700’相距一约等于宽度C2的距离。此外,在背面切割工艺后,接地组件700及700’的余留部份至少部份地暴露出来,以提供电性路径,以降低EMI。如图7C所示,接地组件700及700’的余留部份分别包括连接面S4及S4’。如图7D所示,距离L3小于宽度C2,亦即,在背面切割工艺后,接地组件700与700’相距一小于宽度C2的距离。此外,在背面切割工艺后,接地组件700及700’实质上没有余留部份。
综上所述,虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视后附的权利要求书所界定者为准。
Claims (20)
1.一种半导体封装件,包括:
一基板单元,包括:
一上表面;
一下表面;及
一接地组件,邻近该基板单元的一周边(periphery)设置,且至少部份地延伸于该基板单元的该上表面与该下表面之间,该接地组件具有一连接面(connection surface),该连接面邻近于该基板单元的该上表面设置;
一半导体组件,邻近该基板单元的该上表面设置并电性连接该基板单元;
一封装体,邻近该基板单元的该上表面设置并覆盖该半导体组件,该封装体的一周边相对该基板组件的该周边侧向地凹陷,以使该接地组件的该连接面暴露出来,以作为电性连接之用,该封装体并具有数个外表面;以及
一电磁干扰防护体(electromagnetic interference shield)邻近该封装体的该些外表面设置并电性连接该接地组件的该连接面;
其中,该接地组件提供一电性路径(electrical pathway)以将该电磁干扰防护体上的电磁放射(electromagnetic emission)放电至接地端。
2.如权利要求1所述的半导体封装件,其中该接地组件对应于一接地孔(grounding via),该接地孔包括一孔接垫(via pad),该孔接垫邻近该基板单元的该上表面设置,且该接地组件的该连接面对应于该孔接垫的一电性暴露面(electrically exposed surface)。
3.如权利要求2所述的半导体封装件,其中该基板单元更包括一电性连接机制,其设置于该基板单元的该上表面与该下表面之间,且该接地孔延伸于该基板单元的该上表面与该电性连接机制之间。
4.如权利要求1所述的半导体封装件,其中该接地组件的一高度介于0.1毫米(mm)至1.5mm之间。
5.如权利要求1所述的半导体封装件,其中该电磁干扰防护体包括一侧向部(lateral portion),其沿着该基板单元的该上表面的一周边部份(peripheral portion)延伸。
6.如权利要求5所述的半导体封装件,其中该侧向部实质上终止于该基板单元的该周边。
7.一种半导体封装件,包括:
一基板单元,其具有相对应的一第一表面及一第二表面且包括:
一接地组件,至少部份地延伸于该基板单元的该第一表面与该第二表面之间,该接地组件对应至一接地孔的一余留部份(remnant)并具有一邻近于该基板单元的该第一表面的一周边部份设置的连接面;
一半导体组件,邻近该基板单元的该第一表面设置并电性连接于该基板单元;
一封装体,邻近该基板单元的该第一表面设置并覆盖该半导体组件,该封装体的一周边相对该基板单元的一周边侧向地凹陷,以使该接地组件的该连接面从邻近于该基板单元的该第一表面的该周边部份暴露出来,以作为电性连接之用,该封装体并具有数个外表面;以及
一电磁干扰防护体(electromagnetic interference shield)邻近该封装体的该些外表面设置并电性连接该接地组件的该连接面。
8.如权利要求7所述的半导体封装件,其中该接地组件包括一孔接垫余留部(via pad remnant)及一镀层信道余留部(plated channel remnant),该孔接垫余留部邻近该基板单元的该第一表面设置,而该镀层信道余留部至少部份地延伸于该基板单元的该第一表面与该第二表面之间。
9.如权利要求7所述的半导体封装件,其中该基板单元的该第一表面的该周边部份呈曲状(curved),以定义出该基板单元的一切除部(cut-out portion)。
10.如权利要求7所述的半导体封装件,其中该基板单元更包括一侧面,该侧面延伸于该基板单元的该第一表面与该第二表面之间,该封装体的该些外表面包括一侧面,该封装体的该侧面相对于该基板单元的该侧面侧向地凹陷。
11.如权利要求7所述的半导体封装件,其中该电磁干扰防护体为一全覆盖(conformal)防护体,其包含铝、铜、铬、锡、金、银、不锈钢及镍中的至少一者。
12.如权利要求7所述的半导体封装件,其中该电磁干扰防护体包括一第一层结构及一邻近于该第一层结构设置的第二层结构,该第一层结构及该第二层结构包含不同的电性传导材料。
13.一种半导体封装件的形成方法,包括:
提供一基板,该基板具有一上表面、一下表面及数个接地孔,该些接地孔至少部份地延伸于该基板的该上表面与该下表面之间;
电性连接一半导体组件与该基板的该上表面;
涂布(apply)一封装材料至该基板的该上表面,以形成一封装结构(moldedstructure),该封装结构覆盖该些接地孔及该半导体组件;
形成一第一组切割槽(cutting slit),该第一组切割槽通过该封装结构,以使(a)该封装结构被切割成一覆盖该半导体组件的封装体,该封装体包括数个侧面,该些侧面定义出该封装体的一周边,以及(b)部份的该些接地孔超出于该封装体的该周边设置并具有数个连接面;
形成一电磁干扰涂布体,该电磁干扰涂布体覆盖该封装体及该些连接面;以及
形成一第二组切割槽,该第二组切割槽通过该电磁干扰涂布体及该基板,以使(a)该电磁干扰涂布体被切割成一邻近该封装体及该些连接面设置的电磁干扰防护体、(b)该基板被切割成一包含一上表面的基板单元,该半导体组件邻近该基板单元的该上表面设置以及(c)该些连接面邻近该基板单元的该上表面的一周边部位设置。
14.如权利要求13所述的形成方法,其中该些接地孔中至少一者的一贯孔尺寸介于50微米(μm)与300膜μm之间,而该些接地孔中至少一者的一孔接垫尺寸介于100μm与600μm之间。
15.如权利要求13所述的形成方法,其中该些接地孔中最接近的接地孔间的间距介于0.1mm与3mm之间。
16.如权利要求13所述的形成方法,其中于形成该第一组切割槽的该步骤中包括:
从该封装结构的一上表面,进行一正面切割(front-side singulation)。
17.如权利要求13所述的形成方法,其中该第一组切割槽中至少一者的一宽度介于100μm与2000μm之间。
18.如权利要求13所述的形成方法,其中于形成该第二组切割槽的该步骤中包括:
从该基板的该下表面,进行一背面切割(back-side singulation)。
19.如权利要求13所述的形成方法,其中该第二组切割槽中至少一者的一宽度介于100μm与600μm之间。
20.如权利要求13所述的形成方法,其中该第二组切割槽对齐至该第一组切割槽,且该第二组切割槽中至少一者的一宽度小于该第一组切割槽中至少一者的一宽度。
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Also Published As
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CN101645436B (zh) | 2013-10-09 |
TWI378765B (en) | 2012-12-01 |
US8410584B2 (en) | 2013-04-02 |
US20100032815A1 (en) | 2010-02-11 |
TW201008478A (en) | 2010-02-16 |
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