CN101663747B - 超薄堆叠的芯片封装 - Google Patents

超薄堆叠的芯片封装 Download PDF

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CN101663747B
CN101663747B CN2008800129833A CN200880012983A CN101663747B CN 101663747 B CN101663747 B CN 101663747B CN 2008800129833 A CN2008800129833 A CN 2008800129833A CN 200880012983 A CN200880012983 A CN 200880012983A CN 101663747 B CN101663747 B CN 101663747B
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chip
packing
planarized dielectric
substrate
simplifying
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CN101663747A (zh
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约翰·特雷扎
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Cufer Asset Ltd LLC
Cubic Wafer Inc
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Cubic Wafer Inc
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Abstract

一种封装方法包含将第一芯片(1002)附接至稳定的基底(600)，在稳定的基底上的多个位置形成触点焊盘(902)，在稳定的基底上施加平坦化介质(1102)以便它使得第一芯片的侧面电绝缘，在介质上形成电通路(1302，1304)，将第二芯片(1402)附接至第一芯片以形成组件，以及将稳定的基底移除。一种封装具有至少两个彼此电连接的芯片，至少一个触点焊盘，从触点焊盘向芯片的至少一个上的触点延伸的导电通路，平坦化介质和平坦化介质上的涂层材料(1502)。

Description

超薄堆叠的芯片封装
技术领域
本发明涉及电子封装，更具体的是，涉及芯片封装。
背景技术
长久以来一直希望能够将多个芯片封装进尽可能小的空间内。近年来，这导致了各种集成技术的发展。
一种这样的集成方法，如图1所示，包括直接将一个管芯102附接在第二管芯104上。这允许上管芯102和下管芯104彼此直接通信。此外，使用经由走线迹线108连接到芯片的接合线106使两个芯片102、104被从外部连接。虽然该方法结果形成较小的封装，但同时导致以下问题，如果两个芯片具有相同的尺寸或接近相同的尺寸，在某些情形中，对于接合线110来说可能没有足够的地方以存在于其中一个管芯上。另外，如果必须使用结合线106，则对于多个芯片使用该方法(例如，在多芯片上的多芯片配置中通过将这两个芯片单元中的一些堆叠在另一些的上部)既困难成本又高。
如图2所示，另一种集成选择是使用焊球202、倒装芯片附接方法以允许两个管芯堆叠被从外部连接。该方法比接合线方法更廉价，因此能够允许多芯片上的多芯片配置(图3)中的一些芯片被更加容易地或廉价地实现。然而，如果两个芯片的尺寸是相同的或接近相同的，则该集成选择遇到如上所指出的同样的问题，因为对于焊球焊盘来说可能没有足够的地方以存在于其中一个管芯上。
更进一步，堆叠多个芯片(图3)的处理可能需要每一个管芯都非常非常的薄，以使将被附接到包含焊料凸起焊盘的芯片104上的芯片102的高度将小于焊球凸起202本身的高度。解决该问题的事实是多芯片上的多芯片堆叠的总高度将可能必须很小以使它能够安装在标准封装内。这需要处理许多非常薄的晶片或管芯，然后对这些薄的晶片进行双面处理。结果是，存在产率降低和损坏管芯的重大风险，特别地，如果焊球202必须被安装在那些非常薄的片上。
如图4所示，又一个集成选择是使用被称为“插入机构”的无源器件402，该无源器件能够被用作走线元件将两个管芯从外部连接在一起。该方法具有以下优点，它消除了两个管芯404、406的尺寸是否是相同的或接近的问题，因为它总是能够被做得足够的大以容纳接合线或者焊料块连接。然而，插入机构典型地还具有重大不足。举例来说，他们通常需要全新部件(插入机构及它的附接走线408)的制造，该全新部件的制造可能是复杂的和成本高的。另外，典型的插入机构选择未消除处理非常薄的晶片或者进行这些非常薄的晶片的双面处理的问题，所以上面提及的减小的产率和增加的损害风险仍然存在。更进一步，插入机构典型地非常厚，所以，即便插入机构具有直通连接408，两个管芯之间的连接的长度现在更大，所以芯片与芯片连接的电气性能可能劣化。
插入机构选择还不能免除上面指出的创建多芯片与多芯片叠堆(图5)的问题。
此外，用这样的方法，可能需要在包含有源器件的芯片中使用通孔，在某些应用中，因为通孔占据潜在的电路区域，增加了产率降低的风险，或者两者都有，所以它们并不是合乎需要的。
又进一步，将第三“芯片”添加至堆叠，每一个单个的芯片必须比只具有两个芯片的选择甚至更薄，如此进一步增加产率减小和损坏的风险。
因此，存在对于这样的封装选择的需求，它不会遭受目前可用的前述选择所呈现的问题和/或风险。
发明内容
我们已经开发了用于将芯片集成在一起的处理，其减少或者消除了上述处理中存在的问题。
取决于特定的变形例，我们的方法能够提供下述优点的一个或多个：它们可以使用任意尺寸的两个芯片，它们可以允许最后的堆叠高度非常薄以使多芯片上的多芯片配置能够被创建，它们可以去除在有源芯片中形成通孔的需要，它们可以去除完全形成直通管芯通孔(即，不管管芯是否包含装置)的需要，它们可以去除特别地创建插入结构芯片的需要，它们包含厚的和稳定的平台，它们去除进行单个管芯的双面处理的需要，以及它们还允许小的、密集的连接的使用，而不存在由插入机构直通通孔结构影响“打击”电气性能。
一个实例变形例包含一种封装方法。该方法包含将第一芯片附接至稳定的基底，在稳定的基底上的多个位置形成触点焊盘，在稳定的基底上施加介质以致它使第一芯片的侧面电绝缘，在介质上形成电通路，将第二芯片附接至第一芯片以形成组件，以及移除稳定的基底。
另一个实例变形例包含一种封装，该封装具有至少两个彼此电连接的芯片，至少一个触点焊盘，从触点焊盘延伸至芯片的至少一个上的触点的导电通路，平坦化介质和平坦化介质顶部上的涂覆材料。
通过本文中描述的一个或多个变形例的使用，能够实现本文描述的一个或多个不同优点。本文中描述的优点和特征是可从代表性的实施例获得的许多优点和特征中的一部分，并且仅仅是为了帮助理解本发明而陈述的。应当理解的是这些优点和特征并不考虑作为对权利要求所限定的本发明的限制，或者对权利要求的等效物的限制。例如，这些优点中的一些优点是互相矛盾的，它们不能同时地存在于单个实施例中。类似地，某些优点可适用于本发明的一个方面，但不适用于其他方面。如此，这些特征和优点的总结在确定等效性时不应当被认为是决定性的。本发明另外的特点和优点在以下说明中从附图和权利要求中变得显而易见。
附图说明
图1以十分简化的形式图解了具有接合线外部连接的芯片堆叠；
图2以十分简化的形式图解了具有焊球外部连接的芯片堆叠；
图3以十分简化的形式图解了芯片堆叠上的芯片；
图4以十分简化的形式图解了芯片堆叠的基于插入机构的方法；
图5以十分简化的形式图解了基于插入机构的多芯片对多芯片堆叠；
图6以十分简化的形式图解了适合于作为起始点使用的稳定的基底的实例；
图7以十分简化的形式图解了在支撑涂层已经被施加之后稳定的基底的实例；
图8以十分简化的形式图解了，在支撑涂层中已经形成开口之后的稳定的基底的实例的放大部分；
图9以十分简化的形式图解了，在支撑涂层中已经形成的开口内已经形成焊盘之后的稳定的基底的实例的放大部分；
图10以十分简化的形式图解了，在所有用于放大部分的第一芯片已经被附接于稳定的基底之后，稳定的基底的实例的放大部分；
图11以十分简化的形式图解了，在第一芯片的表面实施平坦化之后稳定的基底的实例的放大部分；
图12以十分简化的形式图解了，在某些区域中的平坦化介质被移除以使得至少焊盘主体被暴露之后的稳定的基底的实例的放大部分；
图13以十分简化的形式图解了在形成触点之后的稳定的基底的实例的放大部分；
图14以十分简化的形式图解了，第二芯片已经被附接于组件之后组件的放大部分；
图15以十分简化的形式图解了，在添加涂覆材料之后图14的复杂的组件；
图16以十分简化的形式图解了，在稳定的基底的移除之后的图15的复杂的组件；
图17以十分简化的形式图解了，在添加导电的接合材料之后图16的复杂的组件；
图18以十分简化的形式图解了，从图15的复杂的组件切割出的两个单个的封装单元；
图19以十分简化的形式图解了，在形成触点之后的稳定的基底的实例的放大部分；
图20以十分简化的形式图解了，在第二芯片已经被附接于组件以形成更复杂的组件之后，组件的放大部分；
图21以十分简化的形式图解了，在添加如上所述的涂覆材料之后图20的复杂的组件；
图22以十分简化的形式图解了，在稳定的基底的移除之后的图21的复杂的组件；
图23以十分简化的形式图解了，在添加如上所述的导电的接合材料之后图22的复杂的组件；
图24以十分简化的形式图解了，从如上所述的图22的复杂的组件切割出的两个单个的封装单元；
图25以十分简化的形式图解了，在其中从第一族方法得到的单个的封装单元经由焊料球块被从外部连接到插入机构的焊盘的变形例；
图26以十分简化的形式图解了，在其中从第一族方法得到的单个的封装单元通过接合线连接被从外部连接到某些其他元件(未显示)的变形例；
图27以十分简化的形式图解了，在其中从第二族方法得到的单个的封装单元经由焊料球块被从外部连接到插入机构的焊盘的变形例；以及
图28以十分简化的形式图解了，在其中从第二族方法得到的单个的封装单元通过接合线连接被从外部连接到某些其他元件的变形例。
具体实施方式
现在将参照两个简化实例的主要实施变形例来描述本方法。如图6到图18所示的第一简化实例实施族，包括芯片封装的创建，该芯片封装包含不同尺寸的两个芯片的堆叠，其中堆叠中的初始芯片宽度比将被堆叠在它上面的芯片的宽度要小。第二简化实例实施族包括芯片封装的创建，该芯片封装包含不同尺寸的两个芯片的堆叠，其中堆叠中的初始芯片宽度比将被堆叠在它上面的芯片的宽度要大。使用这两个主要的实例是因为它们是两个极端，所有包括同样尺寸的芯片的其他实例都落在这两者之间。
值得注意地，为了说明的简便，只描述与理解本方法有关的步骤。因此，可能需要从一个被描述的步骤前进到另一个所需要进行的附加的简单的中间步骤。然而，那些中间步骤对于适当的读者来说是不证自明的。举例来说，描述步骤可以包含在特定的区域中沉积金属。从该说明书中，应当理解的是，对于缺少表述的处理，以及实现转换所需要的或唯一的方法，可以使用任何合适的已知的中间处理。举例来说，一个变形例可以包含，施加光致抗蚀剂、图案化、金属沉积、光致抗蚀剂的剥落，以及，如果适当的话，过涂覆层的去除。另一个变形例可以包含无电镀或电镀，并且如此图案化、籽晶沉积等。因此，除非特别地说明，否则应该认为从处理中一个点到达处理中的另一个点的任何已知的方法可以被使用并且是可接受的。
处理从一块材料开始，该块材料用作稳定的基底，该基底用于大部分的处理，但在后面将被移除。取决于特定的实施，该基底可以是许多不同事物中的任一，举例来说，能够通过刻蚀处理在后面被移除的硅晶片，或者诸如玻璃、蓝宝石、石英、聚合物等的材料。相关的方面是i)将被用作基底的材料具有足够的刚性和稳定性以经受住如下所述的处理步骤，以及ii)在处理中必要时，能够使用不会损坏所创建的封装的技术来移除该材料，无论该处理是否包含通过化学、物理或者热作用(或它们的组合)或一些其他的处理的移除。
该材料的用途是主要地在处理步骤期间提供机械的支撑，从而避免上面指出的薄晶片处理问题，这是因为就包含“薄的”组件这方面来说，它们在芯片级被处理，同时仍允许在晶片级进行主要步骤。
有利地，通过该方法，虽然直通芯片通孔与本文描述的技术是不矛盾的，可以与某些实施一起使用，但即使直通芯片通孔不需要是本文描述的技术的一部分，也可以使用如通过引用被并入本文的序列号为11/329,481、11/329,506、11/329,539、11/329,540、11/329,556、11/329,557、11/329,558、11/329,574、11/329,575、11/329,576、11/329,873、11/329,874、11/329,875、11/329,883、11/329,885、11/329,886、11/329,887、11/329,952、11/329,953、11/329,955、11/330,011以及11/422,551的美国专利申请中描述的触点形成和使用技术。
现在将参照附图描述该处理，记住即便是为了解释的目的可以提供指定的尺寸，但是为了表述的简便尺寸不是按比例的并且有较大变形。
图6以十分简化的形式图解了适合于作为起始点使用的稳定的基底600的实例。此实例的稳定的基底600是硅的晶片，直径大约是300mm，厚度为800μm。
最初，支撑涂层702的薄层，举例来说大约0.5μm，被施加至稳定的基底600的表面704。取决于后面被用来去除稳定的基底600的方法，如下所述的，可以选择能够用作用于后面的处理的蚀刻终止层的材料，作为最后允许稳定的基底600材料的干净移除而不损伤芯片和在后面的步骤中将被添加的连接的分离层，或两者的支撑涂层702。
取决于特定的实施，支撑涂层702可以是氧化物或者其它的电介质、聚合物、金属、沉积的半导体材料或者它们的某些组合。
在一个实例变形例中，支撑涂层702被简单地用作蚀刻终止层，当处理完成时，蚀刻终止层将被留在原地。
在另一个实例变形例中，支撑涂层702被用作在后面的处理步骤中将被移除的蚀刻终止层。
在又一个实例变形例中，支撑涂层702被用作分离层，分离层通过蚀刻使得稳定的基底600从随后沉积的部分(将在下面更详细地讨论)分离。
在又一个实例中，支撑涂层702是组合物。在该组合情形中，举例来说，可以添加金属作为蚀刻终止层，随后可以沉积电介质以阻止在如下所述的后面步骤中创建的连接焊盘在最后工作被完成之后被短接。在该特定的实例情形中，电介质将因此保留而将被用作蚀刻终止层的金属将最终被移除。
图7以十分简化的形式图解了在支撑涂层702已经被施加之后稳定的基底600的实例。为说明该实例的目的，支撑涂层702是电介质。
接下来，在支撑涂层702中将形成最终的连接焊盘的区域中形成开口802。开口802向下延伸至支撑材料，以使将在那些开口802中将被创建的最后的触点在稳定的基底600被移除之后是可达到的。
取决于特定的实施，可以使用适用于所使用的特定的支撑涂层702的任何方法来创建开口。
图8以十分简化的形式图解了，在支撑涂层702中已经形成开口802之后的稳定的基底600的实例的放大部分800。为了该实例解释的目的，已经通过图案化和蚀刻形成开口。
接下来，形成用于最终的触点的焊盘902。取决于特定的实施变形例，焊盘902可以被设定大小，并且材料是适用于传统的焊接或接合线连接焊盘的或者可以由适用于其它类型的连接触点的材料构成，举例来说，适用于与柱和穿透连接或者上面合并的申请中描述的其他类型的连接的材料，以及金立柱块、铜柱或者类似镶焊料的铜柱、覆盖金的铜等合适的金属的组合或合金。此外，如下面结合图17所述的，层可以并入导电的接合材料，以使他们随后在处理中不必被分离地放置。
图9以十分简化的形式图解了，在支撑涂层702中已经形成的开口802内已经形成焊盘902之后的稳定的基底600的实例的放大部分。如图所示，焊盘902由下衬铜的焊盘主体906的沉积金的层904组成。在某些变形例中，焊盘902可以是或者包含传统的凸块下金属(UBM)组材料，举例来说，镍/金。在其他的变形例中，它可以是具有镍或者金作为阻隔层或者氧化阻隔层的传统的铝或者铜焊盘。另外要注意，层904可以另外地在其下面具有某些材料，举例来说，固体材料或者如上面并入的申请中描述的“韧性的”或者“刚性的”材料，以允许不同类型的堆叠选择。在某些变形例中，这些材料可以在开始处理之前被附接至或部分嵌入稳定的基底600中合适的位置。最后，尽管所描述的指定的材料全部是导电的，但是在某些变形例中，焊盘902的一些位置可以填充不导电的材料(举例来说，如果它们被用于对准或间隔的目的)。
接下来，第一芯片1002被放置并被附接于稳定的基底600，在这种情况下，以使它是“面朝上的”(即，芯片上的电路朝向远离稳定的基底600的方向)。在不具有直通通孔的芯片的情形中，芯片以适合于形成第一芯片1002和稳定的基底600之间的物理连接的任意方式被附接。取决于特定的实施，附接可以包含，举例来说，使用环氧树脂、焊料、共价结合、钉扎和/或熔合连接、热压缩、晶片熔融、铜熔融、粘合剂或者热释放接合带或薄膜等。
替代地并有利地，在某些实施变形例中，焊盘902甚至可以被构造为后面用作接合线或者倒装芯片焊盘，作为倒装芯片块本身或作为焊盘和块的组合。
选择性地，如果第一芯片1002具有如上面并入的申请中描述的传统直通芯片通孔，或者直通芯片连接或通孔，则第一芯片1002可以被“面朝下”附接，于是它从底部形成接触。
取决于特定的实施，第一芯片1002可能已经经受它的初始晶片切割前或切割后的附加处理。然而，在该处理中使用之前，对第一芯片1002的最后处理步骤理想地应该是使晶片变薄然后从它切割出单个芯片，或者从晶片中切割出芯片然后使芯片变薄，以便只以薄的形式处理单个芯片。
图10以十分简化的形式图解了，在所有用于放大部分的第一芯片1002已经被附接于稳定的基底600之后，稳定的基底600的实例的放大部分800。
一旦第一芯片1002已经被附接于稳定的基底600，使用平坦化介质1102使稳定的基底600的表面平坦化。
取决于特定的实施变形例，平坦化介质1102可以是旋制氧化矽(spin on glass)、聚合物、环氧树脂、电介质、氧化物、氮化物或者其它的适合的材料，重要的方面是平坦化介质1102是不导电的并将形成或能够被处理为形成实质上平坦的表面。
在某些变形例中，平坦化介质1102被施加以使它与第一芯片1002的顶部一致的或者接近一致。在这种情况下，如果材料将自然地形成平坦的表面，在这个步骤内可以不需要进一步的处理。替代地，在其他变形例中，平坦化介质1102被施加以使它覆盖第一芯片1002并可以或不可以自然地形成平坦表面。在这种情况下，可以通过进一步处理使平坦化介质1102平坦化，举例来说，抛光、研磨、蚀刻、剥离、显影材料等。在另一个类似于第二种情形的变形例中，只有第一芯片1002的表面1004(或者其中的一些部分)可以通过例如一个或多个前述处理被再次暴露。替代地，如果第一芯片尺寸等于或大于将被堆叠在它上面的芯片的触点区域的尺寸，如果第一芯片1002的高度足够地短，可以使用共形的绝缘涂层的简单使用以至少覆盖第一芯片1002的侧面。一般说来，该步骤相关的方面是将表面形成为使得金属走线层能稍后被添加而无需创建至第一芯片1002的侧面的开路或者短路。
图11以十分简化的形式图解了，在第一芯片1002的表面1004实施平坦化之后稳定的基底600的实例的放大部分800。
接下来，指定区域1202中的平坦化介质1102被移除以使得焊盘主体906以及为了形成连接的目的其他任何需要被暴露的区域暴露。
有利地，如果平坦化介质1102是光敏材料，诸如光敏聚酰亚胺，则可以使用简单的图案化和曝光以使得平坦化介质1102对于该步骤就绪。注意作为该步骤的部分，可以在任何需要或希望的地方进行蚀刻，举例来说，在第一芯片1002的顶部、焊盘主体906的顶部(如图12中所示)、某些其他区域的顶部等，只要第一芯片1002的侧面被保护以使在后续步骤中不希望有的短路不会在那些区域发生。
图12以十分简化的形式图解了，在某些区域中的平坦化介质1102被移除以使得至少焊盘主体902被暴露之后的稳定的基底600的实例的放大部分800。注意，在图12的实例中，在第一芯片1002上已经进行额外的蚀刻以允许触点柱的创建。
在这一点上，金属连接1302、1304被形成以使，举例来说，焊盘主体902被连接至第一芯片1002，焊盘主体902、其它的连接点被重走线至能够最终与另一个芯片或者其它的元件的对应的连接对齐的位置，或者(可选地，如果需要)形成升起触点1306。当然，在许多变形例中，将出现这些中两者的一些组合，并且在某些情形中，焊盘主体902可以有意地被连接到另一个焊盘主体(未显示)。
因为第一芯片1002的高度可以较小，由于它仅作为管芯被处理，通过平坦化介质1102的移除而形成的开口可以具有小的深宽比。这允许用于形成连接的低成本沉积技术或者甚至简单的镀敷处理的使用。换句话说，事实上可以被使用的专用的或先进的通孔填充技术是不需要的，处理可以花费更少。
图13以十分简化的形式图解了，在触点1302、1304、1306形成之后的稳定的基底600的实例的放大部分800。
在这一点上，封装组件1308已经被创建，适合于第一芯片1002上的第二芯片1402的添加。如此，在下一步骤中，第二芯片1402被附接于组件1308。注意，因为到目前为止的全部处理已经包含厚的衬底(即稳定的基底600)，该处理比两个芯片通过杂化被结合至非常薄的衬底相比更稳固。还要注意到，尽管第二芯片1402此时可以是薄的，第二芯片1402的所有触点1404理想地将已经被放在第二芯片1402上，然而它仍然处于晶片形式并且较厚，然后包含第二芯片1402的晶片可以被减薄、切割并且第二芯片1402可以被附接于组件1308。
有利地，现在应该理解的是，通过本文描述的变形例的使用，用于处理的双面处理和薄晶片尺度处理被减少，或者理想地被去除。
回到处理，此时第二芯片1402对准并附接于组件1308的各个连接点。取决于特定的实施变形例，这可以包含传统的焊料连接、钉扎&熔合方法、柱和穿透连接、共价结合等。
有利地，在使用紧间距连接(例如＜50μm间距，优选＜30μm)的情形中，钉扎&熔合方法是希望的，尽管不是必要的。另外，独立于紧间距连接或与紧间距连接一起使用诸如上面并入的专利申请中的方法能够形成的低高度(＜25μm高)触点，在将最终封装的总高度保持为较小这方面尤其具有优势。
现在还应该理解的是，本文描述的方法的变形例可以具有由小触点尺寸和短连接长度而没有通孔附加所提供的优点，同时还具有插入机构所提供的优点(即，克服芯片尺寸限制)。另外，在允许厚晶片处理和避免或者去除双面处理的同时可以获得这些优点。
图14以十分简化的形式图解了，在第二芯片1402已经被附接于组件1308以形成更复杂的的组件1406之后，组件1308的放大部分。
此时，主处理完成。然而，如果附加的芯片将被结合至复杂的组件1406，则可以在需要时有利地并简单地重复前步骤的方法。
然而，选择性地，可以继续处理，举例来说，通过添加附加涂覆材料1502，举例来说，以保护芯片，用作导热体、或允许复杂的组件1406变平坦等。取决于特定的实施变形例，涂覆材料1502可选择地可以是对能耐受在下一步骤中的某些情形中可能被使用的蚀刻剂的材料。在大多数的实施变形例中，涂覆材料1502将是不导电类型的材料，并且更具体的是，一种适用于用作平坦化介质1102的材料。有利地，在某些情形中，涂覆材料1502还可以，或者替代地，提供结构支撑以使这里描述的处理所创建的类晶片组件能够在已经移除稳定的基底600之后以类晶片方式被处理。
图15以十分简化的形式图解了，在添加涂覆材料1502之后图14的复杂的组件。
接下来，稳定的基底600被从复杂的组件1406移除。取决于用作稳定的基底600的特定材料，移除能够通过任意多个处理发生，仅有的限制是处理适合于实现所希望的移除并使得焊盘902的稳定的基底600侧暴露。取决于特定的实施，如果涂层702是蚀刻终止层的话，移除能够被对它实施的磨光、研磨和/或蚀刻影响。如果涂层702是牺牲层的话，该层可以通过适当的处理被牺牲(例如，加热、蚀刻、化学反应、光的指定波长，举例来说紫外或者红外曝光等)，借此允许复杂的组件1406从稳定的基底600“飘走”，借此去除了以破坏的方式移除稳定的基底600的需要。如此，对于某些使用牺牲层方法的变形例，稳定的基底600可以变成可再利用的，从而进一步降低成本。
有利地，如果使用蚀刻并且支撑涂层702、平坦化介质1102和涂覆材料1502是耐受蚀刻处理的，则复杂的组件1406中的芯片将完全地被保护免受蚀刻的影响，于是类似湿蚀刻的腐蚀性的处理可以被用于批量处理以无忧地移除稳定的基底600。
随着稳定的基底600的移除，如果支撑涂层702、平坦化介质1102和涂覆材料1502是聚合物，保留的复杂的组件1406是顺应的(compliant)并耐开裂的。
图16以十分简化的形式图解了，在稳定的基底600的移除之后的图15的复杂的组件1406。
此时，如结合图9所描述的，如果用于触点的焊盘902被形成以使例如金或者焊料的接合材料在焊盘902形成的时候被添加，复杂的组件1406将被完全形成，并且在此之后完成封装形成处理所需要完成的仅有的事情是将整个晶片切割成单个封装单元。
替代地，如果将对焊盘902的当前暴露侧使用导电的接合材料1702，举例来说，类似焊料块或者金球，则可以在此时添加导电的接合材料1702。有利地，应当注意的是，因为导电的接合材料1702并未附接于硅的易碎的片的其中之一上，因此在芯片上或者如果使用插入机构，在插入机构上不会产生应力。
图17以十分简化的形式图解了，在导电的接合材料1702的添加之后的图15的复杂的组件1406。
最后，复杂的组件1406被切割成单个的封装单元1802。这里也应该注意的是，即便复杂的组件1406内的单个芯片非常薄，损坏它们的风险仍非常小。
图18以十分简化的形式图解了，从图15的复杂的组件1406切割出的两个单个封装单元1802。
现在将描述第二简化的实例实施族。由于初始步骤与结合图6到图12描述的相同，这里将不再重述那些步骤。另外，由于此实例只是在堆叠中的芯片的相对尺寸上不同于第一简化的实例实施族，因此将只讨论对于这样的区别而格外不同的方面。
在形成图12这样的结果的步骤完成之后，此时，金属连接1902、1904被形成以使，举例来说，焊盘主体902被连接至第一芯片1002，焊盘主体902、其它的连接点重走线至最终对准另一个芯片或某些其他元件的对应的连接的位置，或者(可选地，如果需要)形成升起触点1906。当然，如图13的实例，在许多变形例中，将出现这些中两者的一些组合，并且在某些情形中，焊盘主体902可以有意地被连接到另一个焊盘主体(未显示)。
图19以十分简化的形式图解了，在触点1902、1904、1906形成之后的稳定的基底600的实例的放大部分1900。
在这一点上，如同图13，封装组件1908已经被创建，其适合于第一芯片1002上的第二芯片2002的添加。如此，在下一步骤中，第二芯片2002被附接于组件1908。如同第一实例族，注意，尽管第二芯片2002此时可以较薄，第二芯片2002的所有触点2004理想地将已经被放在第二芯片2002上，同时它仍处于晶片形式和厚度；然后包含第二芯片2002的晶片能够被减薄，切割并且第二芯片2002能够被附接于组件1908。
此时第二芯片2002对准并附接于组件1908的各个连接点。如上所指出的，取决于特定的实施变形例，这可以包含传统的焊料连接、钉扎&熔合方法、柱和穿透连接、共价结合等。
图20以十分简化的形式图解了，在第二芯片2002已经被附接于组件1908以形成更复杂的组件2006之后，组件1908的放大部分。
注意，因为第二芯片2002宽度比第二芯片1402更小，因此第二芯片2002不连接至外围触点1902、1904，而是仅连接至第二芯片2002宽度内的触点1906。然而，通过走线层的使用，外围的触点能够被走线为在第二芯片2002的宽度内，以使，实际上，走线能够将外围的触点移动至不同的并更中心的位置。
此后如结合图15到图18所描述地那样继续处理。如此，图21以十分简化的形式图解了，在如上所述的涂覆材料1502的添加之后图20的复杂的组件2006。
图22以十分简化的形式图解了，在稳定的基底600的移除之后的图21的复杂的组件2006。
图23以十分简化的形式图解了，在如上所述的导电的接合材料1702的添加之后的图22的复杂的组件2006。
图24以十分简化的形式图解了，从如上所述的图22的复杂的组件2006切割出的两个单个的封装单元2402。
从上述内容可知，现在应该很明显的是上述步骤中的一些可以在同样的方法中被重复地采用以添加第三或者附加的芯片。
最后对于这两个族，包含同样大小的两个芯片的变形例能够以如上结合第一或第二实施族所描述的同样的方式被处理，这应该是明显的。
基于如上所述，应该有利地被进一步理解的是，上述方法并非不适用于接合线或者插入机构方法这些方面，应该存在也采用这些方法的需要或希望。
图25以十分简化的形式图解了，在其中从第一族方法得到的单个的封装单元1802经由焊料球块1702被从外部连接到插入机构2504的焊盘2502的变形例。
图26以十分简化的形式图解了，在其中从第一族方法得到的单个的封装单元1802通过接合线连接2602被从外部连接到某些其他元件(未显示)的变形例。
图27以十分简化的形式图解了，在其中从第二族方法得到的单个的封装单元2402经由焊料球块1702被从外部连接到插入机构2504的焊盘2502的变形例。
图28以十分简化的形式图解了，在其中从第二族方法得到的单个的封装单元2402通过接合线连接2802被从外部连接到某些其他元件(未显示)的变形例。
因此应当理解的是本说明书(包括图形)仅仅只是某些示例性的实施例的代表。为了方便读者，上述说明已经集中于所有可能的实施例的代表性实例上，教导本发明的原理的实例上。本说明书并没有试图穷举所有可能的变形例。可替代的实施例可能没有作为本发明的具体部分呈现，或者此外未描述的可替代的实施例可能是可作为一部分得到的，但是这并不被认为是对那些可替代的实施例的放弃。一个普通的技术人员应了解许多那些未描述的实施例结合了本发明的相同原理，并且其他的也是等同的。

Claims (12)

1.一种封装方法，其特征在于，包括：
在基底上形成一触点焊盘；
将第一芯片附接至所述基底；
将平坦化介质放置在所述基底之上以使得所述平坦化介质的表面实质上与所述第一芯片的表面重合；
在所述放置之后在所述平坦化介质上直接形成电通路以创建所述第一芯片和所述触点焊盘之间的电连接；
将第二芯片耦接至所述第一芯片；
在所述第二芯片的至少部分上、所述平坦化介质的至少部分上和所述电通路的至少部分上设置涂覆材料，其中所述涂覆材料与所述第二芯片的所述至少部分、所述平坦化介质的所述至少部分和所述电通路的所述至少部分直接接触；以及
移除所述基底。
2.如权利要求1所述的封装方法，其特征在于，进一步包括在形成触点焊盘之前，将支撑涂层设置在所述基底上，其中然后在所述支撑涂层中形成所述触点焊盘。
3.如权利要求2所述的封装方法，其特征在于，所述支撑涂层包括分离层。
4.如权利要求3所述的封装方法，其特征在于，所述支撑涂层进一步包括蚀刻终止层。
5.如权利要求1所述的封装方法，其特征在于，所述第二芯片被电连接至所述电通路。
6.如权利要求2所述的封装方法，其特征在于，形成触点焊盘进一步包括将所述触点焊盘形成在所述基底上的支撑涂层中的开口内。
7.如权利要求3所述的封装方法，其特征在于，所述支撑涂层与所述平坦化介质直接接触，并且其中移除所述基底包括蚀刻所述分离层和对所述分离层加热中的至少一个。
8.如权利要求1所述的封装方法，其特征在于，所述平坦化介质使得所述第一芯片的侧面电绝缘。
9.如权利要求1所述的封装方法，其特征在于，设置平坦化介质包括将所述平坦化介质施加至超过所述基底的高度，并且其中所述高度实质上与与所述基底相对的所述第一芯片的表面重合。
10.如权利要求1所述的封装方法，其特征在于，进一步包括将选择的区域中的所述平坦化介质移除以暴露所述触点焊盘的与所述基底相对的侧面。
11.如权利要求1所述的封装方法，其特征在于，所述第一芯片以面朝上的方式耦接至所述基底并且所述第二芯片以面朝下的方式耦接至所述第一芯片。
12.如权利要求1所述的封装方法，其特征在于，所述平坦化介质被施加以使得其覆盖所述第一芯片，并且其中所述封装方法进一步包括通过进一步处理平坦化所述平坦化介质。
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