CN101673123B - Bandgap voltage generator with curvature compensation - Google Patents

Abstract

The invention relates to a bandgap voltage generator with curvature compensation, which comprises PMOS pipes P1-P4, transistors Q1-Q4, resistors R1-R4 and an amplifier, wherein the source electrodes of the PMOS pipes P1-P4 are connected with a power supply, the drain electrode of the PMOS pipe P1 is connected with the emitter electrode of the transistor Q1 and the negative input end of the amplifier, the grid electrodes of the PMOS pipes P1-P4 are all connected with the output end of the amplifier, and the collector electrodes and the base electrodes of the transistors Q1-Q4 are all grounded; the drain electrode of the PMOS pipe P2 is connected with the positive input end of the amplifier and is connected with the emitter electrode of the transistor Q2 by the resistor R1; the drain electrode of the PMOS pipe P4 is connected with the emitter electrode of the transistor Q4 and is connected with the drain electrode of the PMOS pipe P3 by the resistor R4; the drain electrode of the PMOS pipe P3 is connected with the emitter electrode of the transistor Q3 by the resistor R2 and is grounded by the R3; and the output end of the bandgap voltage generator is connected with the drain electrode of the PMOS pipe P3. The bandgap voltage generator provided by the invention can work under the voltage of 1V and can enhance the temperature coefficient obviously.

Description

Bandgap voltage generator with curvature compensation

Technical field

The present invention relates to circuit field, relate in particular to bandgap voltage generator with curvature compensation.

Background technology

The band gap voltage generator is the significant components in the simulation system.Band gap voltage generator with conventional structure approximately can be exported the reference voltage of 1.2V, and this reference voltage has the minimum sensitivity to temperature variations.When supply voltage is lower than 1.2V, just conventional structure can't have been re-used.

Have the band gap voltage generator of conventional structure as shown in Figure 1, comprise PMOS pipe P1-P3, transistor Q1-Q3, resistance R 1-R3, and amplifier;

Wherein, the source electrode of PMOS pipe P1-P3 connects supply voltage, drain electrode and the emitter of transistor Q1 and the negative input end of amplifier of PMOS pipe P1, and the grid of PMOS pipe P1-P3 all is connected the equal ground connection of the collector of transistor Q1-Q3 and base stage with the output terminal of amplifier; The drain electrode of PMOS pipe P2 is connected with the positive input terminal of amplifier, and is connected with the emitter of transistor Q2 by resistance R 1; The drain electrode of PMOS pipe P3 is connected with the emitter of transistor Q3 by resistance R 2, and by R3 ground connection; The output terminal of band gap voltage generator is connected with the drain electrode of PMOS pipe P3.Transistor Q1-Q3 is PNP transistor.

Temperature coefficient is very important parameter in the bandgap reference circuit.In fact, transistorized voltage is not along with the linear change of temperature.

By calculating the output voltage V that can obtain structure shown in Figure 1 _REFAs shown in the formula institute's formula:

$V_{\mathrm{REF}}=\frac{R_3}{R_3+R_2}(V_{\mathrm{BEQ}3}+\frac{{2R}_2\ln \left(N\right)}{R_1}{V}_T);$

Wherein, V _BEQ3The voltage between transistor Q3 base stage and the emitter, wherein V _TThermal voltage, V _BGBe the diode voltage under 0 ° of K temperature, N is the ratio of transistor Q2 and Q1, V _BE0The base-emitter voltage under the assigned temperature; η is technological parameter, for standard CMOS process, and η=4.

Can find out that the band gap voltage generator with conventional structure only corrects the first rank (first term).

Summary of the invention

In order to solve above-mentioned technical matters, bandgap voltage generator with curvature compensation is provided, its purpose is, the band gap voltage generator can be worked under lower voltage, and improves temperature coefficient (temperature coefficient).

The invention provides bandgap voltage generator with curvature compensation, comprise PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, and amplifier;

The source electrode of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe connects power supply, the drain electrode of the one PMOS pipe is connected with the negative input end of the emitter of the first transistor and amplifier, the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe are connected with the output terminal of amplifier respectively with the grid of the 4th PMOS pipe, and the first transistor, transistor seconds, the 3rd transistor and the 4th transistorized collector and base stage be ground connection respectively; The drain electrode of the 2nd PMOS pipe is connected with the positive input terminal of amplifier, and is connected with the emitter of transistor seconds by the first resistance; The drain electrode of the 4th PMOS pipe is connected with the emitter of the 4th PMOS pipe, and the drain electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe by the 4th resistance; The drain electrode of the 3rd PMOS pipe is connected with the 3rd transistorized emitter by the second resistance, and the drain electrode of the 3rd PMOS pipe is by the 3rd resistance eutral grounding; The output terminal of band gap voltage generator is connected with the drain electrode of the 3rd PMOS pipe.

The voltage V of the output terminal output of band gap voltage generator _REFCalculate according to following formula:

$V_{\mathrm{REF}}=\frac{R_3}{R_3+R_2}(V_{\mathrm{BEQ}3}+\frac{{2R}_2\ln \left(N\right)}{R_1}{V}_T+\frac{R_2}{R_4}{V}_{\mathrm{NL}});$

$V_{\mathrm{NL}}\&cong;V_{\mathrm{BEQ}3}-V_{\mathrm{BEQ}4}=V_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$V_{\mathrm{BEQ}3}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-(\mathrm{\&eta;}-1)V_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$V_{\mathrm{BEQ}4}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-\mathrm{\&eta;}{V}_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$R_4=\frac{R_2}{\mathrm{\&eta;}-1};$

Wherein: R1, R2, R3 and R4 are respectively the first resistance, the second resistance, the 3rd resistance and resistance value corresponding to the 4th resistance; V _BEQ3The voltage between the 3rd transistorized base stage and the emitter, V _BEQ4Be the voltage between the 4th transistorized base stage and the emitter, η is technological parameter, V _TBe thermal voltage, T is Kelvin's absolute temperature, T ₀The Kelvin's value under the assigned temperature, V _BGBe the band gap voltage of the silicon under 0 ° of K temperature, N is the ratio of the quantity of the quantity of transistor seconds and the first transistor.

The first transistor, transistor seconds, the 3rd transistor and the 4th transistor are PNP transistor.

Band gap voltage generator provided by the invention can be worked under the voltage of 1V, effectively eliminated the second-order temperature mudulation effect of diode by increasing a branch road and resistance, the threshold voltage of metal-oxide-semiconductor does not have the many of supply voltage decline, can obviously improve temperature coefficient simultaneously.

Description of drawings

Fig. 1 is the band gap voltage generator with conventional structure;

Fig. 2 is band gap voltage generator provided by the invention;

Fig. 3 is the synoptic diagram that concerns that has between the temperature of band gap voltage generator of conventional structure and the voltage;

Fig. 4 is the synoptic diagram that concerns between the temperature of band gap voltage generator provided by the invention and the voltage.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in further detail.

Band gap voltage generator provided by the invention comprises PMOS pipe P1-P4, transistor Q1-Q4, resistance R 1-R4, and amplifier as shown in Figure 2;

Wherein, the source electrode of PMOS pipe P1-P4 connects power supply, and the drain electrode of PMOS pipe P1 is connected with the emitter of transistor Q1 and the negative input end of amplifier, and the grid of PMOS pipe P1-P4 all is connected the equal ground connection of the collector of transistor Q1-Q4 and base stage with the output terminal of amplifier; The drain electrode of PMOS pipe P2 is connected with the positive input terminal of amplifier, and is connected with the emitter of transistor Q2 by resistance R 1; The drain electrode of PMOS pipe P4 is connected with the emitter of transistor Q4, and is connected by the drain electrode of resistance R 4 with PMOS pipe P3; The drain electrode of PMOS pipe P3 is connected with the emitter of transistor Q3 by resistance R 2, and by R3 ground connection; The output terminal of band gap voltage generator is connected with the drain electrode of PMOS pipe P3.Transistor Q1-Q4 is PNP transistor.

By calculating the output voltage V that can obtain structure shown in Figure 2 _REFBe shown below:

$V_{\mathrm{REF}}=\frac{R_3}{R_3+R_2}(V_{\mathrm{BEQ}3}+\frac{{2R}_2\ln \left(N\right)}{R_1}{V}_T+\frac{R_2}{R_4}{V}_{\mathrm{NL}});$

Wherein:

$V_{\mathrm{NL}}\&cong;V_{\mathrm{BEQ}3}-V_{\mathrm{BEQ}4}=V_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$V_{\mathrm{BEQ}3}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-(\mathrm{\&eta;}-1)V_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$V_{\mathrm{BEQ}4}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-\mathrm{\&eta;}{V}_T\mathrm{<figure-callout\; id="0"\; label="ln\; T\; T"\; filenames="H2009101964450E00022.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{T}{T_{}}\frac{{}_0}{};$

$R_4=\frac{R_2}{\mathrm{\&eta;}-1}.$

Contain resistance R 2 in the transistor Q3 branch road, and the branch road of Q4 does not comprise resistance, so the electric current of Q3 branch road is relevant with absolute temperature, the electric current of Q4 branch road is then temperature independent.

Band gap voltage generator provided by the invention can be corrected the first rank and second-order (second term).

Fig. 3 has shown the temperature of the band gap voltage generator with conventional structure and the relation between the voltage, and its temperature coefficient is 108ppm/C; Horizontal ordinate is the temperature range-20 ℃～85 ℃ of simulation scanning, and ordinate is the output voltage of band gap, and temperature coefficient is minimum in the time of 20 ℃.

Fig. 4 has shown the synoptic diagram that concerns between the temperature of band gap voltage generator provided by the invention and the voltage, and its temperature coefficient is TC=68ppm/C.Horizontal ordinate is the temperature range-20 ℃～85 ℃ of simulation scanning, and ordinate is the output voltage of band gap, and temperature coefficient is minimum in the time of 20 ℃.

Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determined by the scope of claims.

Claims (3)

1. bandgap voltage generator with curvature compensation is characterized in that, comprises PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe, the first transistor, transistor seconds, the 3rd transistor, the 4th transistor, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, and amplifier;

The source electrode of the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe and the 4th PMOS pipe connects power supply, the drain electrode of the one PMOS pipe is connected with the negative input end of the emitter of the first transistor and amplifier, the one PMOS pipe, the 2nd PMOS pipe, the 3rd PMOS pipe are connected with the output terminal of amplifier respectively with the grid of the 4th PMOS pipe, and the first transistor, transistor seconds, the 3rd transistor and the 4th transistorized collector and base stage be ground connection respectively; The drain electrode of the 2nd PMOS pipe is connected with the positive input terminal of amplifier, and is connected with the emitter of transistor seconds by the first resistance; The drain electrode of the 4th PMOS pipe is connected with the 4th transistorized emitter, and the drain electrode of the 4th PMOS pipe is connected with the drain electrode of the 3rd PMOS pipe by the 4th resistance; The drain electrode of the 3rd PMOS pipe is connected with the 3rd transistorized emitter by the second resistance, and the drain electrode of the 3rd PMOS pipe is by the 3rd resistance eutral grounding; The output terminal of band gap voltage generator is connected with the drain electrode of the 3rd PMOS pipe.

2. bandgap voltage generator with curvature compensation as claimed in claim 1 is characterized in that, the voltage V of the output terminal output of band gap voltage generator _REFCalculate according to following formula:

$V_{\mathrm{REF}}=\frac{R_3}{R_3+R_2}(V_{\mathrm{BEQ}3}+\frac{{2R}_2\ln \left(N\right)}{R_1}{V}_T+\frac{R_2}{R_4}{V}_{\mathrm{NL}});$

$V_{\mathrm{NL}}\&cong;V_{\mathrm{BEQ}3}-V_{\mathrm{BEQ}4}=V_T\ln \frac{T}{T_0};$

$V_{\mathrm{BEQ}3}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-(\mathrm{\&eta;}-1)V_T\ln \frac{T}{T_0};$

$V_{\mathrm{BEQ}4}=V_{\mathrm{BG}}-(V_{\mathrm{BG}}-V_{\mathrm{BE}0})\frac{T}{T_0}-\mathrm{\&eta;}{V}_T\ln \frac{T}{T_0};$

$R_4=\frac{R_2}{\mathrm{\&eta;}-1};$

Wherein: R1, R2, R3 and R4 are respectively the first resistance, the second resistance, the 3rd resistance and resistance value corresponding to the 4th resistance; V _BEQ3The voltage between the 3rd transistorized base stage and the emitter, V _BEQ4The voltage between the 4th transistorized base stage and the emitter, V _BE0Be base stage under the assigned temperature and the voltage between the emitter, η is technological parameter, V _TBe thermal voltage, T is Kelvin's absolute temperature, T ₀The Kelvin's value under the assigned temperature, V _BGBe the band gap voltage of the silicon under 0 ° of K temperature, N is the ratio of transistor seconds and the first transistor.

3. bandgap voltage generator with curvature compensation as claimed in claim 1 or 2 is characterized in that, the first transistor, and transistor seconds, the 3rd transistor and the 4th transistor are PNP transistor.

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