CN101673718A - 半导体装置及其制造方法、电路基板和电子机器 - Google Patents

半导体装置及其制造方法、电路基板和电子机器 Download PDF

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CN101673718A
CN101673718A CN200910179067A CN200910179067A CN101673718A CN 101673718 A CN101673718 A CN 101673718A CN 200910179067 A CN200910179067 A CN 200910179067A CN 200910179067 A CN200910179067 A CN 200910179067A CN 101673718 A CN101673718 A CN 101673718A
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semiconductor device
resin bed
wiring part
distribution
semiconductor element
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CN101673718B (zh
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伊东春树
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

本发明的目的在于，提供可以相应于大型芯片、通过细密配线形成多个外部端子、而且连接可靠性高的半导体装置。该半导体装置是在具有多个电极(9)的半导体元件(2)上形成(1)层或多层树脂层、与电极(9)电连接的多个配线(4)和与该配线(4)电连接的多个外部端子(7)的半导体装置(1)，多个配线(4)的一部分或全部由从与电极(9)连接的部分向着半导体元件(2)的中心(10)方向的第1配线部(4a)、和与该第1配线部(4a)连接、从半导体元件(2)的中心(10)方向向着外侧与外部端子(7)连接的第2配线部(4b)形成，在第1配线部(4a)和第2配线部(4b)之间至少形成1层树脂层。

Description

半导体装置及其制造方法、电路基板和电子机器
技术领域
本发明涉及一种半导体装置及其制造方法、电路基板和电子机器，涉及连接可靠性高的半导体装置及其制造方法、搭载有该半导体装置的电路基板和具有该半导体装置的电子机器。
背景技术
为了高密度地安装半导体装置，希望进行不使半导体芯片封装而以原样的状态安装的裸芯片安装。但是，以裸芯片安装对半导体芯片的保护十分不利，操作也困难。因此，提出使用CSP(Chip Size Package芯片尺寸的封装)的半导体装置，特别是近年开发了由晶片进行切割(切断)的晶片原样成为半导体装置的晶片级CSP。在该晶片级CSP中，在形成微小的晶体管等的硅晶片的表面上形成树脂层或配线，通过将该硅晶片切断成各个半导体装置，以制造半导体装置。
在现有的适用晶片级CSP的半导体装置的制造方法中，当硅晶片的表面上形成树脂层时，使被切割的部分不形成树脂层那样进行，以便防止半导体装置端部缺口或树脂层剥离(例如，参照特许文献1)。
【专利文献1】国际公开第01/071805号小册子(图1、图14)
发明内容
但是，在现有的适用晶片级CSP的半导体装置的制造方法(例如，参照专利文献1)中，在半导体元件的中心附近形成树脂层及外部端子，使配线从在半导体元件的外周部形成的电极延伸到该外部端子而进行连接。这时，从电极向着半导体元件的中心方向延伸配线、直接与外部端子连接时，因半导体装置产生的应力等，存在与配线的外部端子连接的部分容易断线的问题。特别是晶片级CSP的情况下，形成配线的外部端子的部分(称为岸面的部分)大，有时该岸面附带的根断线。
另外，在现有的适用晶片级CSP的半导体装置的制造方法(例如，参照专利文献1)中，由于越从半导体元件的中心偏离、应力就越大，所以芯片尺寸大时，存在在半导体元件的外周部形成的岸面附带的根容易断线的问题。
另外，在该半导体装置的制造方法中，由于使配线从在半导体元件的表面上形成的电极延伸到树脂层上而形成，配线存在阶差，所以存在细密配线困难的问题。
本发明的目的在于，提供一种可以相应于大型芯片、通过细密配线形成多个外部端子、而且连接可靠性高的半导体装置。其目的还在于，提供该半导体装置的制造方法、搭载了该连接可靠性高的半导体装置的电路基板和具有该半导体装置的电子机器。
本发明的半导体装置是在具有多个电极的半导体元件上形成1层或多层树脂层、与电极电连接的多个配线和与该配线电连接的多个外部端子的半导体装置，其中，该多个配线的一部分或全部由从与电极连接的部分向着半导体元件的中心方向的第1配线部，和与该第1配线部连接、从半导体元件的中心方向向着外侧与外部端子连接的第2配线部所形成，在第1配线部和第2配线部之间至少形成有1层树脂层。
由于该多个配线的一部分或全部由从与电极连接的部分向着半导体元件的中心方向的第1配线部、和从半导体元件的中心方向向着外侧与外部端子连接的第2配线部形成，所以配线的纵断面形状成为コ字型，可以有效地缓和应力。另外，与配线的外部端子连接的部分在半导体元件的中心侧出来，即使在半导体装置发生应力的情况下，也可以防止配线与外部端子连接的部分发生断线。另外，由于第1配线部和第2配线部之间至少形成1层树脂层，所以可以进一步缓和配线中产生的应力，也就可以与伴随大型芯片化的应力的增大相对应。
另外，只要在树脂层上不形成第1配线部、不设阶差，就细密配线成为可能，形成多个外部端子。
另外，本发明的半导体装置，其上述半导体装置的封装方式是芯片·尺寸·封装。
在半导体装置的封装方式是芯片·尺寸·封装(CSP)的情况下，如上述那样，有配线与外部端子连接的部分发生断线的问题。因此，在芯片·尺寸·封装的半导体装置中，只要适用上述那样的结构的配线，就可以有效地防止配线的断线。
另外，本发明的半导体装置，其上述外部端子由焊球构成。
在芯片·尺寸·封装的半导体装置中，作为外部端子多数情况下使用焊球。由该焊球构成的外部端子形成配线的部分(称为岸面的部分)大，存在该岸面的附带的根断线的问题，但是通过形成上述结构的配线就可以防止岸面的附带的根的断线。
另外，本发明的半导体装置至少在1层树脂层上形成有用于连接第1配线部和第2配线部的穿孔(via hole)。
例如，只要在第1配线部和第2配线部之间形成的树脂层上形成用于连接它们的穿孔，就可以容易地连接第1配线部和第2配线部，还提高了连接的可靠性。
另外，本发明的半导体装置，通过切割切断由硅晶片构成的半导体元件的集合体，制造该半导体装置。
由于例如通过使形成微小的晶体管等的硅晶片进行切割而切断制造半导体装置，所以可以由1枚硅晶片得到多个半导体装置。
另外，本发明的半导体装置避开半导体元件的集合体的由切割切断的部分而至少形成有1层树脂层。
由于至少形成1层树脂层，避开半导体元件的集合体的由切割切断的部分而形成的，所以可以防止半导体装置端部的缺口和树脂层的剥离。
另外，本发明的半导体装置在形成电极的部分上至少形成有1层树脂层。
例如，只要在形成电极的部分上形成在第1配线部和第2配线部之间形成的树脂层，就能够使形成外部端子的区域扩展、形成多个外部端子。
本发明的半导体装置的制造方法是在具有多个电极的半导体元件上形成1层或多层树脂层、与电极电连接的多个配线和与该配线电连接的多个外部端子的半导体装置的制造方法，其中，在该半导体元件上、从与电极连接的部分向着半导体元件的中心方向形成第1配线部后，至少形成1层树脂层，形成与第1配线部连接、从半导体元件的中心方向向着外侧与外部端子连接的第2配线部。
由于在半导体元件上从与电极连接的部分向着半导体元件的中心方向形成第1配线部后，至少形成1层树脂层，形成与第1配线部连接、从半导体元件的中心方向向着外侧与外部端子连接的第2配线部，所以配线的纵断面形状成为コ字型，可以有效地缓和应力。另外，与配线的外部端子连接的部分在半导体元件的中心侧出来，即使在半导体装置发生应力的情况下，也可以防止配线与外部端子连接的部分发生断线。
另外，由于第1配线部和第2配线部之间至少形成1层树脂层，所以可以进一步缓和配线产生的应力，也就可以与伴随大型芯片化的应力的增大相对应。
另外，只要在树脂层上不形成第1配线部、不设阶差的方式，就可以细密配线，形成多个外部端子。
另外，本发明的半导体装置的制造方法，其上述半导体装置的封装方式是芯片·尺寸·封装。
在半导体装置的封装方式是芯片·尺寸·封装(CSP)的情况下，如上述那样，有配线与外部端子连接的部分发生断线的问题。因此，在芯片·尺寸·封装的半导体装置中，只要形成如上述那样结构的配线，就可以有效地防止配线的断线。
另外，本发明的半导体装置的制造方法，其上述的外部端子由焊球构成。
在芯片·尺寸·封装的半导体装置中，作为外部端子多数情况下使用焊球。由该焊球构成的外部端子形成配线的部分(称为岸面的部分)大，存在该岸面的附带的根断线的问题，但是通过形成上述结构的配线就可以防止岸面的附带的根断线。
另外，本发明的半导体装置的制造方法，至少在1层树脂层上形成用于连接第1配线部和第2配线部的穿孔。
例如，只要在第1配线部和第2配线部之间形成的树脂层上形成用于连接它们的穿孔，就可以容易地连接第1配线部和第2配线部，还提高了连接的可靠性。
另外，本发明的半导体装置的制造方法，通过切割而切断由硅晶片构成的半导体元件的集合体而制造上述半导体装置。
由于例如通过使形成微小的晶体管等的硅晶片进行切割而切断制造半导体装置，所以可以由1枚硅晶片得到多个半导体装置。
另外，本发明的半导体装置的制造方法，避开集合体的由切割切断的部分而至少形成1层树脂层。
由于避开半导体元件的集合体的由切割而切断的部分而至少形成1层树脂层，所以可以防止半导体装置端部的缺口和树脂层的剥离。
另外，本发明的半导体装置的制造方法，在形成电极的部分上至少形成1层树脂层。
例如，只要在形成电极的部分上形成在第1配线部和第2配线部之间形成的树脂层，就可以使形成外部端子的区域扩展、形成多个外部端子。
本发明的电路基板可以搭载有上述任一种半导体装置。
由于该电路基板可以搭载有上述任一种半导体装置，所以连接的可靠性高。
本发明的电子机器可以具有上述任一种半导体装置。
由于该电子机器可以具有上述任一种半导体装置，所以由半导体装置的连接不良造成的故障少，可靠性就高。
附图说明
图1是本发明实施方式1的半导体装置的俯视图和纵剖面图。
图2是表示不适用实施方式1的配线结构的半导体装置例的俯视图和纵剖面模式图。
图3是表示本发明实施方式2的半导体装置的制造工序的俯视图。
图4是表示继续图3的半导体装置的制造工序的俯视图。
图5是表示继续图4的半导体装置的制造工序的俯视图。
图6是表示本发明的实施方式3的电路基板例的立体模式图。
图7是表示本发明实施方式3的电子机器的例。
图中：1-半导体装置，2-半导体元件，3-第1树脂层，4-配线，4a-第1配线部，4b-第2配线部，5-第2树脂层，6-第3树脂层，7-外部端子，8-钝化膜，9-电极，10-中心，11-穿孔，12-连接部，14-第1岸面，15-第2岸面
具体实施方式
(实施方式1)
图1是本发明的实施方式1的半导体装置的俯视图及纵剖面图。另外，图1(a)是实施方式1的半导体装置的1例，使一部分透明而表示的。
本实施方式1的半导体装置1，主要在半导体元件2的一个面上形成第1树脂层3、配线4、第2树脂层5、第3树脂层6、外部端子7而构成的。
另外，如图1所述，配线4由第1配线部4a和第2配线部4b构成，在第1配线部4a和第2配线部4b之间形成有第1树脂层3。另外，在半导体元件2的一个表面上，形成有由绝缘体构成的钝化膜8及电极9，在钝化膜8的表面上形成有第1配线部4a。
设有多个电极9和配线4，并成为电连接的状态。另外，在各个配线4上设有与配线4电连接的外部端子7，结果电极9和外部端子7成为导通的状态。
另外，第2树脂层5，通常多数情况下为了保护配线4和外部端子7而设置，但是也未必必须设置。另外，在本实施方式1中，为了外部端子7的根本的补强，设置第3树脂层6，但是也未必必须设置。
半导体元件2通过前处理硅晶片形成多个微小的晶体管等。而且，通过在硅晶片上形成第1树脂层3、外部端子7等后，使硅晶片进行切割而切断，制造各个半导体装置1。这样使硅晶片进行切割、其直接成为的半导体装置的称为晶片级CSP。这样的晶片级CSP是称为CSP(芯片·尺寸·封装)的封装方式的一种，比以往的CSP向小型化又迈进了一步。另外，在本实施方式1中，作为半导体元件2使用硅(主要是单晶硅)，但是也可以使用镓、砷等其它半导体材料。
在上述的半导体元件2的一个面上形成薄的钝化膜8和由铝等构成的电极9，在钝化膜8的表面上，形成第1配线部4a及第1树脂层3。在本实施方式1中，多个电极9位于半导体元件2的外周部，在形成电极9的部分的上方形成第1树脂层3。这样，通过形成第1树脂层3，可以扩展能够形成外部端子7的区域而形成多个外部端子。另外，在半导体元件2的最外侧的外周部不形成为第1树脂层3的形态。另外，作为第1树脂层3的材料可以使用硅变性聚酰亚胺树脂、环氧树脂、硅变性环氧树脂、苯酚系树脂、丙烯酸树脂、苯并环丁烯(BCB Benzo Cyclo Butene)、聚苯并噁唑(PBO Poly Benz Oxazole)等。
如上所述，配线4由第1配线部4a和第2配线部4b构成，以在钝化膜8的表面上与半导体元件2上的电极9连接方式形成第1配线部4a。第1配线部4a在多个电极9的每个上形成，与电极9连接侧的另一端成为用于与第2连接部4b连接的第1岸面(将在实施方式2中详述)。另外，通过例如使由钛·钨合金构成的层和由铜构成的层多层层叠而形成该第1配线部4a。该第1配线部4a，如图1(a)所示，从与电极9连接的部分向着半导体元件1的中心10的方向形成第1配线部4a。这里，所谓中心10表明是在图1(a)那样的正方形的半导体元件2的情况下，但是，例如在长方形的半导体元件2的情况下是将纵及横方向一分为二的位置，在其它形状的情况下可以理解为是半导体元件2的重心。
另外，在实施方式1中，在钝化膜8的表面上形成第1配线部4a，但是，也可以例如在第1配线部4a和半导体元件2之间还形成其它的树脂层。
第2配线部4b借助于在第1树脂层3上形成的穿孔11与第1配线部4a连接的。另外，在本实施方式1中，在第1树脂层3的表面上形成第2配线部4b，在第1配线部4a和第2配线部4b之间形成第1树脂层3，但是，也可以在第1配线部4a和第2配线部4b之间形成多层树脂层或者加入其它构件。该第2配线部4b从半导体元件2的中心10的方向向着外侧与外部端子7连接，与第1配线部4a连接的部分的另一端成为用于与外部端子7连接的第2岸面(将在实施方式2中详述)。
另外，在本实施方式1中，与在半导体元件2的中心10附近形成的外部端子7连接的第2配线部4b不是按照从半导体元件2的中心10的方向向着外侧与外部端子7连接，而是在正上方与外部端子7连接的形态。另外，在本实施方式1中，如图1(b)所示，在穿孔11的内壁上形成第2配线部4b，但是，也可以在穿孔11的内壁上形成第1配线部4a。
图2是表示不适用实施方式1的配线4的结构的半导体装置的例的俯视图和纵剖面模式图。另外，在图2(a)中，与图1(a)同样，使一部分透明地表示。另外，在图2(b)中，为了方便表示了横向并列的2个外部端子7，与图1相同的部分赋予相同的符号。
在图2所示的半导体装置1中，配线4不是由第1配线部4a和第2配线部4b的2个部分构成而是由1个部分构成。另外，配线4在第1树脂层3的表面上形成，按照从电极9向着半导体元件2的中心10延伸那样形成，从其本身外侧向着中心10与外部端子7连接的。
在图1或图2所示的半导体装置1中，因翘曲等从中心10离开越远越产生大的应力。这里，如图2所示，配线4从外侧向着半导体元件2的中心10与外部端子7连接时，与配线4的外部端子7的连接部12成为从中心10离开的位置，会产生大的应力。因此，如图2所示的以往的半导体装置1中，在连接部12的部分上有时会断线。另外，由于与从中心离开的位置的外部端子7连接的配线4短，所以在产生应力时连接部12的部分容易断线。因此，在本实施方式1的半导体装置1(参照图1)中，通过形成第1配线部4a和第2配线部4b、使第2配线部从半导体元件2的中心10向着外侧与外部端子7连接，就可以防止连接部12断线。
这里，返回到图1所示的本实施方式1的半导体装置1的结构中。在形成第1树脂层3、第1配线部4a和第2配线部4b的半导体元件2的表面上形成有第2树脂层5。但是，在半导体元件2的最外侧的外周部和形成有第2配线部4b的外部端子7的部分(第2岸面，将在第2实施方式中详述)上没有形成第2树脂层5。之所以在半导体元件2的最外侧的外周部上不形成第1树脂层3和第2树脂层5，是由于在通过切割从硅晶片上切断半导体元件2时，可以避开通过切割而切断的部分，可以防止半导体装置1的端部缺口或者树脂层剥离。另外，作为第2树脂层5的材料，既可以使用与第1树脂层3同样的材料，也可以使用与第1树脂层3不同的材料。
在第2配线部4b的前端的第2岸面(将在实施方式2中详述)上形成由焊球构成的外部端子7。该外部端子7在使半导体装置1与电路基板等连接时使用，例如可以由不含铅的无铅软钎料而形成的。
而且，在第2树脂层5的表面上也可以形成第3树脂层6。由于第3树脂层6主要是用于外部端子7的根本补强而形成，所以外部端子7的周边部分成为露出的形状。另外，第3树脂层6以露出外部端子7的一部分的形态形成。该第3树脂层6的材料既可以使用与第1树脂层3同样的材料，也可以使用与第1树脂层3不同的材料。
这里，第1树脂层3、第2树脂层5、第3树脂层6优选以该顺序以成为低弹性那样形成。这样，通过从半导体元件2侧向着外部端子7侧形成低弹性的树脂层，就可以有效地缓和翘曲等的应力。
在本实施方式1中，由于多个配线4的一部分或全部由从与电极9连接的部分向着半导体元件2的中心10方向的第1配线部4a、和从半导体元件2的中心10方向向着外侧与外部端子7连接的第2配线部4b形成，所以配线4的纵断面形状成为コ字型，可以有效地缓和应力。另外，与第2配线部4b的外部端子7连接的部分在半导体元件2的中心侧出来，即使在半导体装置1发生应力的情况下，也可以防止第2配线部4b与外部端子7连接的部分发生断线。另外，由于第1配线部4a和第2配线部4b之间形成第1树脂层3，所以可以进一步缓和配线4上产生的应力，也就可以与伴随大型芯片化的应力的增大相对应。
另外，由于在树脂层上不形成第1配线部4a、不设阶差的形态，就可以进行细密配线，形成多个外部端子7。
(实施方式2)
图3、图4及图5是表示本发明实施方式2的半导体装置的制造工序的俯视图。另外，实施方式2中所示的制造方法是制造实施方式1中所示的半导体装置的制造方法，在图3、图4及图5中，与图1(a)同样使第2树脂层5、第3树脂层6等透明而表示。另外，在图3、图4及图5中仅表示与作为半导体元件2的集合体的硅晶片的1个半导体元件1对应的部分。
首先，通过进行前处理在形成多个微小的晶体管等的硅晶片上形成钝化膜8及电极9(图3(a))。钝化膜8在半导体元件2的单侧表面的电极9以外的部分上形成。另外，电极9在半导体元件2的外周部上形成。
而且，以与半导体元件2上的电极9连接的形态形成多个第1配线部4a(图3(b))。另外，这时，从与电极9连接的部分向着半导体元件2的中心10方向形成第1配线部4a。第1配线部4a的前端成为与其后的第2配线部4b连接的第1岸面14。通过使该第1岸面14形成比较小，就可以形成多个外部端子7，还可以抑制第1岸面14的附带的根部分的断线。
第1配线部4a，通过例如用溅射法在钝化膜8的表面的全面上形成钛·钨合金层和铜层后，以所定的形状涂布保护膜(未图示)，进行蚀刻，仅残留第1配线部4a的部分，剥离保护膜而可以形成。
然后，在图3(b)工序中形成第1配线部4a的钝化膜8的表面上形成第1树脂层3(图3(c))。这时，在第1配线部4a和电极9的部分上也形成第1树脂层3。通过在电极9的部分上形成第1树脂层3，扩展了能够形成外部端子7的区域，可以形成多个外部端子7。另外，在第1树脂层3的第1岸面14的部分上形成穿孔11，就可以连接第1配线部4a和第2配线部4b。
其后，在第1树脂层3的表面上形成第2配线部4b(图4(d))。该第2配线部4b，借助于穿孔11以与第1配线部4a连接的形态形成，并以从半导体元件2的中心10向外侧形成的方式进行。另外，第2配线部4b，例如也可以与第1配线部4a同样地形成，但是优选在钛·钨合金层和铜层上再实施镀铜。
而且，在第1树脂层3及第2配线部4b的表面上形成第2树脂层5(图4(e))。这时，在如上述那样的半导体元件2的最外侧的外周部和第2配线部4b的穿孔11侧的另一端上不形成第2树脂层5。第2配线部4b的穿孔11侧的另一端成为第2岸面15，形成外部端子7。该第2岸面15优选比第1岸面14形成更大。
而且，在第2岸面15的部分上形成由焊球构成的外部端子7(图4(f))。该外部端子7例如由无铅软钎料构成，通过焊球转印、糊印刷、镀等而形成。
然后，在第2树脂层5的表面上形成第3树脂层6(图5(g))。这时，第3树脂层6，以露出外部端子7的一部分的形态形成。另外，第3树脂层6也未必必须形成。
最后，通过切割切断已结束直至图4(f)或者图5(g)工序处理的硅晶片，完成各个半导体装置1。另外，上述的制造工序中，在作为半导体元件2的集合体的硅晶片的切割的部分上不形成第1树脂层3及第2树脂层5，由于不切断这些树脂层，所以可以防止半导体元件2的端部缺口和树脂层的剥离。
在本实施方式2中，由于多个配线4的一部分或全部由从与电极9连接的部分向着半导体元件2的中心10方向的第1配线部4a、和从半导体元件2的中心10方向向着外侧与外部端子7连接的第2配线部4b形成，所以配线4的纵断面形状成为コ字型，可以有效地缓和应力。另外，与第2配线部4b的外部端子7连接的部分在半导体元件2的中心侧出来，即使在半导体装置1发生应力的情况下，也可以防止第2配线部4b与外部端子7连接的部分发生断线。另外，由于在第1配线部4a和第2配线部4b之间形成第1树脂层3，所以可以进一步缓和配线4上产生的应力，也就可以与伴随大型芯片化的应力的增大相对应。
其它效果与实施方式1的半导体装置相同。
(实施方式3)
图6是表示本发明的实施方式3的电路基板的例的立体模式图。图6所示的电路基板100搭载了实施方式1所示的半导体装置1。电路基板100由玻璃环氧基板等构成，预先形成铜等的配线图形。通过在该电路基板100上连接半导体装置1的外部端子7，成为电导通的状态，可以进行希望的处理(例如数据处理)。
图7是表示本发明的实施方式3的电子机器例子的图。图7所示的电子机器具有实施方式1所示的半导体装置1。图7(a)是将半导体装置1适用于笔记本型个人电脑200的例子，图7(b)是将半导体装置1适用于移动电话机300的例子。另外，实施方式1所示的半导体装置1及实施方式2的制造方法所示的半导体装置1也可以使用于其它家电制品等中。

Claims (1)

1.一种半导体装置，包括：具有电极的半导体元件；与上述电极电连接的外部端子；与上述电极连接的第1配线；与上述外部端子连接的第2配线；在上述第1配线和上述第2配线之间形成的树脂层，
上述半导体装置中，
上述第2配线通过上述树脂层上形成的过孔与上述第1配线连接，
上述第1配线连接上述第2配线的部分，比上述电极更靠近上述半导体元件的中心，
上述第1配线连接上述第2配线的部分，比上述外部电极更靠近上述半导体元件的中心。
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EP1544913A2 (en) 2005-06-22
US20100019384A1 (en) 2010-01-28
US7982310B2 (en) 2011-07-19
US20110233742A1 (en) 2011-09-29
US20130264709A1 (en) 2013-10-10
KR100805503B1 (ko) 2008-02-20
KR20050061360A (ko) 2005-06-22
CN1630072A (zh) 2005-06-22
US20050133914A1 (en) 2005-06-23
EP2863424A1 (en) 2015-04-22
US9589886B2 (en) 2017-03-07
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JP3855992B2 (ja) 2006-12-13
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US8482121B2 (en) 2013-07-09
US7615864B2 (en) 2009-11-10
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US20080261352A1 (en) 2008-10-23
US20140361434A1 (en) 2014-12-11
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EP1544913A3 (en) 2011-11-09
CN101673718B (zh) 2011-10-05

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