CN101675518B - 芯片上功率引线球栅阵列封装 - Google Patents

芯片上功率引线球栅阵列封装 Download PDF

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Publication number
CN101675518B
CN101675518B CN2007800529278A CN200780052927A CN101675518B CN 101675518 B CN101675518 B CN 101675518B CN 2007800529278 A CN2007800529278 A CN 2007800529278A CN 200780052927 A CN200780052927 A CN 200780052927A CN 101675518 B CN101675518 B CN 101675518B
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lead frame
integrated circuit
power conductors
lead
electrically connected
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CN101675518A (zh
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P·约翰斯顿
K·海斯
李曙钟
J·米勒
图-安·特兰
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

形成了一种封装组件(30)，诸如球栅阵列封装，其通过使用置于集成电路管芯(52)上并且接合至BGA载体基板(42)中和内部管芯区域中形成的多个接合焊盘(45)的被包封的构图的引线框导体(59)，跨集成电路管芯(52)的内部区域分送功率，由此将该内部管芯区域电耦合至外部提供的参考电压。

Description

芯片上功率引线球栅阵列封装
技术领域
本发明通常涉及半导体装置的领域。在一个方面，本发明涉及电子元件封装。
背景技术
随着集成电路装置的密度和复杂度的增加以及该装置尺寸的缩小，在这些装置的设计和封装中出现了很多挑战。一个挑战是，随着电路复杂度的增加越来越多的功率和信号线必须电连接至集成电路管芯，但是随着装置尺寸的缩小存在越来越少的空间用于允许这些连接。另一个挑战是，用于将信号和功率电连接至集成电路管芯(die)的传统方法，诸如将芯片上引线(LOC)或者带式自动接合(TAB)引线框导体接合到管芯区域，完全不是用于连接现今装置所需数目的信号和功率线的可行解决方案，相比于管芯尺寸，该导体的尺寸是相对大的和不易使用的。这些传统方法还呈现出了在保护集成电路管芯免受结构或机械损坏方面的封装挑战，诸如当引线框导体延伸通过保护封装以与外部世界电接触时，由于湿气或其他环境暴露可能引起该损坏。
随着信号和功率线的数目的增加，电子行业已尝试通过使用导线接合(wirebond)连接技术增加管芯接触的密度，并且还已经采用了新型封装，诸如球栅阵列(ball grid array，BGA)、岸面栅格阵列(landgrid array，LGA)和针脚栅格阵列(pin grid array，PGA)封装，以提供改进的装置保护并且减小封装外形。然而，这些导线接合封装解决方案常常将功率不均匀地递送到整个管芯，这是因为如图1和2所示的，功率线被导线接合至排列在管芯22的有效(active)表面或正面表面23的所有侧边上的外围接合焊盘(bonding pad)。特别地，图1以简化的示意图的形式示出了传统的导线接合的BGA封装装置10的截面图，其中集成电路管芯22(具有背表面21和有效表面23)安装或附连至载体基板12并且装入绝缘封装体20内。使用焊料球安装层8将焊料球固着至载体基板12的下表面，该焊料球安装层8将每个焊料球物理附连并电连接至载体基板中的导电电路。在封装10中，第一参考电压(例如，VSS)被通过导电路径，诸如VSS/热焊料球阵列5和导电迹线16，提供到管芯22的背表面21。此外，第二参考电压(例如，VDD)被通过导电路径，诸如VDD焊料球3、导电迹线13、通孔(via)14、接触焊盘15和VDD导线接合导体24，提供到管芯22的有效表面23的外围边缘。最后，施加到信号焊料球1的信号信息2通过导电路径，诸如导线、接触焊盘或层、导电通孔、载体基板12中形成的导电迹线(未示出)、和信号导线接合导体26，电连接至管芯22的有效表面23的外围边缘。除了通过管芯22的背表面21的电连接之外，施加到VSS焊料球5的VSS信息6也通过导电路径，诸如导线、接触焊盘或层、导电通孔、载体基板12中形成的导电迹线、以及VSS导线接合导体(未示出)，电连接至管芯22的有效表面23的外围边缘。
VDD导线接合导体24被固着至管芯22外围处的接合焊盘，功率未被均匀地跨管芯22的有效表面23递送。这可以参考图2说明，图2示出了图1所示的封装装置10的简化平面图，其中在中心区域27和/或内部区域28处提供的功率或电压相比于在外围区域29处提供的功率或电压减小了。内部区域27、28中的电压降或功率下陷(power sag)是由以下事实导致的：在其中VDD导线接合导体24连接至管芯22的外围区域29中，电压是最强的。对于使用传统的导线接合封装的低功率装置而言，功率损失的问题可能是特别尖锐的。例如，对于5～8瓦范围中的产品，特定功率域的区域上的每个毫伏的电压下降可能导致性能和/或产率损失。对于位于距离封装级供给端子大于约2mm的区域中的高速CMOS数字逻辑(例如，高于600MHz)，该压降可能削弱其性能。尽管倒装封装可以提供出色的功率分布，但是其成本通常高于导线接合封装并且可能限制其应用空间。
因此，需要一种为具有多个信号和功率线的集成电路管芯提供改进的功率分布的阵列封装方案。此外，需要一种在不削弱装置性能或产率的情况下将信号和功率线电连接至集成电路管芯的成本有效的半导体装置封装。还需要改进的封装工艺和装置以克服现有技术中的诸如上文概述的问题。在参考下面的附图和具体实施方式阅读本申请的剩余内容之后，传统工艺和技术的另外的限制和缺陷对于本领域的技术人员将是显而易见的。
附图说明
在结合附图考虑下文的优选实施例的详细描述时，可以理解本发明及其众多的目的、特征和所获优点，在附图中：
图1以简化的示意图的形式示出了传统的导线接合的BGA封装装置的截面图；
图2示出了图1所示封装装置的简化平面图；
图3示出了其中单层引线框向跨管芯区域分布的管芯级接合焊盘提供功率的导线接合的BGA封装装置的截面图；
图4示出了图3所示封装装置的平面图；
图5示出了其中多层引线框中的第一层固着到载体基板的导线接合的BGA封装的截面图；
图6示出了图5所示封装装置的平面图；
图7示出了其中多层引线框中的第二层固着到载体基板以向跨管芯区域分布的管芯级接合焊盘提供功率的导线接合的BGA封装装置的截面图；并且
图8示出了图7所示封装装置的平面图。
将认识到，为了使说明简单和清楚，附图中示出的元件没有必要依比例绘制。例如，出于促进和提高清晰度和理解的目的，某些元件的尺寸被相对于其他元件放大。而且，在被视为适当的情况中，在附图中重复使用附图标记表示对应的或类似的元件。
具体实施方式
描述了一种用于将半导体管芯包封在封装中的方法和装置，其中包封的引线框结构被接合和连接至集成电路管芯，以便于将功率和/或接地分送到跨管芯区域分布的管芯级接合焊盘。除了改进跨管芯区域的功率分布之外，该包封的引线框结构还在管芯外围提供另外的接触区域用于导线接合的信号线。该引线框结构通过在载体基板中形成的导电路径(例如，焊料球、导电迹线、通孔、接触焊盘)电连接至片外功率和/或接地供应。此外，该引线框结构由一个或更多个构图的导体层形成，该导体层设置于集成电路管芯区域上以与集成电路管芯中的功率和/或接地供给端子电接触。为了跨管芯区域分送功率，该引线框结构被构图来限定具有近端的多个引线，其中在最终的封装组件中每个近端被安置或对准以用于到集成电路管芯中的对应的功率和/或接地供应端子的电连接。在多种实施例中，被构图的引线框结构通过跨管芯区域分布的短的、低外形(low profile)的鲁棒的(robust)引线接合，电连接至集成电路管芯的功率和/或接地栅格。在其他实施例中，该被构图的引线框结构的一个或更多个层通过导电管芯附连技术，诸如导电粘合剂、焊料、热压或热超声接合技术，电连接至集成电路管芯的功率和/或接地栅格。不论是否通过一个或更多个构图的导体层实现，该引线框结构都被安置为被完全包含在BGA基板边界内，使得没有引线框导电层延伸到产品元件外表面。通过使用该被构图的引线框结构跨管芯区域分送的功率和/或接地供给，可以使用传统导线接合技术将信号线电连接至集成电路管芯，从而增加封装中的信号线连接的密度。
现将参考附图详细描述本发明的多种说明性实施例。尽管在下文的描述中阐述了多种细节，但是将认识到，本发明可以在没有这些特定细节的情况下实践，并且对于此处描述的本发明可以做出许多针对特定实现方案的决定以实现装置的设计人员的将依实现方案的不同而变化的特定目标，诸如与工艺技术或设计相关约束的兼容性。尽管该开发努力可能是复杂的和耗时的，但是其将是受益于本公开内容的本领域的普通技术人员所采取的惯常程序。例如，参考封装的半导体装置的简化截面图示出了选定的方面，该截面图未依比例绘制并且不包括每个装置特征或几何尺寸以避免限制本发明或使本发明不清楚。还应注意，在本说明书通篇中，特定的封装组件(诸如构图的引线框结构和导线接合的导体)将被形成并组装用于制造封装的半导体装置。在下文未详细描述具体过程的情况下，可以使用用于形成和组装这些组件的对于本领域技术人员而言的传统技术。这些细节是公知的并且没有必要教授本领域的技术人员如何实现或使用本发明。
如此处解释的，被构图的引线框功率导体被安置并包封在导线接合的BGA封装装置内，以将功率和/或接地电压递送到跨集成电路管芯的有效表面分布的多个管芯级功率端子。这可以参考图3来图示说明，图3示出了导线接合的BGA封装组件30的截面图，该导线接合BGA封装组件30包括单层引线框功率导体59，其用于将功率分送到跨集成电路管芯52的有效表面分布的多个管芯级接合焊盘，该集成电路管芯52被安装或附连至载体基板42并且被装入绝缘封装体50中。集成电路管芯52可以通过使用粘合剂层、管芯附连环氧树脂或者本领域已知的其他管芯附连技术直接附连至载体基板42。
封装组件30包括载体基板42，其中形成在载体基板42的上表面和下表面之间延伸的一个或更多个通孔开口。如将认识到的，载体基板42可被形成为任何期望的形状和厚度，并且可以包括用于形成功能半导体封装的任何期望的特征。此外，载体基板42可由电绝缘材料(诸如有机聚合物树脂)的相对薄的柔性膜制造，或者由刚性的基本上平的构件制造，该构件可以由任何已知的适当材料制造，该材料包括但不限于：涂覆了绝缘体的硅、玻璃、陶瓷、环氧树脂、双马来酰亚胺-三嗪(BT)树脂、或者适于用作载体基板的本领域已知的任何其他材料。诸如通过使用焊料球安装层38，将多个外部导体或导电球(诸如导电焊料球)固着至载体基板42的下表面，该焊料球安装层38将每个焊料球物理附连并电连接至载体基板中的导电电路。每个导电电路由在载体基板42上和穿过载体基板42形成的封装岸面(landing)区域、通孔、迹线、和接触焊盘的导电图案形成，用于将(后继形成的)焊料球电连接至(后继附连的)集成电路管芯。例如，外部参考电压(例如，VSS)可以通过导电路径，诸如VSS/热焊料球35和导电通孔46，提供到管芯52的背表面51。如将认识到的，可以在载体基板42中形成一个或更多个内部导电层(未示出)，但是出于简化描述的目的，它们由单个通孔46表示。这些导电层可由任何导电材料形成，包括但不限于：导电掺杂多晶硅、导电金属或金属合金、导电的或填充了导体的弹性体、或者本领域技术人员已知的用于电连接的任何其他导电材料。最后，在载体基板的表面上形成的单独的电路线(例如，接触焊盘或封装岸面)通过选择性形成的电介质层相互电隔开。
在封装组件30中，集成电路管芯52具有背表面51和其中形成有效电路的有效表面53。信号信息32通过载体基板42中的导电路径(未示出)电连接到管芯52的有效表面53的外围边缘，该导电路径将信号焊料球31耦合至信号导线接合导体56，信号导线接合导体56又接合至排列在管芯52的正表面53的所有侧边上的外围接合焊盘。使用传统的导线接合技术允许将多个信号导线接合导体56附连到有效表面53，由此增加管芯52的信号线密度。
除了信号信息之外，还通过在载体基板42中形成的导电路径将功率提供给管芯52。为此，所示封装组件30包括单层引线框功率导体59，该单层引线框功率导体59跨管芯52的有效表面53延伸，并且用于向跨管芯52的有效表面53分布的多个接合焊盘提供功率。所示单层引线框功率导体59通过非导电粘合剂层58物理附连至管芯52，该非导电粘合剂层58可由热塑性聚(硅氧烷-酰亚胺)共聚物或者任何期望的粘合/接合材料形成。此外，单个引线框功率导体59通过多个短的低外形的鲁棒的导线接合54电连接至管芯52中的多个接合焊盘。为了支持该导线接合连接，引线框功率导体包括多个近端或接触区域(例如，图4中被示出为导线接合54所附连到的引线框功率导体59的部分)，该多个近端或接触区域终止于被配置用于至位于集成电路管芯52的正面上的多个接合焊盘的附连的接合端。该单层引线框功率导体59还使用用于实现电接触的任何期望的技术，诸如使用焊料、导电粘合剂、热压接合、热超声接合或导线接合，电和物理地连接至在载体基板42中形成的一个或更多个封装岸面45。封装岸面45又通过通孔44、导电迹线43和焊料球导体33电连接至外部功率源(例如，VDD)。功率供给焊料球导体33被示出为固着在一个或更多个位置34，然而可以使用任何期望的位置。
一旦引线框功率导体59、集成电路管芯52和导线接合导体附连至载体基板42，则可以形成包封层或材料50来密封并保护封装组件30内部的导电元件免受湿气、污染、腐蚀和机械冲击的影响，诸如通过施加、注入或者以另外方式形成保护层以密封开口区域。例如，可以使用任何期望的技术来在集成电路管芯52上形成转移模塑复合物(transfermolding compound)50以电隔离、物理保护以及以另外方式保护并封装管芯52。通过将引线框功率导体59安置在BGA基板42的区域内，引线框功率导体59可由绝缘封装体50完全包封，并由此被保护免受潜在的破坏性环境条件的影响。在所选择的实施例中，引线框功率导体59被安置成基本上在管芯52的区域内，由此使得功率导体59的任何部分都不会延伸通过封装体50的外表面。在该位置，借助于短的低外形的鲁棒的导线接合54将引线框功率导体59接合和连接至管芯52的有效表面53上的多个管芯级接触焊盘。
尽管在图3的截面外形中仅示出了单个引线框功率导体59，但是将认识到，在封装组件30中也可以包括另外的引线框功率导体。例如，通过形成具有包括一个或更多个开口区域的适当图案的单层引线框功率导体59，可以组装和附连一个或更多个另外的单层引线框功率导体以跨由该开口区域暴露的管芯表面53的部分延伸。通过这些另外的功率导体，可以通过利用导线接合连接器54将每个功率导体电连接至其对应的接合焊盘，将另外的功率电平提供给跨管芯52的有效表面53分布的管芯级接合焊盘。事实上，可以使用两个分立的引线框功率导体59、159来从封装岸面焊盘45提供第一功率电平(例如，VDD)，每个引线框功率导体被构图以覆盖管芯52的部分有效表面53(包括中心部分或内部区域)以及包括使管芯表面53的其他部分暴露的开口区域。
在第一引线框功率导体59、159所定义的开口区域中，可以使用两个分立的引线框功率导体55、155来从封装岸面焊盘47提供第二功率电平(例如，VSS)，每个引线框功率导体被构图以覆盖由引线框功率导体59、159暴露的管芯52的部分有效表面53。此外，每个引线框功率导体55、155经由导线接合连接器54电连接至管芯级接合焊盘。在图4所示封装组件30的平面图中，每个引线框功率导体55、59、155、159可以被形成为具有A形图案，该A形图案被安置为置于管芯表面53的中心或内部区域上，同时允许类似地安置用于另一引线框功率导体的空间。然而，可以使用任何期望的图案来提供管芯表面53上的引线框功率导体的互补的安置。该引线框功率导体的安置不仅改进了跨内部管芯区域的功率分布，而且还释放了处在集成电路管芯53的外围的另外的管芯级接触焊盘，由此可以使用传统的导线接合技术附连另外的信号线56。为了支持该导线接合连接，每个引线框功率导体55、59、155、159包括多个近端或接触区域，该多个近端或接触区域终止于被配置用于至位于集成电路管芯52的正面上的多个接合焊盘的附连的接合端(例如，图4中被示出为位于岸面焊盘45、47上的引线框功率导体部分)。如将认识到的，可以使用任何期望的组装技术将引线框功率导体55、59、155、159一起或顺序固着至载体基板42和电路管芯52。例如，可以首先将一个或更多个引线框功率导体固着至相应的封装岸面焊盘45、47，并且随后将其导线接合至位于集成电路管芯52的正面上的相应的多个接合焊盘，或者如果需要，可以反转该顺序。
尽管如上文所述的，可以用一个或更多个非重叠的导电层来实现引线框功率导体，但是将引线框功率导体实现为用于跨管芯区域分送功率和/或地的双层或多层引线框导体，仍可以获得功率分布优点。图5中示出了示例性实现方案，图5示出了在组装的中间阶段的导线接合的BGA封装组件60的截面图，其中集成电路92和多层引线框导体中的第一层76被固着至载体基板72。使用焊料球安装层68将多个焊料球61、63、65固着至载体基板72的下表面，该焊料球安装层68将每个焊料球物理附连和电连接至载体基板72中的导电电路。每个导电电路可由接触焊盘的导电图案、迹线、通孔和封装岸面区域形成，用于将(后继形成的)焊料球电连接至(后继附连的)集成电路管芯。例如，可以通过导电路径，诸如VSS/热焊料球65和导电通孔73，将外部参考电压(例如，VSS)提供到管芯92的背表面91。
为了向管芯92的有效表面93提供另外的或者替代的功率供给(例如，参考电压VSS)，封装组件60可以包括第一引线框功率导体76，该第一引线框功率导体76跨管芯92的有效表面93延伸并且接触跨管芯表面93分布的多个接合焊盘98。引线框功率导体76可以诸如通过选择性地刻蚀导电层、压印或丝网印刷引线框功率导体，由引线框样式块状金属(例如，铜、金、镀有银或金的铜、锡和/或铅等)的一个或更多个导电层形成，该块状金属以低成本提供低损耗的功率分布。使用对应的多个导电管芯附连粘合剂层99将所示出的第一引线框功率导体76物理和电地附连至多个管芯接合焊盘98。此外，使用用于实现电接触的任何期望的技术，诸如使用焊料、导电粘合剂、热压接合、热超声接合或导线接合，将第一引线框功率导体76电和物理地连接至载体基板72中形成的一个或更多个封装岸面75。封装岸面75又通过导电迹线74、通孔73和VSS/热焊料球65电连接至外部功率源(例如，VSS)。
尽管可以使用导电管芯附连技术将第一引线框功率导体76电连接至管芯92中的管芯级接合焊盘98，但是在第一引线框功率导体76上形成的任何另外的引线框功率导体层将典型地使用导线接合导体连接至其对应的管芯级接合焊盘。为此，第一引线框功率导体76可被形成有适当的图案，该图案包括一个或更多个开口区域，通过该开口区域可以实现另外的引线框功率导体与管芯级接触焊盘的导线接合连接。为了说明该构图的第一引线框功率导体76的示例，图6示出了图5所示的封装组件60的平面图。如所示出的，第一引线框功率导体76可被形成为单独导体线的交叉影线(cross-hatched)图案，这些导体线被安置为置于整体管芯表面93(特别包括中心或内部区域)上，同时提供用于使管芯表面93的外围和内部区域两者上的多个管芯级接触焊盘95暴露的开口。当然，可以使用任何期望的图案来使管芯表面93中的管芯级接触焊盘95暴露，只要第一引线框功率导体76中的开口允许堆叠在第一引线框功率导体76上的另外的引线框功率导体导线接合至所暴露的管芯级接触焊盘95。
不论使用什么图案，都将通过第一引线框功率导体76分送功率，其供给自封装岸面75(由于封装岸面75通过载体基板72连接至外部参考电压)。随着电流流过第一引线框功率导体76并且流向管芯表面93的内部区域中的电连接的管芯级接合焊盘98，电流被跨第一引线框功率导体76的单独的各导电元件分流。因此，自图6所示的左下的封装岸面75提供的电流101被分流到组成电流路径102中，每个组成电流路径102又被分流为组成电流路径103。然而，由于第一引线框功率导体76的单独的导电元件电连接至管芯级接合焊盘98，相比于其中功率线导线接合至位于管芯表面93外围的管芯级接合焊盘的传统方法，减小了跨管芯表面93的电压降。
图7和8中示出了堆叠的引线框功率导体的示例，图7和8分别示出了导线接合的BGA封装组件90的截面图和平面图，其中集成电路92、第一引线框功率导体76和第二引线框功率导体85固着至载体基板72并且被装入绝缘封装体100中。第二引线框功率导体85被安置在第一引线框功率导体76上面，并且通过电介质材料86与其隔开。替代地，第一和第二引线框功率导体可以被构造为双层复合结构，其具有层叠或形成在一起的电介质层和两个导电层，以便于将电介质层安置在两个导电层之间，由此这两个导电层用作两层引线框功率导体。当被安置为延伸跨整个管芯92时，第二引线框功率导体85可用于均匀地向管芯92上的所有管芯级接合焊盘95，包括中心或内部区域中的管芯级接合焊盘，提供另外功率(例如，参考电压VDD)。这可以通过将多个导线接合导体87连接在管芯级接合焊盘95和第二引线框功率导体85之间完成。第二引线框功率导体85又被使用用于实现电接触的任何期望的技术物理和电地连接至在载体基板72中形成的一个或更多个封装岸面84。封装岸面84又通过导电通孔和迹线81～83以及VDD焊料球63电连接至外部功率源(例如，VDD)。
为了说明如何将第二引线框功率导体85导线接合至管芯级接合焊盘95的示例，图8示出了图7所示封装组件90的平面图。如所示出的，第二引线框功率导体85被构图为单独的导体线的交叉影线图案，并且被安置为与第一引线框功率导体76重叠。通过该配置，第一和第二引线框功率导体76、85被安置为置于整体管芯表面93(特别包括中心或内部区域)上，同时提供用于使管芯表面93的外围和内部区域上的多个管芯级接触焊盘95暴露的开口。如将认识到的，第一和第二引线框功率导体76、85没有必要准确重叠，不过该重叠应允许定义使管芯级接触焊盘95暴露的清楚的开口，特别是在中心或内部区域中。通过这些开口，导线接合导体87被安置和附连以电连接接触焊盘95和第二引线框功率导体85。出于简化视觉呈现的目的，图8仅示出了一些导线接合导体87，但是将认识到，可以实现另外的导线接合连接以连接接触焊盘95和第二引线框功率导体85。
通过第二引线框功率导体85，来自封装岸面84的电流将流向管芯表面93的内部区域中的导线接合的管芯级接合焊盘95。随着电流的流动，电流被跨第二引线框功率导体85的单独的导电元件分流，由此自图8所示的左下的封装岸面84提供的电流201将被分流到组成电流路径202中，每个组成电流路径202又被分流为组成电流路径203。然而，由于第二引线框功率导体85的单独的导电元件电连接至管芯级接合焊盘95，相比于其中功率线导线接合至位于管芯表面93外围的管芯级接合焊盘的传统方法，减小了跨管芯表面93的电压降。
如将认识的，堆叠的引线框功率导体可以包括堆叠在第一和第二引线框功率导体上的另外的导电层，由此允许将另外的功率电平提供到管芯表面93的内部区域。无论使用了多少堆叠的引线框功率导体，此处定义的开口用于实现与管芯级焊盘的导线接合接触，由此可以自功率导体，而非使用外围的管芯接触焊盘，来跨管芯表面施加功率，以将功率施加到芯片的中心区域。此外，另外的功率导体层及其中形成的开口允许将另外的信号线导线接合至集成电路管芯92外围处的管芯级信号接合焊盘94。在所选择的实施例中，管芯表面的周界区域被预留用于管芯级信号接合焊盘94，信号导线接合被附连至该管芯级信号接合焊盘94。尽管图中没有示出，但是这允许管芯外的信号导线接合导体(例如，图4所示的导线56)附连至管芯92的周界区域中的管芯级信号接合焊盘94，达到它们未被内侧的(inboard)供应导线87替换的程度。
在示例性组装工序中，诸如通过使用管芯附连粘合剂层(未示出)或其他适当的管芯附连技术，将集成电路管芯92安置和固着至载体基板72。此外，诸如通过选择性刻蚀导电层、压印或丝网印刷引线框功率导体以形成多个开口，来由一个或更多个导电层形成第一引线框功率导体76。随着管芯92被固着，第一引线框功率导体76被安置和固着至载体基板72，由此第一引线框功率导体76的一个或更多个近端与在载体基板72中形成的对应的封装岸面焊盘75对准。可以使用用于实现电接触的任何期望的技术，诸如使用焊料、导电粘合剂、热压接合、热超声接合或导线接合，将第一引线框功率导体76电和物理地连接至封装岸面焊盘75。在这一点上，由于先前形成的与接合焊盘98对准的管芯附连粘合剂层99，第一引线框功率导体76还电和物理地连接至管芯级接合焊盘98。在第一引线框功率导体76顶部上，施加电介质层86，作为第一引线框功率导体76的一部分或者作为分立的电介质层。随着第一引线框功率导体76被固着，使用任何期望的电接触技术将第二引线框功率导体85安置和固着至载体基板72，由此第二引线框功率导体85的一个或更多个近端与在载体基板72中形成的对应的封装岸面焊盘84对准。在这一点上，第二引线框功率导体85还通过导线接合导体87电连接至管芯级接合焊盘95，该导线接合导体87延伸通过在第一和第二引线框功率导体中定义的开口。
到此为止应认识到，已提供了一种用于制作球栅阵列封装组件的方法。在该方法下，提供了一种球栅阵列载体基板，其具有在载体基板表面上形成的多个参考电压端子封装岸面焊盘和多个信号线封装岸面焊盘。此外，提供了一种集成电路管芯，其具有有效表面，该有效表面具有内部区域(管芯级参考电压供给端子位于其中)和外围区域(管芯级信号端子位于其中)。在该集成电路中，管芯级参考电压供给端子用于向电路提供参考电压(例如，接地、I/O VDD、VDD或VSS)。诸如通过将管芯附连粘合剂材料施加到部分载体基板表面并且随后将集成电路管芯附连至该管芯附连粘合剂材料，使得该集成电路管芯的有效表面与载体基板表面相反(即，背离)，来将该集成电路管芯附连至载体基板表面。在附连集成电路管芯之后，将第一引线框功率导体附连至至少两个参考电压端子封装岸面焊盘，由此该第一引线框功率导体电连接至参考电压端子封装岸面焊盘，并且被置于集成电路管芯的内部区域上。此外，诸如通过利用多个导线接合导体将管芯级参考电压供给端子导线接合至第一引线框功率导体，或者通过施加导电管芯附连粘合剂材料以将管芯级参考电压供给端子电连接至第一引线框功率导体，来将第一引线框功率导体电连接至集成电路管芯的内部区域中的多个管芯级参考电压供给端子。在所选择的实施例中，第二引线框功率导体固着至至少两个不同的参考电压端子封装岸面焊盘，由此该第二引线框功率导体电连接至不同的参考电压端子封装岸面焊盘并且置于集成电路管芯的内部区域上。可以通过将第二引线框功率导体堆叠在第一引线框功率导体上，或者通过将第二引线框功率导体固着在由第一引线框功率导体定义的开口区域中使得其与第一引线框功率导体不重叠，来固着第二引线框功率导体。以这样的方式，第一引线框功率导体可以电连接至第一参考电压并且第二引线框功率导体可以电连接至第二参考电压。所述多个信号线封装岸面焊盘也被导线接合至集成电路管芯上的多个管芯级信号端子。随后，包封集成电路管芯和引线框功率导体以完全封闭第一引线框功率导体。
在另一形式中，提供了用于封装半导体装置的球栅阵列封装组件。该封装包括具有第一表面的载体基板，在该第一表面中形成用于供给参考电压的多个导电接合焊盘。该封装还包括具有有效表面的集成电路，其中形成跨有效表面的内部区域分布的多个信号接合焊盘和多个参考电压接合焊盘。在固着时，集成电路的有效表面可以与载体基板的第一表面相反。此外，该封装包括构图的引线框导体，其置于集成电路的有效表面上并且电连接至(例如，接合至)所述多个参考电压接合焊盘和所述多个导电接合焊盘，由此将该集成电路电耦合至载体基板。在所选择的实施例中，该构图的引线框导体是通过两个构图的引线框导体实现的，其中第一构图的引线框导体置于集成电路的有效表面上并且电连接至(例如，接合至)第一多个参考电压接合焊盘和第一多个导电接合焊盘，并且其中第二构图的引线框导体置于集成电路的有效表面上并且电连接至(例如，接合至)第二多个参考电压接合焊盘和第二多个导电接合焊盘。如所公开的，第二构图的引线框导体可被安置为至少部分地与第一构图的引线框导体重叠，或者可被安置为与第一构图的引线框导体相邻使得第一和第二构图引线框导体之间不存在重叠。在其他实施例中，该构图的引线框导体被实现为两层复合结构，其具有形成在一起的电介质层和两个导电层，以便于将电介质层安置在两个导电层之间，由此每个导电层是构图的引线框导体。该球栅阵列封装还可以包括多个导线接合连接器，用于将载体基板的第一表面上形成的多个信号线封装岸面焊盘电连接至集成电路的有效表面上形成的所述多个信号接合焊盘。在最终组件中，该封装包括绝缘封装体，其固着至载体基板并且将构图的引线框导体和集成电路完全包封在该封装组件中。
在另一形式中，提供了一种具有集成电路的集成电路装置，该集成电路具有有效表面，其中形成有跨该有效表面的内部区域分布的多个参考电压接合焊盘。该集成电路装置包括用于安装和包封集成电路的封装结构，其中该封装结构包括包封的引线框导体，该封装引线框导体置于集成电路的有效表面上并且电连接至跨该有效表面的内部区域的所述多个参考电压接合焊盘。
尽管此处公开的所述示例性实施例涉及多种封装组件及其制造方法，但是本发明没有必要限于这些说明本发明的各创造性方面的示例性实施例，本发明广泛适用于多种封装工艺和/或装置。因此，上文公开的特定实施例仅是说明性的，并且不应被视为对本发明的限制，因为本发明可以通过对于受益于此处的教导的本领域的技术人员是显而易见的、不同的但是等效的方式修改和实践。因此，前面的描述并不意图将本发明限于所阐述的特定形式，恰恰相反地，其意图是涵盖可以被包括在如所附权利要求所限定的本发明的精神和范围内的替换、修改和等效方案，由此本领域的技术人员应理解他们可以以最广泛的形式进行多种改变、替换和变化而不偏离本发明的精神和范围。
上文已经针对特定实施例描述了益处、其他优点和对问题的解决方案。然而，这些益处、优点、对问题的解决方案以及可以使任何益处、优点或解决方案出现或变得更加显著的任何要素不应被解释为任何或所有权利要求的关键的、必需的或基本的特征或因素。如此处使用的，术语“包括”或其其他变体，意图涵盖非排他性的包括，由此包括一系列要素的工艺、方法、物品或装置并不是仅包括这些要素，而是可以包括未明确列出的或者对于该工艺、方法、物品或装置是固有的其他要素。

Claims (19)

1.一种用于制作封装组件的方法，包括：
提供载体基板，其具有在所述载体基板的第一表面上形成的多个参考电压端子封装岸面焊盘和多个信号线封装岸面焊盘；
将集成电路管芯附连至所述载体基板的所述第一表面，其中所述集成电路管芯包括有效表面，所述有效表面具有多个管芯级参考电压供给端子和多个管芯级信号端子；
将第一引线框功率导体固着至至少两个所述参考电压端子封装岸面焊盘，由此所述第一引线框功率导体电连接至所述参考电压端子封装岸面焊盘并且被置于所述集成电路管芯的内部区域上；
将所述第一引线框功率导体电连接至所述集成电路管芯的内部区域中的所述多个管芯级参考电压供给端子，
其中将所述第一引线框功率导体电连接至所述多个管芯级参考电压供给端子包括：在包封所述集成电路管芯之前，利用多个导线接合导体将所述多个管芯级参考电压供给端子导线接合至所述第一引线框功率导体；以及
包封所述集成电路管芯和第一引线框功率导体以完全封闭所述第一引线框功率导体。
2.如权利要求1所述的方法，其中将所述集成电路管芯附连至所述载体基板的第一表面包括：附连所述集成电路管芯使得所述集成电路管芯的所述有效表面背离所述载体基板的所述第一表面。
3.如权利要求1所述的方法，进一步包括：在包封所述集成电路管芯之前，将所述多个信号线封装岸面焊盘导线接合至所述集成电路管芯上的所述多个管芯级信号端子。
4.如权利要求1所述的方法，其中将所述第一引线框功率导体电连接至所述多个管芯级参考电压供给端子包括：在包封所述集成电路管芯之前，施加导电管芯附连粘合剂材料以将所述多个管芯级参考电压供给端子电连接到所述第一引线框功率导体。
5.如权利要求1所述的方法，进一步包括：将第二引线框功率导体固着至至少两个不同的参考电压端子封装岸面焊盘，由此使得所述第二引线框功率导体电连接至所述至少两个不同的参考电压端子封装岸面焊盘，并且被置于所述集成电路管芯的内部区域上。
6.如权利要求5所述的方法，其中所述第一引线框功率导体电连接至第一参考电压，而所述第二引线框功率导体电连接至第二参考电压。
7.如权利要求5所述的方法，其中固着所述第二引线框功率导体包括：将所述第二引线框功率导体堆叠在所述第一引线框功率导体上。
8.如权利要求5所述的方法，其中固着所述第二引线框功率导体包括：将所述第二引线框功率导体固着在由所述第一引线框功率导体定义的开口区域中。
9.如权利要求1所述的方法，其中电连接所述第一引线框功率导体包括：将所述第一引线框功率导体电连接至所述集成电路管芯的内部区域中的多个管芯级接地供给端子。
10.如权利要求1所述的方法，其中电连接所述第一引线框功率导体包括：将所述第一引线框功率导体电连接至所述集成电路管芯的内部区域中的多个管芯级VDD供给端子。
11.如权利要求1所述的方法，其中电连接所述第一引线框功率导体包括：将所述第一引线框功率导体电连接至所述集成电路管芯的内部区域中的多个管芯级VSS供给端子。
12.一种封装组件，包括：
载体基板，其包括第一表面和用于提供参考电压的位于所述第一表面的多个导电接合焊盘；
集成电路，其包括有效表面，所述有效表面具有跨所述有效表面分布的多个信号接合焊盘和多个参考电压接合焊盘；
构图的引线框导体，其置于所述集成电路的所述有效表面上，并且电连接至所述多个参考电压接合焊盘和所述多个导电接合焊盘，由此将所述集成电路电耦合至所述载体基板；
其中所述构图的引线框导体包括设置在所述集成电路的所述有效表面上的导电材料的导电结构，其从所述集成电路向外并向下朝向载体基板延伸，并且电连接到第一多个导电接合焊盘；
多个导线接合连接器，每一导线接合连接器电连接并附连到第一多个参考电压接合焊盘中的一个参考电压接合焊盘，且电连接并附连到所述构图的引线框导体的所述导电结构；和
绝缘封装体，其固着至所述载体基板，由此所述构图的引线框导体被完全包封在所述封装组件中。
13.如权利要求12所述的封装组件，其中所述构图的引线框导体包括：
第二构图的引线框导体，其置于所述集成电路的所述有效表面上，并且电连接至第二多个参考电压接合焊盘和第二多个导电接合焊盘。
14.如权利要求13所述的封装组件，其中所述第二构图的引线框导体被安置为至少部分地与所述导电结构重叠。
15.如权利要求13所述的封装组件，其中所述第二构图的引线框导体被安置为与所述导电结构相邻，由此在所述导电结构和所述第二构图的引线框导体之间不存在重叠。
16.如权利要求12所述的封装组件，其中所述构图的引线框导体包括两层复合结构，其具有一起形成的电介质层和两个导电层，以便于将所述电介质层安置在所述两个导电层之间，由此每个导电层是构图的引线框导体。
17.如权利要求12所述的封装组件，其中所述集成电路的所述有效表面与所述载体基板的所述第一表面相反。
18.如权利要求12所述的封装组件，进一步包括：
第二多个导线接合连接器，用于将所述载体基板的所述第一表面上形成的多个信号线封装岸面焊盘电连接至所述集成电路的所述有效表面上形成的所述多个信号接合焊盘。
19.一种集成电路装置，包括：
集成电路，其包括有效表面，其中形成有跨所述有效表面的内部区域分布的多个参考电压接合焊盘；和
封装结构，用于安装和包封所述集成电路，所述封装结构包括基板以及包封的引线框导体结构，所述包封的引线框导体结构置于所述集成电路的所述有效表面上，并且电连接至跨所述有效表面的内部区域的所述多个参考电压接合焊盘，所述引线框导体结构从所述集成电路向外并向下朝向所述基板延伸，并且电连接到所述基板的导电焊盘；
多个导线接合连接器，其电连接并附连到所述包封的引线框导体结构且电连接并附连到所述多个参考电压接合焊盘。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009147547A1 (en) * 2008-06-02 2009-12-10 Nxp B.V. Electronic device and method of manufacturing an electronic device
TWI447878B (zh) * 2009-08-28 2014-08-01 Great Team Backend Foundry Inc 增加通路及降低電阻之電晶體連接結構
US8426251B2 (en) * 2010-01-07 2013-04-23 Infineon Technologies Ag Semiconductor device
US8513784B2 (en) * 2010-03-18 2013-08-20 Alpha & Omega Semiconductor Incorporated Multi-layer lead frame package and method of fabrication
US8791582B2 (en) 2010-07-28 2014-07-29 Freescale Semiconductor, Inc. Integrated circuit package with voltage distributor
US9099340B2 (en) 2011-10-07 2015-08-04 Volterra Semiconductor Corporation Power management applications of interconnect substrates
US8674509B2 (en) * 2012-05-31 2014-03-18 Freescale Semiconductor, Inc. Integrated circuit die assembly with heat spreader
US8927345B2 (en) 2012-07-09 2015-01-06 Freescale Semiconductor, Inc. Device package with rigid interconnect structure connecting die and substrate and method thereof
US8643189B1 (en) 2012-07-17 2014-02-04 Freescale Semiconductor, Inc. Packaged semiconductor die with power rail pads
US9196598B1 (en) 2014-06-12 2015-11-24 Freescale Semiconductor, Inc. Semiconductor device having power distribution using bond wires
JP6566625B2 (ja) 2014-11-06 2019-08-28 キヤノン株式会社 電子部品、電子モジュール及びこれらの製造方法、電子機器
US11152326B2 (en) 2018-10-30 2021-10-19 Stmicroelectronics, Inc. Semiconductor die with multiple contact pads electrically coupled to a lead of a lead frame
US20230055211A1 (en) * 2021-08-19 2023-02-23 Texas Instruments Incorporated Electronic device multilevel package substrate for improved electromigration preformance

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2201545B (en) * 1987-01-30 1991-09-11 Tanaka Electronics Ind Method for connecting semiconductor material
US5235207A (en) * 1990-07-20 1993-08-10 Hitachi, Ltd. Semiconductor device
US5060052A (en) * 1990-09-04 1991-10-22 Motorola, Inc. TAB bonded semiconductor device having off-chip power and ground distribution
KR100276781B1 (ko) * 1992-02-03 2001-01-15 비센트 비. 인그라시아 리드-온-칩 반도체장치 및 그 제조방법
EP0594299A3 (en) 1992-09-18 1994-11-23 Texas Instruments Inc Multi-layer circuit grid unit and integrated circuit method.
EP0641019A3 (en) * 1993-08-27 1995-12-20 Poly Flex Circuits Inc Flexible lead frame printed on a polymer.
DE4430050A1 (de) 1994-08-24 1996-02-29 Siemens Ag Leadframe zur LOC-Montage im Innerleadbereich und/oder zur ungehäusten Montage eines Chips im Outerleadbereich
US5719748A (en) * 1995-06-28 1998-02-17 Honeywell Inc. Semiconductor package with a bridge for chip area connection
US5872403A (en) * 1997-01-02 1999-02-16 Lucent Technologies, Inc. Package for a power semiconductor die and power supply employing the same
JP3480291B2 (ja) * 1998-01-08 2003-12-15 日立電線株式会社 半導体装置及び電子装置
US6319755B1 (en) * 1999-12-01 2001-11-20 Amkor Technology, Inc. Conductive strap attachment process that allows electrical connector between an integrated circuit die and leadframe
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
DE10222660A1 (de) * 2002-05-22 2003-12-04 Linde Ag Verfahren und Vorrichtung zum Hochgeschwindigkeits-Flammspritzen
SG120879A1 (en) * 2002-08-08 2006-04-26 Micron Technology Inc Packaged microelectronic components
US6784525B2 (en) * 2002-10-29 2004-08-31 Micron Technology, Inc. Semiconductor component having multi layered leadframe
TWI376756B (en) 2003-07-30 2012-11-11 Taiwan Semiconductor Mfg Ground arch for wirebond ball grid arrays
US7256482B2 (en) 2004-08-12 2007-08-14 Texas Instruments Incorporated Integrated circuit chip packaging assembly
US7550318B2 (en) * 2006-08-11 2009-06-23 Freescale Semiconductor, Inc. Interconnect for improved die to substrate electrical coupling
DE102006060484B4 (de) * 2006-12-19 2012-03-08 Infineon Technologies Ag Halbleiterbauelement mit einem Halbleiterchip und Verfahren zur Herstellung desselben
US7829997B2 (en) * 2007-04-04 2010-11-09 Freescale Semiconductor, Inc. Interconnect for chip level power distribution

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US8129226B2 (en) 2012-03-06
CN101675518A (zh) 2010-03-17
WO2008139273A1 (en) 2008-11-20
US20100270663A1 (en) 2010-10-28
TWI520240B (zh) 2016-02-01

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