CN101685811A - 基于基片的未模制封装 - Google Patents
基于基片的未模制封装 Download PDFInfo
- Publication number
- CN101685811A CN101685811A CN200910174799A CN200910174799A CN101685811A CN 101685811 A CN101685811 A CN 101685811A CN 200910174799 A CN200910174799 A CN 200910174799A CN 200910174799 A CN200910174799 A CN 200910174799A CN 101685811 A CN101685811 A CN 101685811A
- Authority
- CN
- China
- Prior art keywords
- substrate
- lead
- semiconductor element
- lead frame
- frame structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 239000004065 semiconductor Substances 0.000 claims abstract description 138
- 239000000463 material Substances 0.000 claims description 60
- 238000000465 moulding Methods 0.000 claims description 56
- 238000000034 method Methods 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 11
- 230000003287 optical effect Effects 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000008393 encapsulating agent Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- 238000009434 installation Methods 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 claims 1
- 239000012778 molding material Substances 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical compound C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 235000010290 biphenyl Nutrition 0.000 description 1
- 239000004305 biphenyl Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920002994 synthetic fiber Polymers 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Abstract
本发明涉及一种基于基片的未模制封装,并揭示了一种半导体管芯封装。在一个实施例中,半导体管芯封装具有一基片。它包括(i)包含具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构以及(ii)模制材料。管芯附着表面和引线表面通过模制材料而暴露。半导体管芯位于管芯附着区域上,且半导体管芯电气耦合到引线。
Description
本发明专利申请是国际申请号为PCT/US2003/023864,国际申请日为2003-07-30,进入中国国家阶段的申请号为03820399.5,名称为“基于基片的未模制封装”的发明专利申请的分案申请。
发明背景
某些常规半导体管芯封装使用陶瓷基片。在一个实例中,陶瓷基片被金属化并具有导线和焊盘。半导体管芯安装于陶瓷基片上以形成半导体管芯封装。随后,将该半导体管芯封装安装于电路板上。
其它常规半导体封装使用引线框架。在一个实例中,半导体管芯用引线安装于引线框架上。线路将半导体管芯耦合到引线。线路、半导体管芯和随后多数引线框架(除了向外延伸的引线)随后被密封于模制化合物中。随后,使该模制化合物成形。所形成的半导体管芯封装接着被安装到电路板上。
虽然这种半导体封装是有用的,但可以进行改良。例如,使用陶瓷基片的半导体管芯封装制造成本相对较高。与许多聚合物材料相比,陶瓷材料较昂贵。此外,上述的两种类型的半导体管芯封装相对较厚。期望可以降低半导体管芯封装的厚度。随着消费电子产品(例如,蜂窝电话、膝上计算机等)继续减小尺寸,越发需要更薄的电子装置和更小的电子部件。
本发明的实施例单独和共同解决了上述问题和其它问题。
发明内容
本发明的实施例针对包括基片和半导体管芯的半导体封装以及形成其的方法。
本发明的一个实施例涉及半导体管芯封装,它包括(a)基片,它包括(i)包含具有管芯附着表面的管芯附着区域和具有引线表面(或者,其中诸如焊料球的其它互连方法可附着以形成“无引线封装”的区域)的引线的引线框架结构,以及(ii)模制材料,其中管芯附着表面和引线表面通过模制材料而暴露;以及(b)半导体管芯,它位于所述管芯附着区域上,其中半导体管芯电气耦合到引线。
本发明的另一个实施例涉及一种用于处理引线框架结构的方法,所述方法包括:(a)提供引线框架结构,它具有管芯附着表面和附着到带状结构上的引线表面,该管芯附着表面和栅极引线邻近于带状结构;(b)将模制材料沉积于与带状结构相对的引线框架结构的一侧上;(c)凝固模制材料;以及(d)从引线框架结构和凝固的模制材料上移除带状结构,从而暴露管芯附着表面和引线表面。
本发明的另一个实施例涉及一种用于形成半导体管芯封装的方法,包括:(a)形成一基片,它包括(i)包含具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构,以及(ii)模制材料,其中管芯附着表面和引线表面通过模制材料而暴露;以及(b)将半导体管芯安装于所述管芯附着区域上和管芯附着表面上,其中在安装后半导体管芯电气耦合到引线。
本发明的另一个实施例涉及一种用于形成用于半导体管芯封装的基片的方法,该方法包括:(a)提供包括具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构;以及(b)将模制材料模制于引线框架结构周围,其中管芯附着表面和引线表面通过模制材料暴露以形成基片。
以下将详细描述本发明的这些和其它实施例。
附图概述
图1示出了根据本发明实施例的基片的平面图。
图2示出了根据本发明实施例的半导体管芯封装的平面图。
图3示出了根据本发明实施例的基片的平面图。
图4示出了根据本发明实施例的半导体管芯封装的平面图。
图5(a)示出了沿图1的线5(a)-5(a)获得的根据本发明实施例的基片的剖视图。
图5(B)示出了根据本发明实施例的基片的剖视图。
图6示出了沿线6-6获得的图1基片的剖视图。
图7是沿线7-7获得的图2的半导体管芯封装的侧剖视图。
图8是根据本发明实施例的另一个半导体管芯封装的侧剖视图。
图9示出了附着到引线框架结构上的带状结构的侧剖视图,它将被置于模具中的模具腔内。
具体实施方式
图1示出了根据本发明实施例的基片40。基片40可以支持半导体管芯封装中的半导体管芯(未示出)。
基片40包括引线框架结构10和模制材料20。术语“引线框架结构”可表示由引线框架获得的结构。例如,可以通过蚀刻连续导电片以形成预定图案而形成引线框架。但是,如果使用模压,则引线框架初始就是通过系杆连接在一起的引线框架阵列中的许多引线框架之一。在制造半导体管芯封装的过程中,引线框架阵列会被切割以使引线框架与其它引线框架分开。作为该切割的结果,诸如源极引线和栅极引线的最终半导体管芯封装中的引线框架结构的一些部分会被电气地和机械地相互断开。因此,在本发明的实施例中,半导体管芯封装的引线框架结构会是连续的金属结构或者不连续的金属结构。
引线框架结构10包括管芯附着区域12。在该实例中,管芯附着区域12具有源极附着区域12(a)和栅极附着区域12(b)。当半导体管芯(未示出)位于管芯附着区域12上时,MOSFET(金属氧化物半导体场效应晶体管)的源极区和栅极区将分别耦合到源极附着区域12(a)和栅极附着区域12(b)。如果MOSFET是垂直MOSFET(以下详细描述),则MOSFET的漏极区将位于半导体管芯的相对侧。
为了说明目的,上述基片实施例具有相互隔离的源极附着区域和栅极附着区域。但是,在其它实施例中,基片可以包括漏极附着区域取代源极附着区域和栅极附着区域或者除它们之外还包括漏极附着区域。如果半导体管芯包括垂直MOSFET,则MOSFET的含漏极区的表面将耦合到并靠近基片,同时在半导体管芯的另一侧上的源极区和栅极区将远离基片。
在该实例中,基片40具有含相应源极引线表面的5个源极引线14(a)-14(e)以及含栅极引线表面的栅极引线18。隐线示出模制材料20下面的连接,其将五个源极引线14(a)-14(e)耦合到源极附着区域12(a)。隐线还示出耦合到栅极附着区域12(b)的栅极引线18。栅极附着区域12(b)和源极附着区域12(a)相互电绝缘。
引线框架结构10可以包括任何合适的材料,可以具有任何合适的形式,并可以具有任何合适的厚度。实例性的引线框架结构材料包括金属,诸如铜、铝、金等及其合金。引线框架结构还可以包括镀敷层,诸如金、铬、银、钯、镍等的镀敷层。引线框架结构10还可以具有任何合适的厚度,包括小于约1mm的厚度(例如,小于约0.5mm)。
最终安装于基片40上的半导体管芯可以包括任何合适的半导体器件。合适的器件包括垂直功率晶体管。垂直功率晶体管包括VDMOS晶体管。VDMOS晶体管是具有通过扩散形成的两个或更多半导体区域的MOSFET。它具有源极区、漏极区和栅极。器件是垂直的,其源极区和漏极区位于半导体管芯的相对表面处。栅极是沟槽栅极结构或者平面栅极结构,并形成于同源极区相同的表面处。沟槽栅极结构是优选的,因为沟槽栅极结构更窄并比平面栅极结构占据更少的空间。在操作期间,VDMOS期间中从源极区到漏极区的电流基本垂直于管芯表面。
模制材料20可以包括任何合适的材料。合适的模制材料包括联苯基材料,和多功能横向连接环氧树脂合成材料。如图1所示,引线14(a)-14(e),18没有侧向延伸向外延伸越过模制材料20,从而基片40可以被认为是“无引线”且包括该基片的封装可以被认为是“无引线”封装。
在某些实施例中,模制材料可以具有暗色(例如,黑色)。源极附着区域12(a)、源极引线14(a)-14(e)、栅极附着区域12(b)和栅极引线18可以包括具有与模制材料20的良好反差(contrast)的金属材料(例如,铜、铝)。良好反差使其更便于对准和沉积焊料或者将半导体管芯置于源极附着区域12、源极引线14(a)-14(e)、栅极附着区域12和栅极引线18。例如,改良的反差使机器更易于自动沉积焊料或自动拾取和放置半导体管芯于基片40上。这降低了形成有缺陷的半导体管芯封装的可能性。
如上所述,管芯附着区域12包括源极附着区域12(a)和栅极附着区域12(b)。在所形成的半导体管芯封装中,MOSFET的源极区和栅极区可以位于封装中半导体管芯的相同侧处。半导体管芯中的源极区和栅极区可分别耦合到源极附着区域12(a)和栅极附着区域12(b)。可使用焊料将半导体管芯电气耦合到源极附着区域12(a)和栅极附着区域12(b)。
如图1所示,栅极引线18的栅极引线表面和源极引线14(a)-14(e)的源极引线表面通过模制材料20暴露。同样,源极附着区域12(a)的表面和栅极附着区域12(b)的表面通过模制材料20暴露。在该实施例中,模制材料20的外表面以及源极附着区域12(a)、栅极附着区域12(b)、栅极引线18和源极引线14(a)-14(e)的暴露表面基本是共面的。
图2示出了使用图1所示的基片40的半导体管芯封装100。半导体管芯封装100包括管芯附着区域之上的半导体管芯50。焊料结构52(a)-52(e)(例如,焊料球)分别沉积于源极引线14(a)-14(e)上。另一个焊料结构56沉积于栅极引线18上。可以使用任何合适的工艺形成焊料结构52(a)-52(e)、56,包括丝网印刷、球附着、拾取和放置工艺等等。
在沉积焊料结构52(a)-52(e)、56和安装半导体管芯50于基片40上之后,半导体管芯封装100可以被翻转,随后安装到电路板上。
图3和4分别示出根据本发明另一个实施例的基片和半导体管芯封装。在图1到4中,相同的标号表示相同的元件。图3和4中的实施例类似于图1和2中的元件,除了在图3和4所示的实施例中,存在更少的源极引线和相应焊料结构。与图1和2中的实施例相比,图3和4中基片和半导体管芯封装的面积更小。如通过图1-4的不同实施例所示,本发明的实施例可以具有任何合适数量的源极引线和漏极引线。
图5(a)示出了沿图1所示的线5(a)-5(a)获得的基片40的剖视图。
图5(a)示出一基片,其中源极附着区域12(a)的相对主表面通过模制材料20暴露。在该实施例中,模制材料20的厚度可基本等于引线框架结构的厚度。引线框架结构的上表面和下表面的一些部分可通过模制材料20暴露。
图5(b)示出本发明的又一个实施例。在图5(b)中,示出了管芯附着区域的源极附着区域12(a),且模制材料20暴露源极附着区域12(a)。与图5(a)所示的实施例不同的是,模制材料20覆盖引线框架结构的侧表面和下表面。
图5(a)所示的基片实施例比图5(b)所示的基片实施例更薄。例如,如果所形成的半导体管芯封装要用于较薄的装置中,诸如无线电话或膝上计算机,则这是期望的。
图6示出沿线6-6获得的图1所示基片40的侧视图。如图所示,引线框架10包括源极附着区域12(a)和两个源极引线14(a),14(c)。模制材料20设置于引线框架10中的凹槽中。凹槽中的模制材料20可以帮助选择性地暴露源极引线14(a),14(b)。
图7示出了沿线7-7获得的图2所示的半导体管芯封装100的侧剖视图。半导体管芯封装100包括通过焊料层48安装于引线框架结构10的源极附着区域12(a)和栅极附着区域12(b)上的半导体管芯50。该实施例中的焊料层48是不连续的,从而管芯50中的栅极和源极区不短路。焊料球52(e),56分别位于源极引线14(e)和栅极引线18上。模制材料20位于焊料球52(e),56和半导体管芯50之间的引线框架结构10中的凹槽中。模制材料20也位于源极附着区域12(a)和栅极附着区域12(b)之间以电气绝缘传递到半导体管芯50的栅极电流和源极电流。
图8示出根据本发明的另一个实施例的半导体管芯封装100。半导体管芯封装100包括基片40上的半导体管芯50。半导体管芯50可包括半导体管芯50的上表面处的源极区和栅极区,和其下表面处的漏极区。线路62例如可以耦合半导体管芯50中的源极区和源极引线60。另一线路(未示出)可耦合半导体管芯50的栅极区到栅极引线(未示出)。
密封材料66覆盖半导体管芯50和线路62以包含这些部件。在某些实施例中,密封材料66可以同模制材料20不同。可使用任何合适的密封材料。合适的密封材料包括联苯材料,以及多功能横向连接的环氧树脂合成物。
基片40包括引线框架12,它具有邻近于半导体管芯50的第一表面12-1和远离半导体管芯50的第二表面12-2。第一表面12-1的面积大于第二表面12-2的面积。通过减小第二表面的大小,封装100可以安装于电路板上的合适尺寸的导电焊盘上。
任何合适的工艺可形成减小面积的第二表面12-2。例如,光刻工艺可用于将光阻材料图案印制于诸如引线框架的金属结构上。随后,可以将合适的蚀刻剂用于蚀刻金属材料到合适深度,以形成引线框架结构的减小面积的第二表面12-2。光刻法和蚀刻工艺是本技术领域内已知的。
与之前的实施例不同,图8所示的半导体管芯封装100可安装于电路板上而不颠倒。这样,当半导体管芯封装100安装于电路板上时,表面12-2比表面12-1更靠近电路板。
根据本发明实施例的基片可用于纯粹电子器件之外的装置中。例如,本发明的实施例可用于光耦合器封装中。光耦合器封装包含至少一个光发射器装置,它通过光传输介质光耦合到光接收器装置。光发射器装置和光接收器装置可位于基片上(类似于上述的一些)。该设置允许信息从包含光发射器装置的一个电路传递到包含光接收器装置的另一个电路。在这两个电路之间维持高度电气绝缘。因为信息越过绝缘间隙而被光传播,所以该传送是单向的。例如,光接收器装置不能更改包含光发射器装置的电路的操作。该特点是有用的,因为例如发射器可以使用微处理器或逻辑门电路由低电压电路驱动,而输出光接收器装置可以是高电压DC或AC负载电路的一部分。光隔离还可以防止由相对对立的输出电路引起的对输入电路的损坏。合适的光耦合器装置的实例描述于美国专利申请No.09/944717,其提交于2001年8月31日,并被转让给本申请的相同受让人。该美国专利申请结合在此整体作为参考。
图9示出了本发明的实施例中如何可以形成基片。在该实施例中,引线框架结构10(单独按引线框架的形式或者具有阵列中的其它引线框架)被粘着到带状结构18的粘合侧。随后,将该组合置于模具12的模具腔104中。模制化合物(以液体或半液体形式)随后被引入引线框架结构10之下的模制腔,如由标号96所表示的,且模制化合物向上通过并填充引线框架结构10中的缝隙25。一旦模化合物凝固,就可将带状结构38、引线框架10和模制化合物从模具12上移除。如果要形成如图5(a)中所示的基片,就可以在其凝固之前或之后从与带状结构38相对的引线框架结构10的侧部移除多余的模制化合物。接着,带状结构38可与所形成的基片分开。与带状结构38接触的金属表面通过凝固的模制化合物暴露。该过程可以是“带辅助单侧模制工艺”的实例。
在另一个实施例中,代替使用模具,可以将模制材料丝网印刷入引线框架结构的缝隙中。例如,可以将引线框架结构置于表面(或带)上。可使用橡皮刮板或其它装置扩展模制材料进入引线框架结构的缝隙中。随后,如期望,可除去多余的模制化合物(例如,使用橡皮刮板)。模制材料可凝固且引线框架结构可与表面分开。之前与表面接触的引线框架结构的一些部分将没有模制材料并因此将通过凝固的模制材料暴露。此外,可进行去废料(dejunk)和去毛刺(deflash)工艺(本技术领域内已知)以除去多余的模制化合物。
在形成基片后,用于形成半导体封装的其余步骤可包括诸如焊料分配、焊料球附着、倒装芯片管芯附着,随后回流焊料球的步骤,从而可以将半导体管芯附着到基片上。
在将半导体管芯安装到引线框架之前或之后,可部分切割引线框架结构以隔离引线用于测试。例如,参考图1,源极引线14(1)-14(e)和栅极引线18可以是引线框架阵列内的单个引线框架结构10的一部分。最初,引线框架结构10可通过外框架状元件经由从每个引线14(a)-14(e),18向外延伸的“系杆”(未示出)机械地耦合在一起。在形成基片后,连到栅极引线18的系杆(未示出)可以被切割以使栅极引线18与元件引线14(a)-14(e)隔离。随后,在将其与其它基片分离之前电气测试该基片。
如果基片通过测试,则半导体管芯封装阵列中的半导体管芯封装可按单数(singulation)工艺(例如,使用锯)相互分开。随后,本技术领域内已知的带和卷轴工艺可紧接着该单数工艺。有利地,在本发明的实施例中,不需要修整和形成模制的成形系数(form factor)专用工具。
本发明的实施例具有大量其它优点。首先,如上所述,在本发明的实施例中,在基片中使用引线框架结构。引线框架结构是廉价且便于制造的。因此,根据本发明的实施例的基片可以更廉价地制成。例如,与陶瓷金属化基片相比,根据本发明实施例制成的基片的成本可以降低约70%或以上。其次,根据本发明实施例的基片具有模制材料和引线框架的暴露区域之间的高反差。如以上进一步说明的,这导致更少的缺陷。第三,本发明的实施例可制成得比常规半导体管芯封装和基片更薄。相比现有技术的封装的当前状态,本发明实施例的封装尺寸可降低至少20%。例如,根据本发明实施例的半导体管芯封装的厚度可以在约0.5mm(或更小)的数量级上。第四,在本发明的实施例中,模制过程是与成形系数无关的,因为它用于构建基片,且不需要用于完全密封半导体管芯。第五,可以使用已知的“倒装芯片”技术安装本发明实施例的基片和封装。第六,在本发明的实施例中,可以在引线框架结构中蚀刻精细的几何形状,从而封装引线和管芯附着表面可按需要而定制。第七,根据本发明实施例的基片是机械刚性的,但仍足够柔性以便在高度自动化的设备中运用。
此外,在本发明的实施例中,可以预先模制引线框架以形成基片,随后(用管芯)封装该基片以形成封装。有利地,可以蚀刻或印制非常薄的引线框架。例如,可以采用约4密耳厚的铜箔,将其冲压或蚀刻为所需图案,随后将其模制入约6到8密耳厚的基片。现在,可在常规装配设备(例如,倒装芯片接合器)中方便地运用所形成的基片。与常规镀敷工艺相比,本发明的实施例减少了处理时间并提升了制造的方便性。例如,铜按约4-8微米/分钟的速度镀敷。为了获得4密耳厚的铜轨迹一般将花费30到40分钟。本发明的实施例花费更少的时间来制造,因为预先形成的引线框架可用于形成基片。
这里所采用的术语和表达用于描述而非限制性的,且这种术语和表达的使用不旨在排出所示和描述的等效物或其部分,可以理解,各种修改都落在所要求的本发明的范围之内。此外,本发明的任何实施例的任一个或多个特点可以与本发明的任何其它实施例的任一个或多个其它特点组合,而不背离本发明的范围。例如,可以理解,图5(b)所示的类型的基片可用于图2和4所示的半导体管芯封装中。
Claims (36)
1.一种半导体管芯封装,其特征在于,包括:
(a)基片,它包括(i)包含具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构,以及(ii)模制材料,其中管芯附着表面和引线表面通过模制材料而暴露;以及
(b)半导体管芯,它位于所述管芯附着区域上,
其中半导体管芯电气耦合到引线,并且半导体管芯电气耦合到管芯附着区域。
2.如权利要求1所述的半导体管芯封装,其特征在于,模制材料的厚度等于引线框架结构的厚度。
3.如权利要求1所述的半导体管芯封装,其特征在于,半导体管芯包括垂直MOSFET,它具有半导体管芯的一侧处的源极区和栅极区以及半导体管芯的另一侧处的漏极区。
4.如权利要求1所述的半导体管芯封装,其特征在于,半导体管芯包括垂直MOSFET,它具有半导体管芯的一侧处的源极区和栅极区以及半导体管芯的另一侧处的漏极区,其中源极区和栅极区邻近于基片而漏极区远离基片。
5.如权利要求1所述的半导体管芯封装,其特征在于,引线是源极引线且引线表面是源极引线表面,其中引线框架结构还包括具有栅极引线表面的栅极引线,该栅极引线表面通过模制材料而暴露。
6.如权利要求5所述的半导体管芯封装,其特征在于,进一步包括栅极和源极引线上的焊料结构。
7.如权利要求5所述的半导体管芯封装,其特征在于,其中半导体管芯包括垂直MOSFET,它具有半导体管芯的一侧处的源极区和栅极区以及半导体管芯的另一侧处的漏极区,其中源极区电气耦合到源极引线,栅极区电气耦合到栅极引线。
8.如权利要求7所述的半导体管芯封装,其特征在于,其中模制化合物的厚度等于引线框架结构的厚度。
9.如权利要求1所述的半导体管芯封装,其特征在于,管芯附着表面的面积大于与管芯附着表面相对的引线框架结构表面的面积。
10.一种用于形成半导体管芯封装的方法,其特征在于,包括:
(a)形成一基片,它包括(i)包含具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构,以及(ii)模制材料,其中管芯附着表面和引线表面通过模制材料而暴露;以及
(b)将半导体管芯安装于所述管芯附着区域的管芯附着表面上,其中在安装后半导体管芯电气耦合到管芯附着表面和引线。
11.如权利要求10所述的方法,其特征在于,半导体管芯包括垂直功率MOSFET。
12.一种用于形成用于半导体管芯封装的基片的方法,其特征在于,该方法包括:
(a)提供包括具有管芯附着表面的管芯附着区域和具有引线表面的引线的引线框架结构;以及
(b)将模制材料模制于引线框架结构周围,其中管芯附着表面和引线表面通过模制材料暴露以形成基片,其中模制材料的外表面与引线表面共面,其中包括外表面和引线表面的衬底的主表面平坦且自衬底的一边延伸到衬底的相对一边。
13.如权利要求12所述的方法,其特征在于,提供引线框架结构包括冲压或蚀刻一片导电材料以形成引线框架结构。
14.一种用于半导体管芯封装的衬底,该衬底包括:
引线框架结构,其具有多个具有引线表面的引线;和
位于引线框架结构上的模制材料,其中模制材料的外表面与引线表面共面,其中包括外表面和引线表面的衬底的主表面平坦且自衬底的一边延伸到衬底的相对一边。
15.如权利要求14所述的衬底,其特征在于,所述主表面占据了衬底的整个一侧。
16.如权利要求14所述的衬底,其特征在于,所述衬底由模制材料和引线框架结构所构成。
17.如权利要求14所述的衬底,其特征在于,所述模制材料的厚度等于引线框架结构的厚度。
18.如权利要求14所述的衬底,其特征在于,所述引线框架结构包括覆盖了金属的结构。
19.如权利要求14所述的衬底,其特征在于,所述引线框架结构还包括管芯接触区域,其中引线由该管芯接触区域延伸出来。
20.如权利要求14所述的衬底,其特征在于,所述引线框架结构包括凹槽,并且所述模制材料充填在凹槽中。
21.一种半导体管芯封装,包括:
如权利要求14所述的衬底;和
在衬底上的半导体管芯。
22.如权利要求21所述的半导体管芯封装,其特征在于所述半导体管芯包括垂直晶体管。
23.如权利要求21所述的半导体管芯封装,其特征在于,所述半导体管芯包括功率MOSFET。
24.一种半导体管芯封装,包括:
衬底,其包括具有含引线表面的多个引线的引线框架结构,和在引线框架结构上的模制材料,其中模制材料的外表面与引线表面共面,且至少部分地形成所述衬底的平坦表面;
在衬底上的半导体管芯;和
覆盖半导体管芯的密封材料。
25.如权利要求24所述的半导体管芯封装,其特征在于,密封材料完全地覆盖半导体管芯并与之接触。
26.如权利要求24所述的半导体管芯封装,其特征在于,所述半导体管芯包括垂直晶体管。
27.如权利要求24所述的半导体管芯封装,其特征在于,还包括将半导体管芯连接到衬底的导线。
28.如权利要求24所述的半导体管芯封装,其特征在于,所述半导体管芯包括功率MOSFET。
29.如权利要求24所述的半导体管芯封装,其特征在于,所述模制材料的厚度与所述引线框架结构的厚度相同。
30.如权利要求24所述的半导体管芯封装,其特征在于,所述引线框架结构具有第一表面,其形成管芯附着表面,和第二表面,其与第一表面相对向。
31.如权利要求30所述的半导体管芯封装,其特征在于,第一表面的面积比第二表面要大。
32.如权利要求24所述的半导体管芯封装,其特征在于,所述引线框架结构包括铜。
33.一种形成半导体管芯封装的方法,包括:
形成包括引线框架结构的衬底,所述结构包括具有引线表面的引线,模制材料,平坦的第一和第二侧,其中所述引线表面通过模制材料而暴露出来;和
将半导体管芯固定到所述第一侧上,其中所述半导体管芯在固定之后电气连接到所述引线上。
34.如权利要求33所述的方法,其特征在于,所述半导体管芯包括垂直功率MOSFET。
35.如权利要求33所述的方法,其特征在于,所述半导体管芯包括光学装置。
36.如权利要求33所述的方法,还包括将导线附着到半导体管芯和衬底上。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/233,248 US7061077B2 (en) | 2002-08-30 | 2002-08-30 | Substrate based unmolded package including lead frame structure and semiconductor die |
US10/233,248 | 2002-08-30 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN038203995A Division CN1679162B (zh) | 2002-08-30 | 2003-07-30 | 基于基片的未模制封装及形成该封装的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101685811A true CN101685811A (zh) | 2010-03-31 |
CN101685811B CN101685811B (zh) | 2012-12-05 |
Family
ID=31977195
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2009101747995A Expired - Fee Related CN101685811B (zh) | 2002-08-30 | 2003-07-30 | 基于基片的未模制封装 |
CN038203995A Expired - Fee Related CN1679162B (zh) | 2002-08-30 | 2003-07-30 | 基于基片的未模制封装及形成该封装的方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN038203995A Expired - Fee Related CN1679162B (zh) | 2002-08-30 | 2003-07-30 | 基于基片的未模制封装及形成该封装的方法 |
Country Status (9)
Country | Link |
---|---|
US (6) | US7061077B2 (zh) |
JP (2) | JP4634146B2 (zh) |
KR (1) | KR101037997B1 (zh) |
CN (2) | CN101685811B (zh) |
AU (1) | AU2003257046A1 (zh) |
DE (1) | DE10393164T5 (zh) |
MY (1) | MY149851A (zh) |
TW (2) | TWI267176B (zh) |
WO (1) | WO2004021400A2 (zh) |
Families Citing this family (72)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6753605B2 (en) | 2000-12-04 | 2004-06-22 | Fairchild Semiconductor Corporation | Passivation scheme for bumped wafers |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
US7061077B2 (en) * | 2002-08-30 | 2006-06-13 | Fairchild Semiconductor Corporation | Substrate based unmolded package including lead frame structure and semiconductor die |
US7217594B2 (en) | 2003-02-11 | 2007-05-15 | Fairchild Semiconductor Corporation | Alternative flip chip in leaded molded package design and method for manufacture |
US20060003483A1 (en) * | 2003-07-07 | 2006-01-05 | Wolff Larry L | Optoelectronic packaging with embedded window |
US6919625B2 (en) | 2003-07-10 | 2005-07-19 | General Semiconductor, Inc. | Surface mount multichip devices |
TWI254437B (en) * | 2003-12-31 | 2006-05-01 | Advanced Semiconductor Eng | Leadless package |
US7196313B2 (en) * | 2004-04-02 | 2007-03-27 | Fairchild Semiconductor Corporation | Surface mount multi-channel optocoupler |
US7256479B2 (en) * | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
JP2006210777A (ja) * | 2005-01-31 | 2006-08-10 | Nec Electronics Corp | 半導体装置 |
US7226821B2 (en) * | 2005-06-24 | 2007-06-05 | Cardiac Pacemakers, Inc. | Flip chip die assembly using thin flexible substrates |
CN101213663B (zh) | 2005-06-30 | 2010-05-19 | 费查尔德半导体有限公司 | 半导体管芯封装及其制作方法 |
US7285849B2 (en) * | 2005-11-18 | 2007-10-23 | Fairchild Semiconductor Corporation | Semiconductor die package using leadframe and clip and method of manufacturing |
US20090057852A1 (en) * | 2007-08-27 | 2009-03-05 | Madrid Ruben P | Thermally enhanced thin semiconductor package |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
US20070164428A1 (en) * | 2006-01-18 | 2007-07-19 | Alan Elbanhawy | High power module with open frame package |
US7868432B2 (en) * | 2006-02-13 | 2011-01-11 | Fairchild Semiconductor Corporation | Multi-chip module for battery power control |
US7768075B2 (en) * | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
US7618896B2 (en) * | 2006-04-24 | 2009-11-17 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple dies and a common node structure |
US7656024B2 (en) | 2006-06-30 | 2010-02-02 | Fairchild Semiconductor Corporation | Chip module for complete power train |
US7564124B2 (en) | 2006-08-29 | 2009-07-21 | Fairchild Semiconductor Corporation | Semiconductor die package including stacked dice and heat sink structures |
US7927923B2 (en) | 2006-09-25 | 2011-04-19 | Micron Technology, Inc. | Method and apparatus for directing molding compound flow and resulting semiconductor device packages |
US8106501B2 (en) | 2008-12-12 | 2012-01-31 | Fairchild Semiconductor Corporation | Semiconductor die package including low stress configuration |
US7768105B2 (en) * | 2007-01-24 | 2010-08-03 | Fairchild Semiconductor Corporation | Pre-molded clip structure |
US7821116B2 (en) * | 2007-02-05 | 2010-10-26 | Fairchild Semiconductor Corporation | Semiconductor die package including leadframe with die attach pad with folded edge |
US8159828B2 (en) * | 2007-02-23 | 2012-04-17 | Alpha & Omega Semiconductor, Inc. | Low profile flip chip power module and method of making |
KR101391925B1 (ko) * | 2007-02-28 | 2014-05-07 | 페어차일드코리아반도체 주식회사 | 반도체 패키지 및 이를 제조하기 위한 반도체 패키지 금형 |
KR101489325B1 (ko) | 2007-03-12 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법 |
US7659531B2 (en) * | 2007-04-13 | 2010-02-09 | Fairchild Semiconductor Corporation | Optical coupler package |
US7683463B2 (en) * | 2007-04-19 | 2010-03-23 | Fairchild Semiconductor Corporation | Etched leadframe structure including recesses |
US7902657B2 (en) * | 2007-08-28 | 2011-03-08 | Fairchild Semiconductor Corporation | Self locking and aligning clip structure for semiconductor die package |
US7737548B2 (en) | 2007-08-29 | 2010-06-15 | Fairchild Semiconductor Corporation | Semiconductor die package including heat sinks |
US20090057855A1 (en) * | 2007-08-30 | 2009-03-05 | Maria Clemens Quinones | Semiconductor die package including stand off structures |
US7768123B2 (en) * | 2007-09-26 | 2010-08-03 | Fairchild Semiconductor Corporation | Stacked dual-die packages, methods of making, and systems incorporating said packages |
US7727813B2 (en) | 2007-11-26 | 2010-06-01 | Infineon Technologies Ag | Method for making a device including placing a semiconductor chip on a substrate |
US20090140266A1 (en) * | 2007-11-30 | 2009-06-04 | Yong Liu | Package including oriented devices |
US7589338B2 (en) * | 2007-11-30 | 2009-09-15 | Fairchild Semiconductor Corporation | Semiconductor die packages suitable for optoelectronic applications having clip attach structures for angled mounting of dice |
KR20090062612A (ko) * | 2007-12-13 | 2009-06-17 | 페어차일드코리아반도체 주식회사 | 멀티 칩 패키지 |
US7781872B2 (en) * | 2007-12-19 | 2010-08-24 | Fairchild Semiconductor Corporation | Package with multiple dies |
US7791084B2 (en) | 2008-01-09 | 2010-09-07 | Fairchild Semiconductor Corporation | Package with overlapping devices |
US8106406B2 (en) * | 2008-01-09 | 2012-01-31 | Fairchild Semiconductor Corporation | Die package including substrate with molded device |
US7626249B2 (en) * | 2008-01-10 | 2009-12-01 | Fairchild Semiconductor Corporation | Flex clip connector for semiconductor device |
KR101463074B1 (ko) * | 2008-01-10 | 2014-11-21 | 페어차일드코리아반도체 주식회사 | 리드리스 패키지 |
US20090194857A1 (en) * | 2008-02-01 | 2009-08-06 | Yong Liu | Thin Compact Semiconductor Die Packages Suitable for Smart-Power Modules, Methods of Making the Same, and Systems Using the Same |
US20090194856A1 (en) * | 2008-02-06 | 2009-08-06 | Gomez Jocel P | Molded package assembly |
KR101524545B1 (ko) * | 2008-02-28 | 2015-06-01 | 페어차일드코리아반도체 주식회사 | 전력 소자 패키지 및 그 제조 방법 |
US7768108B2 (en) * | 2008-03-12 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die package including embedded flip chip |
US8018054B2 (en) * | 2008-03-12 | 2011-09-13 | Fairchild Semiconductor Corporation | Semiconductor die package including multiple semiconductor dice |
US7893548B2 (en) * | 2008-03-24 | 2011-02-22 | Fairchild Semiconductor Corporation | SiP substrate |
KR101519062B1 (ko) * | 2008-03-31 | 2015-05-11 | 페어차일드코리아반도체 주식회사 | 반도체 소자 패키지 |
US7935575B2 (en) * | 2008-04-07 | 2011-05-03 | Semiconductor Components Industries, Llc | Method of forming a semiconductor package and structure therefor |
US20090278241A1 (en) * | 2008-05-08 | 2009-11-12 | Yong Liu | Semiconductor die package including die stacked on premolded substrate including die |
US7855439B2 (en) * | 2008-08-28 | 2010-12-21 | Fairchild Semiconductor Corporation | Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same |
US7829988B2 (en) * | 2008-09-22 | 2010-11-09 | Fairchild Semiconductor Corporation | Stacking quad pre-molded component packages, systems using the same, and methods of making the same |
US8314499B2 (en) * | 2008-11-14 | 2012-11-20 | Fairchild Semiconductor Corporation | Flexible and stackable semiconductor die packages having thin patterned conductive layers |
US8193618B2 (en) | 2008-12-12 | 2012-06-05 | Fairchild Semiconductor Corporation | Semiconductor die package with clip interconnection |
US7816784B2 (en) | 2008-12-17 | 2010-10-19 | Fairchild Semiconductor Corporation | Power quad flat no-lead semiconductor die packages with isolated heat sink for high-voltage, high-power applications, systems using the same, and methods of making the same |
US7973393B2 (en) | 2009-02-04 | 2011-07-05 | Fairchild Semiconductor Corporation | Stacked micro optocouplers and methods of making the same |
US8222718B2 (en) * | 2009-02-05 | 2012-07-17 | Fairchild Semiconductor Corporation | Semiconductor die package and method for making the same |
JP4985810B2 (ja) * | 2010-03-23 | 2012-07-25 | サンケン電気株式会社 | 半導体装置 |
US8655481B2 (en) * | 2010-04-09 | 2014-02-18 | Victor Shi-Yueh Sheu | IMR (in-mold roller or in-mold release)/IMF (in-mold forming) making method using a digital printer printing and pre-forming technique |
US8252631B1 (en) * | 2011-04-28 | 2012-08-28 | Freescale Semiconductor, Inc. | Method and apparatus for integrated circuit packages using materials with low melting point |
US8421204B2 (en) | 2011-05-18 | 2013-04-16 | Fairchild Semiconductor Corporation | Embedded semiconductor power modules and packages |
US20130082365A1 (en) | 2011-10-03 | 2013-04-04 | International Business Machines Corporation | Interposer for ESD, EMI, and EMC |
CN105977223B (zh) * | 2012-03-01 | 2018-11-27 | 日月光半导体制造股份有限公司 | 不规则形状的封装结构及其制造方法 |
US9691745B2 (en) * | 2013-06-26 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bonding structure for forming a package on package (PoP) structure and method for forming the same |
US9252076B2 (en) | 2013-08-07 | 2016-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D packages and methods for forming the same |
US9252063B2 (en) * | 2014-07-07 | 2016-02-02 | Infineon Technologies Ag | Extended contact area for leadframe strip testing |
US20180261535A1 (en) * | 2014-12-15 | 2018-09-13 | Bridge Semiconductor Corp. | Method of making wiring board with dual routing circuitries integrated with leadframe |
DE102015215497A1 (de) | 2015-08-13 | 2017-02-16 | Volkswagen Aktiengesellschaft | Brennstoffzellenstapel mit variabler Segmentierung sowie Brennstoffzellensystem und Fahrzeug mit einem solchen |
US11393743B2 (en) * | 2019-12-18 | 2022-07-19 | Infineon Technologies Ag | Semiconductor assembly with conductive frame for I/O standoff and thermal dissipation |
Family Cites Families (70)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3982317A (en) * | 1975-07-31 | 1976-09-28 | Sprague Electric Company | Method for continuous assembly and batch molding of transistor packages |
US4789709A (en) * | 1985-05-02 | 1988-12-06 | Sumitomo Chemical Company, Limited | Process for the production of heat resistant thermoplastic copolymer |
NL8602091A (nl) * | 1986-08-18 | 1988-03-16 | Philips Nv | Beeldopneeminrichting uitgevoerd met een vaste-stof beeldopnemer en een elektronische sluiter. |
US5164218A (en) * | 1989-05-12 | 1992-11-17 | Nippon Soken, Inc. | Semiconductor device and a method for producing the same |
JPH03108744A (ja) | 1989-09-22 | 1991-05-08 | Toshiba Corp | 樹脂封止型半導体装置 |
US5172214A (en) | 1991-02-06 | 1992-12-15 | Motorola, Inc. | Leadless semiconductor device and method for making the same |
US5448450A (en) * | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
US5307272A (en) * | 1991-08-19 | 1994-04-26 | The United States Of America As Represented By The United States Department Of Energy | Minefield reconnaissance and detector system |
JP3016658B2 (ja) * | 1992-04-28 | 2000-03-06 | ローム株式会社 | リードフレーム並びに半導体装置およびその製法 |
JPH0732225B2 (ja) * | 1992-10-14 | 1995-04-10 | 富士機工電子株式会社 | リードフレームへのピン保持部の形成方法、およびダム部の形成方法 |
KR100280762B1 (ko) * | 1992-11-03 | 2001-03-02 | 비센트 비.인그라시아 | 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법 |
JP3254865B2 (ja) * | 1993-12-17 | 2002-02-12 | ソニー株式会社 | カメラ装置 |
FR2721694B1 (fr) * | 1994-06-22 | 1996-07-19 | Snecma | Refroidissement de l'injecteur de décollage d'une chambre de combustion à deux têtes. |
JPH08250641A (ja) * | 1995-03-09 | 1996-09-27 | Fujitsu Ltd | 半導体装置とその製造方法 |
US5789809A (en) | 1995-08-22 | 1998-08-04 | National Semiconductor Corporation | Thermally enhanced micro-ball grid array package |
JP3549294B2 (ja) * | 1995-08-23 | 2004-08-04 | 新光電気工業株式会社 | 半導体装置及びその実装構造 |
US5765208A (en) * | 1995-09-29 | 1998-06-09 | Motorola, Inc. | Method of speculatively executing store instructions prior to performing snoop operations |
US5637916A (en) | 1996-02-02 | 1997-06-10 | National Semiconductor Corporation | Carrier based IC packaging arrangement |
JPH09321173A (ja) * | 1996-05-27 | 1997-12-12 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及び半導体装置とそれらの製造方法 |
US5847458A (en) * | 1996-05-21 | 1998-12-08 | Shinko Electric Industries Co., Ltd. | Semiconductor package and device having heads coupled with insulating material |
JPH09312355A (ja) | 1996-05-21 | 1997-12-02 | Shinko Electric Ind Co Ltd | 半導体装置とその製造方法 |
KR19980044247A (ko) | 1996-12-06 | 1998-09-05 | 황인길 | 반도체 패키지의 몰딩방법 |
KR100258852B1 (ko) | 1996-12-19 | 2000-06-15 | 김영환 | 반도체 패키지의 제조 방법 |
US6545384B1 (en) * | 1997-02-07 | 2003-04-08 | Sri International | Electroactive polymer devices |
KR100214555B1 (ko) | 1997-02-14 | 1999-08-02 | 구본준 | 반도체 패키지의 제조방법 |
JP2000049184A (ja) * | 1998-05-27 | 2000-02-18 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6249041B1 (en) * | 1998-06-02 | 2001-06-19 | Siliconix Incorporated | IC chip package with directly connected leads |
US6229200B1 (en) | 1998-06-10 | 2001-05-08 | Asat Limited | Saw-singulated leadless plastic chip carrier |
JP2000003988A (ja) * | 1998-06-15 | 2000-01-07 | Sony Corp | リードフレームおよび半導体装置 |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6133634A (en) | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
JP2000138107A (ja) * | 1998-11-04 | 2000-05-16 | Mitsubishi Materials Corp | 半導体サージ吸収素子 |
JP4260263B2 (ja) * | 1999-01-28 | 2009-04-30 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3871486B2 (ja) * | 1999-02-17 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2000294580A (ja) | 1999-04-12 | 2000-10-20 | Nitto Denko Corp | 半導体チップの樹脂封止方法及びリ−ドフレ−ム等貼着用粘着テ−プ |
JP3686287B2 (ja) * | 1999-07-14 | 2005-08-24 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6384487B1 (en) * | 1999-12-06 | 2002-05-07 | Micron Technology, Inc. | Bow resistant plastic semiconductor package and method of fabrication |
US6720642B1 (en) | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
JP3420153B2 (ja) * | 2000-01-24 | 2003-06-23 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
DE10103428A1 (de) * | 2000-02-23 | 2001-08-30 | Basf Ag | Stabilisatoren enthaltende UV-vernetzbare Schmelzhaftklebstoffe |
US6384472B1 (en) * | 2000-03-24 | 2002-05-07 | Siliconware Precision Industries Co., Ltd | Leadless image sensor package structure and method for making the same |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6870254B1 (en) * | 2000-04-13 | 2005-03-22 | Fairchild Semiconductor Corporation | Flip clip attach and copper clip attach on MOSFET device |
US6355502B1 (en) | 2000-04-25 | 2002-03-12 | National Science Council | Semiconductor package and method for making the same |
US6661082B1 (en) | 2000-07-19 | 2003-12-09 | Fairchild Semiconductor Corporation | Flip chip substrate design |
JP3639515B2 (ja) * | 2000-09-04 | 2005-04-20 | 三洋電機株式会社 | Mosfetの実装構造の製造方法 |
US6545364B2 (en) | 2000-09-04 | 2003-04-08 | Sanyo Electric Co., Ltd. | Circuit device and method of manufacturing the same |
JP3745213B2 (ja) * | 2000-09-27 | 2006-02-15 | 株式会社東芝 | 半導体装置及びその製造方法 |
TW458377U (en) * | 2000-11-23 | 2001-10-01 | Siliconware Precision Industries Co Ltd | Sensor structure of quad flat package without external leads |
US6753605B2 (en) | 2000-12-04 | 2004-06-22 | Fairchild Semiconductor Corporation | Passivation scheme for bumped wafers |
US6798044B2 (en) | 2000-12-04 | 2004-09-28 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package with two dies |
KR20020045674A (ko) | 2000-12-09 | 2002-06-20 | 윤종용 | 테이프를 이용한 듀얼 다이 패키지 제조 방법 |
US6864423B2 (en) * | 2000-12-15 | 2005-03-08 | Semiconductor Component Industries, L.L.C. | Bump chip lead frame and package |
JP2002203957A (ja) * | 2000-12-28 | 2002-07-19 | Rohm Co Ltd | トランジスタ |
JP2002217416A (ja) * | 2001-01-16 | 2002-08-02 | Hitachi Ltd | 半導体装置 |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
KR100704311B1 (ko) | 2001-02-05 | 2007-04-05 | 삼성전자주식회사 | 내부리드 노출형 반도체 칩 패키지와 그 제조 방법 |
US6731002B2 (en) * | 2001-05-04 | 2004-05-04 | Ixys Corporation | High frequency power device with a plastic molded package and direct bonded substrate |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
US7057273B2 (en) * | 2001-05-15 | 2006-06-06 | Gem Services, Inc. | Surface mount package |
US6524886B2 (en) | 2001-05-24 | 2003-02-25 | Advanced Semiconductor Engineering Inc. | Method of making leadless semiconductor package |
US6679888B2 (en) * | 2001-05-29 | 2004-01-20 | Synthes | Femur lever |
US6633030B2 (en) | 2001-08-31 | 2003-10-14 | Fiarchild Semiconductor | Surface mountable optocoupler package |
US6461900B1 (en) * | 2001-10-18 | 2002-10-08 | Chartered Semiconductor Manufacturing Ltd. | Method to form a self-aligned CMOS inverter using vertical device integration |
US6630726B1 (en) * | 2001-11-07 | 2003-10-07 | Amkor Technology, Inc. | Power semiconductor package with strap |
US6737750B1 (en) | 2001-12-07 | 2004-05-18 | Amkor Technology, Inc. | Structures for improving heat dissipation in stacked semiconductor packages |
US6650015B2 (en) * | 2002-02-05 | 2003-11-18 | Siliconware Precision Industries Co., Ltd. | Cavity-down ball grid array package with semiconductor chip solder ball |
US7061077B2 (en) | 2002-08-30 | 2006-06-13 | Fairchild Semiconductor Corporation | Substrate based unmolded package including lead frame structure and semiconductor die |
US6777800B2 (en) * | 2002-09-30 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor die package including drain clip |
US7196313B2 (en) | 2004-04-02 | 2007-03-27 | Fairchild Semiconductor Corporation | Surface mount multi-channel optocoupler |
-
2002
- 2002-08-30 US US10/233,248 patent/US7061077B2/en not_active Expired - Lifetime
-
2003
- 2003-07-30 AU AU2003257046A patent/AU2003257046A1/en not_active Abandoned
- 2003-07-30 KR KR1020057001655A patent/KR101037997B1/ko active IP Right Grant
- 2003-07-30 JP JP2004532833A patent/JP4634146B2/ja not_active Expired - Fee Related
- 2003-07-30 CN CN2009101747995A patent/CN101685811B/zh not_active Expired - Fee Related
- 2003-07-30 WO PCT/US2003/023864 patent/WO2004021400A2/en active Application Filing
- 2003-07-30 DE DE10393164T patent/DE10393164T5/de not_active Ceased
- 2003-07-30 CN CN038203995A patent/CN1679162B/zh not_active Expired - Fee Related
- 2003-08-13 TW TW094126031A patent/TWI267176B/zh not_active IP Right Cessation
- 2003-08-13 TW TW092122242A patent/TWI266393B/zh not_active IP Right Cessation
- 2003-08-28 MY MYPI20033260A patent/MY149851A/en unknown
-
2004
- 2004-05-06 US US10/841,656 patent/US7439613B2/en not_active Expired - Fee Related
-
2005
- 2005-07-12 US US11/180,405 patent/US7504281B2/en not_active Expired - Lifetime
- 2005-07-12 US US11/180,367 patent/US8541890B2/en active Active
-
2008
- 2008-05-09 US US12/118,222 patent/US7682877B2/en not_active Expired - Lifetime
-
2009
- 2009-01-23 US US12/358,654 patent/US7790513B2/en not_active Expired - Fee Related
-
2010
- 2010-09-03 JP JP2010197828A patent/JP2011018924A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
MY149851A (en) | 2013-10-31 |
US7790513B2 (en) | 2010-09-07 |
US7504281B2 (en) | 2009-03-17 |
CN101685811B (zh) | 2012-12-05 |
JP2011018924A (ja) | 2011-01-27 |
TWI266393B (en) | 2006-11-11 |
JP4634146B2 (ja) | 2011-02-16 |
TW200408084A (en) | 2004-05-16 |
AU2003257046A8 (en) | 2004-03-19 |
CN1679162B (zh) | 2010-06-02 |
CN1679162A (zh) | 2005-10-05 |
US20060006550A1 (en) | 2006-01-12 |
US20090130802A1 (en) | 2009-05-21 |
US20080213946A1 (en) | 2008-09-04 |
TWI267176B (en) | 2006-11-21 |
WO2004021400A2 (en) | 2004-03-11 |
WO2004021400A3 (en) | 2004-06-17 |
US20040041242A1 (en) | 2004-03-04 |
US20060003492A1 (en) | 2006-01-05 |
US7439613B2 (en) | 2008-10-21 |
US7061077B2 (en) | 2006-06-13 |
KR101037997B1 (ko) | 2011-05-30 |
JP2005537664A (ja) | 2005-12-08 |
AU2003257046A1 (en) | 2004-03-19 |
KR20050039833A (ko) | 2005-04-29 |
US8541890B2 (en) | 2013-09-24 |
US7682877B2 (en) | 2010-03-23 |
TW200539401A (en) | 2005-12-01 |
US20040207052A1 (en) | 2004-10-21 |
DE10393164T5 (de) | 2005-08-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101685811B (zh) | 基于基片的未模制封装 | |
US6400004B1 (en) | Leadless semiconductor package | |
CN101807533B (zh) | 半导体管芯封装及其制作方法 | |
US5635671A (en) | Mold runner removal from a substrate-based packaged electronic device | |
CN100380636C (zh) | 用于整体成型组件的热增强封装及其制造方法 | |
CN100490140C (zh) | 双规引线框 | |
CN101207117B (zh) | 系统级封装体及其制造方法 | |
US5808359A (en) | Semiconductor device having a heat sink with bumpers for protecting outer leads | |
US8030741B2 (en) | Electronic device | |
US20020197826A1 (en) | Singulation method used in leadless packaging process | |
CN100568498C (zh) | 半导体器件及其制造方法 | |
TW200522328A (en) | Semiconductor device and manufacturing method thereof | |
CN104854695A (zh) | 具有印刷形成的端子焊盘的引线载体 | |
CN100576522C (zh) | 半导体封装结构及其制造方法 | |
US11444012B2 (en) | Packaged electronic device with split die pad in robust package substrate | |
US11764142B2 (en) | Semiconductor apparatus and method having a lead frame with floating leads | |
JP2503029B2 (ja) | 薄型構造の半導体装置の製造方法 | |
JP4162303B2 (ja) | 半導体装置の製造方法 | |
CN114944341A (zh) | 半导体结构的封装方法、封装结构和电子设备 | |
KR20000046443A (ko) | 반도체 패키지 | |
JPH0794651A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121205 Termination date: 20210730 |
|
CF01 | Termination of patent right due to non-payment of annual fee |