CN101706763B - Method and device for serialization and deserialization - Google Patents
Method and device for serialization and deserialization Download PDFInfo
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- CN101706763B CN101706763B CN2009102215717A CN200910221571A CN101706763B CN 101706763 B CN101706763 B CN 101706763B CN 2009102215717 A CN2009102215717 A CN 2009102215717A CN 200910221571 A CN200910221571 A CN 200910221571A CN 101706763 B CN101706763 B CN 101706763B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
Abstract
The invention discloses a method for serialization and deserialization, comprising the following steps: the number N of channels is taken as variable, a frame format encoding serial data is set; a local reception end determines the frame head of the received serial data according to the set frame format and converts the serial data into N-bit parallel data; the parallel data is analyzed according to the set frame format so as to obtain a link state and the N-bit parallel data is output; a local transmission end encodes the local parallel data according to the set frame format, and the parallel data corresponding to the frame format is output according to the link state resulted from the analysis of the local reception end; and the parallel data is converted into the serial data and frequency-doubling high-speed clock is utilized to output the serial data. The invention further discloses a device for serialization and deserialization; by adopting the method and the device, chips with the single-chip SERDES function can be used for the mutual conversion between parallel signals and serial signals of the different number of channels, and meanwhile, consumptive cost of users is reduced.
Description
Technical field
The present invention relates to serial communication technology, relate in particular to method and device that serial is conciliate in a kind of serial.
Background technology
Along with development of Communication Technique, people constantly increase the demand of information flow-rate, and traditional parallel interface technology then becomes the bottleneck of further raising message transmission rate.Along with the raising of chip processing speed and the development and the extensively utilization of high speed optical fiber communication technology, serial communication technology---serializer/deserializer (SERDES) technology just progressively replaces traditional parallel interface technology, and becomes popular high-speed interface technology at present.
The SERDES technology is a kind of time division multiplexing, and the point-to-point communication technology, transmitting terminal with multichannel, be that multichannel low-speed parallel signal converts high-speed serial signals to by certain agreement or framing method, and send through optical fiber or other medium, receiving end converts the high-speed serial signals that receives to the low-speed parallel signal.Wherein, carry required frame indicator signal in string and the conversion in the signal that described transmitting terminal sends, be used for the frame head that receiving end solves serial signal, the frame head that described receiving end at first solves serial signal according to the agreement or the framing method of transmitting terminal institute foundation, decompose by bit according to frame head then, solve the parallel signal of corresponding each passage.This point-to-point serial communication technology has made full use of characteristics such as the high power capacity of present transmission medium and chip processing speed height, thereby, be widely used in the industries such as communication and industrial design.
At present, a lot of chip manufacturers have developed the chip of multiple realization SERDES function, are used for N: the string of the data link that 1 ratio is different and conversion that is: are used for the mutual conversion of different low-speed parallel signal of port number and high-speed serial signals.Wherein, described N is a port number, and N 〉=2 are generally even number; Described N: 1 can be: 8: 1 or 10: 1 or 16: 1 etc. are used for 8 passages or the low-speed parallel signal of 10 passages or 16 passages etc. and the mutual conversion of high-speed serial signals.But a certain chip that possesses the SERDES function that chip manufacturer produced can only satisfy the string and the conversion of the data link of a certain fixed ratio, do not support the string and the conversion of the data link of other ratio, for example, the chip of a certain SERDES function is used to the string and the conversion of 8: 1 data link, if the user wants to change 8 channel parallel signals into 10 channel parallel signals, then can only buy the chip of 10: 1 SERDES function again, the chip of former 8: 1 SERDES function then can't be utilized again, as seen, the applicable scope underaction of chip of existing SERDES function, user's consumer cost is very high.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of serial to conciliate the method and the device of serial, makes the chip of monolithic SERDES function can be used for the mutual conversion of the parallel signal and the serial signal of different port numbers, reduces user's consumer cost.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention provides a kind of serial and conciliate the method for serial, this method comprises:
With port number N is that variable is provided with the frame format that serial data is encoded; The local reception end is oriented frame head according to the frame format that has been provided with the serial data that receives, and converts serial data to N bit parallel data; Resolve parallel data according to the frame format that has been provided with and obtain Link State, and output N bit parallel data;
Local transmitting terminal is encoded local parallel data by the frame format that is provided with, export the parallel data of corresponding frame format according to the Link State of local reception end parsing gained; Convert parallel data to serial data, and utilize the high-frequency clock output serial data after the frequency multiplication.
Wherein, described the serial data that receives is oriented before the frame head, further comprised: extract the clock in the serial data that the other side sent out,, be used for the conversion of serial data to parallel data as the sampling clock of serial data.
Wherein, before the described output N bit parallel data, further comprise: local clock is regulated the clock synchronization in the serial data that assurance local clock and the other side are sent out with reference to the clock in the serial data that the other side sent out.
Wherein, describedly convert parallel data to serial data, and utilize the high-frequency clock output serial data after the frequency multiplication, be specially:
Local N bit parallel data are become serial data with four control domain data-switching, with clock multiplier be local parallel data clock N+4 doubly, and give the other side with the serial data transmission of described high-frequency clock correspondence.
The present invention also provides a kind of serial to conciliate the device of serial, and this device comprises: module, the commentaries on classics of frame string and module, frame format decoder module, coded module, frame are set and change string module and clock multiplier module; Wherein,
The described module that is provided with, being used for port number N is that variable is provided with the frame format that serial data is encoded;
Described frame string changes and module, is used for according to the frame format that the module setting is set the serial data that receives being oriented frame head, and serial data is converted to N bit parallel data and sends to the frame format decoder module;
Described frame format decoder module is used for resolving parallel data according to the frame format that the module setting is set and obtains Link State and notification frame form coding module, and output N bit parallel data;
Described coded module is used for local parallel data is encoded by the frame format that the module setting is set, and resolves the Link State of gained according to the frame format decoder module and exports the parallel data of corresponding frame format and send to frame and commentaries on classics string module;
Described frame also changes the string module, is used for converting parallel data to serial data, and exports serial data with the high-frequency clock after the frequency multiplication; Described clock multiplier module, being used for the local clock frequency multiplication is high-frequency clock, and sends to frame and change the string module.
Wherein, this device further comprises clock recovery module, is used for extracting the clock of the serial data that the other side sends out, and sends to the frame string and change and module; Accordingly, described frame string changes and module, specifically is used for utilizing the clock of serial data, converts serial data to N bit parallel data according to the frame format that has been provided with.
This device further comprises the clock adjustment module, is used for before the frame format decoder module output N bit parallel data clock synchronization in the serial data of being sent out with reference to the adjusting local clock of the clock in the serial data that the other side sent out and the other side.
The method and the device of serial conciliate in serial provided by the invention, is that variable is provided with the frame format that serial data is encoded with port number N; The local reception end is oriented frame head according to the frame format that has been provided with the serial data that receives, and converts serial data to N bit parallel data; The local reception end is resolved parallel data according to the frame format that has been provided with and is obtained Link State, and output N bit parallel data; Local transmitting terminal is encoded local parallel data by the frame format that is provided with, export the parallel data of corresponding frame format according to the Link State of local reception end parsing gained; Local transmitting terminal converts parallel data to serial data, and utilizes the high-frequency clock output serial data after the frequency multiplication.The present invention is made as variable with port number N and is used for the implementation procedure that the serial flow process is conciliate in serial, can realize the parallel signal of different port numbers and the mutual conversion between serial signal, has saved developer's R﹠D costs, and then has reduced user's consumer cost.In addition, when the present invention obtained Link State in the parsing parallel data, any data received that can achieve a butt joint were monitored, thereby reach the effect of the Link State between monitoring the other side and this locality, are convenient to timely maintenance link.
Description of drawings
Fig. 1 conciliates the realization flow synoptic diagram that serial data is changed to parallel data in the serial approach for serial of the present invention;
Fig. 2 conciliates the realization flow synoptic diagram that parallel data is changed to serial data in the serial approach for serial of the present invention;
Fig. 3 conciliates the apparatus structure synoptic diagram of serial for serial of the present invention.
Embodiment
Basic thought of the present invention is: with port number N is that variable is provided with the frame format that serial data is encoded; The local reception end is oriented frame head according to the frame format that has been provided with the serial data that receives, and converts serial data to N bit parallel data, and resolve parallel data according to the frame format that has been provided with and obtain Link State, and output N bit parallel data;
Local transmitting terminal is encoded local parallel data by the frame format that is provided with, export the parallel data of corresponding frame format according to the Link State of local reception end parsing gained; Convert parallel data to serial data, and utilize the high-frequency clock output serial data after the frequency multiplication.
Among the present invention, described N is a port number, N 〉=2; The described frame format that serial data is encoded comprises: locating frame, Frame and erroneous frame; Accordingly, described Link State can be: the beginning that resets, receive locating frame, receive Frame and receive erroneous frame etc.
Below in conjunction with drawings and the specific embodiments the present invention is described in further detail.
Serial of the present invention is conciliate the method for serial and is mainly carried out in programmable gate array (FPGA) module at the scene, Fig. 1 conciliates the realization flow synoptic diagram that serial data is changed to parallel data in the serial approach for serial of the present invention, as shown in Figure 1, this flow process may further comprise the steps:
Step 101: with port number N is that variable is provided with the frame format that serial data is encoded;
Concrete, the FPGA module is that variable is provided with the frame format that serial data is encoded with port number N, and here, the described frame format that serial data is encoded has three types, comprise: locating frame, Frame and erroneous frame, various frames are made up of data field and control domain, wherein, and described control domain, be that control signal is four, data field is the N position, and every frame comprises N+4 bit, and the transfer rate that therefore can calculate serial data is N+4 a times of parallel data.
Described three kinds of frame formats are described in tabulation respectively in detail below, and described locating frame is as shown in table 1:
Table 1
As shown in table 1, locating frame described in the present invention has two kinds, be locating frame A and locating frame B, can find out, locating frame A is identical with the parallel data frequency and dutycycle is 50% signal, locating frame B is identical with the parallel data frequency, and dutycycle is not 50% but high level is Duoed one signal than low level.
Described Frame has four kinds, and is as shown in table 2:
| ? | Data field | Control domain |
| True value | D0～D(N-1) | 1101 |
| Negate | /(D0～D(N-1)) | 0010 |
| True value | D0～D(N-1) | 1011 |
| Negate | /(D0～D(N-1)) | 0100 |
Table 2
Here, described "/" expression bit negate, four kinds of Frames are used for the alternate transmission of data, prevent that data from being 0 continuously or being continuously at 1 o'clock, the problem that receiving end can not recovered clock.
Described erroneous frame has eight kinds, and is as shown in table 3:
Table 3
Wherein, described " x " expression 0 or 1; The kind of described one to eight expression erroneous frame promptly has eight kinds.
Among the present invention, the other side's transmitting terminal at first transmission frame format is the serial data of locating frame A, phaselocked loop is in that to send form after the steady state (SS) be the serial data of locating frame B, that is to say, transmission frame format is the serial data of locating frame A before the local reception end is determined the frame head position, after the position of frame head is determined, be the serial data of locating frame B to the other side's transmission frame format, finished the process of deciding frame head to notify the other side this locality, the stable once more back of phaselocked loop transmission frame format is the serial data of Frame, in transmission frame format is in the serial data process of Frame, because fault may transmission frame format be the serial data of erroneous frame.
Step 102: the local reception end is oriented frame head according to the frame format that has been provided with the serial data that receives;
Concrete, receiving end in the local FPGA module is oriented frame head according to the frame format that has been provided with the serial data that receives, and here, can be found out by three kinds of set in the step 101 frame formats, only when the other side sends locating frame, could determine that in data stream where frame head.Because when the other side sends locating frame, have only a negative edge and a rising edge in the data stream, and locating frame for two kinds of forms, the position of its rising edge all is fixed between the second and the 3rd bit of control domain, the present invention utilizes the position of this rising edge to carry out frame alignment, and frame head is located in the position of the 3rd bit of this rising edge back.If frame head is the location not, then the local reception end will constantly be searched the rising edge of serial data, is positioned up to frame head.
Further, before locating frame head, the present invention also comprises the clock that extracts in the serial data that the other side sent out, and as the sampling clock of serial data, is used for the conversion of serial data to parallel data.Wherein, described clock, i.e. the other side's clock.
Step 103: the local reception end converts serial data to N bit parallel data;
Be specially: behind the frame head location of the receiving end in the local FPGA module with serial data, utilize the clock in the serial data to convert the follow-up serial data that receives to N bit parallel data by the frame format that has been provided with, promptly convert N bit parallel data and four data that the control domain data are formed to.
Among the present invention, before setting up both sides' link, at first determine described N: the concrete numerical value of N in the string of 1 data link and the conversion, carry out the mutual conversion between described serial data and the parallel data afterwards again so that set up both sides' link.
Step 104: the local reception end is resolved parallel data according to the frame format that has been provided with and is obtained Link State and notify local transmitting terminal, exports N bit parallel data afterwards;
Be specially: the data that the receiving end in the local FPGA module is formed the N bit parallel data that convert to and four control domain data are resolved, obtain current Link State and notify local transmitting terminal, for example: if the frame format of the data correspondence of N bit parallel data and four control domain data compositions is a Frame, then current Link State is: receive Frame, export N bit parallel data afterwards; If the frame format of the data correspondence of N bit parallel data and four control domain data compositions is a locating frame, then current Link State is: receive locating frame, export N bit parallel data afterwards; If the frame format of the data correspondence of N bit parallel data and four control domain data compositions is an erroneous frame, then current Link State is: receive erroneous frame, export N bit parallel data afterwards; Before both sides' link establishment, current Link State is: the beginning that resets, local transmitting terminal can send locating frame to the other side and begin to set up link, in addition, also will return the initial state that resets and rebulid link after the local reception end is received erroneous frame.
Here, the parallel data of described output is not valid data entirely, has only Link State when receiving Frame, the parallel data of output is valid data, if and receive locating frame, then do not comprise the data message that will transmit in the data of locating frame correspondence, therefore be not valid data; If receive erroneous frame, then the data message of erroneous frame correspondence is error message, and what prove transmission is error code, is not valid data therefore.
Further, before output N bit parallel data, need local clock to be regulated, guarantee local clock and the other side's clock synchronization with reference to the other side's clock.
Among the present invention,, then return step 102, rebulid link local and the other side, reached the effect of monitoring link status always, be convenient in time safeguard the link between this locality and the other side if receive erroneous frame.
Fig. 2 conciliates the realization flow synoptic diagram that parallel data is changed to serial data in the serial approach for serial of the present invention;
Step 201: local transmitting terminal is encoded local parallel data by the frame format that is provided with;
Be specially: the transmitting terminal in the local FPGA module is encoded N bit parallel data and four control domain data of this locality by three kinds of frame formats of the Link State correspondence of local reception end parsing gained.
Step 202: the parallel data of exporting corresponding frame format according to the Link State of local reception end parsing gained;
Here, transmitting terminal in the local FPGA module is resolved the Link State that parallel data obtains according to local reception end in the step 104, send the parallel data of different frame formats, if, then export the parallel data of locating frame form if current Link State is to reset beginning or resolve Link State that parallel data obtains when receiving locating frame; If resolve Link State that parallel data obtains when receiving Frame, the parallel data of output data frame format then is so that this locality and the two-way foundation of the other side link between the two.More specifically, before phaselocked loop that the link of resolving gained is in reset initial state or receiving end was in steady state (SS), transmission frame format was the parallel data of locating frame A; After the phaselocked loop of receiving end is in steady state (SS) and link be in receive Frame before the time, transmission frame format is the parallel data of locating frame B; When the Link State of resolving gained when receiving Frame, then transmission frame format is the parallel data of Frame.
Here, the Link State that described local transmitting terminal is resolved gained with the local reception end serve as according to the former of the parallel data of the corresponding frame format of output because: the method that serial is conciliate in serial of the present invention is mainly used in the process of setting up of link between this locality and the other side, therefore, local transmitting terminal should echo with the data frame format that the local reception termination is received mutually to the data frame format that the other side sends, so that the foundation of link between the both sides.
Step 203: local transmitting terminal converts parallel data to serial data, and utilizes the high-frequency clock output serial data after the frequency multiplication;
Be specially: the transmitting terminal in the local FPGA module becomes serial data with local N bit parallel data with four control domain data-switching, and be local parallel data clock N+4 high-frequency clock doubly with clock multiplier, give the other side with the serial data transmission of this high-frequency clock correspondence afterwards.
Fig. 3 conciliates the apparatus structure synoptic diagram of serial for serial of the present invention, as shown in Figure 2, this device comprises: module, the commentaries on classics of frame string and module, frame format decoder module, coded module, frame are set and change string module and clock multiplier module, except that the clock multiplier module, all be integrated in field programmable gate array (FPGA) module, described frame string commentaries on classics and module and frame format decoder module are positioned at receiving end, and described coded module, frame and commentaries on classics string module and clock multiplier module are positioned at transmitting terminal; Wherein,
The described module that is provided with, being used for port number N is that variable is provided with the frame format that serial data is encoded;
Described frame string changes and module, is used for according to the frame format that the module setting is set the serial data that receives being oriented frame head, and serial data is converted to N bit parallel data and sends to the frame format decoder module;
Described frame format decoder module is used for resolving parallel data according to the frame format that the module setting is set and obtains Link State and notification frame form coding module, and output N bit parallel data;
Described coded module is used for local parallel data is encoded by the frame format that the module setting is set, and resolves the Link State of gained according to the frame format decoder module and exports the parallel data of corresponding frame format and send to frame and commentaries on classics string module;
Described frame also changes the string module, is used for converting parallel data to serial data, and utilizes the high-frequency clock after the frequency multiplication to export serial data;
Described clock multiplier module, being used for the local clock frequency multiplication is high-frequency clock, and sends to frame and change the string module.
This device further comprises clock recovery module, is used for extracting the clock of the serial data that the other side sends out, and sends to the frame string and change and module; Accordingly, described frame string changes and module, specifically is used for utilizing the clock of serial data, converts serial data to N bit parallel data according to the frame format that has been provided with.
This device further comprises the clock adjustment module, is used for regulating local clock and the other side's clock synchronization with reference to the other side's clock before the frame format decoder module output N bit parallel data.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. the method for serial is conciliate in a serial, it is characterized in that this method comprises:
With port number N is that variable is provided with the frame format that serial data is encoded; The local reception end is oriented frame head according to the frame format that has been provided with the serial data that receives, and converts serial data to N bit parallel data; Resolve parallel data according to the frame format that has been provided with and obtain Link State, and output N bit parallel data;
Local transmitting terminal is encoded local parallel data by the frame format that is provided with, export the parallel data of corresponding frame format according to the Link State of local reception end parsing gained; Convert parallel data to serial data, and utilize the high-frequency clock output serial data after the frequency multiplication.
2. the method for serial is conciliate in serial according to claim 1, it is characterized in that, described the serial data that receives is oriented before the frame head, further comprise: extract the clock in the serial data that the other side sent out, as the sampling clock of serial data, be used for the conversion of serial data to parallel data.
3. the method for serial is conciliate in serial according to claim 1 and 2, it is characterized in that, before the described output N bit parallel data, further comprise: local clock is regulated the clock synchronization in the serial data that assurance local clock and the other side are sent out with reference to the clock in the serial data that the other side sent out.
4. the method for serial is conciliate in serial according to claim 1 and 2, it is characterized in that, describedly converts parallel data to serial data, and utilizes the high-frequency clock output serial data after the frequency multiplication, is specially:
Local N bit parallel data are become serial data with four control domain data-switching, with clock multiplier be local parallel data clock N+4 doubly, and give the other side with the serial data transmission of described high-frequency clock correspondence.
5. the device of serial is conciliate in a serial, it is characterized in that this device comprises: module is set, the frame string changes and module, frame format decoder module, coded module, frame and change string module and clock multiplier module; Wherein,
The described module that is provided with, being used for port number N is that variable is provided with the frame format that serial data is encoded;
Described frame string changes and module, is used for according to the frame format that the module setting is set the serial data that receives being oriented frame head, and serial data is converted to N bit parallel data and sends to the frame format decoder module;
Described frame format decoder module is used for resolving parallel data according to the frame format that the module setting is set and obtains Link State and notification frame form coding module, and output N bit parallel data;
Described coded module is used for local parallel data is encoded by the frame format that the module setting is set, and resolves the Link State of gained according to the frame format decoder module and exports the parallel data of corresponding frame format and send to frame and commentaries on classics string module;
Described frame also changes the string module, is used for converting parallel data to serial data, and exports serial data with the high-frequency clock after the frequency multiplication;
Described clock multiplier module, being used for the local clock frequency multiplication is high-frequency clock, and sends to frame and change the string module.
6. the device of serial is conciliate in serial according to claim 5, it is characterized in that this device further comprises clock recovery module, is used for extracting the clock of the serial data that the other side sends out, and sends to also module of frame string commentaries on classics;
Accordingly, described frame string changes and module, specifically is used for utilizing the clock of serial data, converts serial data to N bit parallel data according to the frame format that has been provided with.
7. conciliate the device of serials according to claim 5 or 6 described serials, it is characterized in that, this device further comprises the clock adjustment module, be used for before the frame format decoder module output N bit parallel data clock synchronization in the serial data of being sent out with reference to the adjusting local clock of the clock in the serial data that the other side sent out and the other side.
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| CN2009102215717A CN101706763B (en) | 2009-11-20 | 2009-11-20 | Method and device for serialization and deserialization |
| PCT/CN2010/077346 WO2011060669A1 (en) | 2009-11-20 | 2010-09-27 | Serializing and deserializing method and apparatus |
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| CN2009102215717A CN101706763B (en) | 2009-11-20 | 2009-11-20 | Method and device for serialization and deserialization |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101706763B (en) * | 2009-11-20 | 2011-11-30 | 中兴通讯股份有限公司 | Method and device for serialization and deserialization |
| CN101945061A (en) * | 2010-09-06 | 2011-01-12 | 北京国科环宇空间技术有限公司 | High-speed baseband data transmission method and system based on field-programmable gate array |
| CN202615145U (en) * | 2011-01-05 | 2012-12-19 | 浙江彩虹鱼通讯技术有限公司 | Interface control circuit, all-fiber joint and all-fiber transmission line |
| CN102710240B (en) * | 2011-03-08 | 2016-03-02 | 浙江彩虹鱼通讯技术有限公司 | Signal processing apparatus, method, SERDES and processor |
| US9378174B2 (en) * | 2013-11-04 | 2016-06-28 | Xilinx, Inc. | SERDES receiver oversampling rate |
| CN104009823B (en) * | 2014-06-02 | 2017-07-07 | 复旦大学 | Dislocation detection and error correction circuit in a kind of SerDes technologies |
| CN108010554B (en) * | 2016-10-27 | 2020-09-29 | 华为技术有限公司 | Data access system, data writing method and data reading method |
| CN109144915A (en) * | 2017-06-13 | 2019-01-04 | 上海复旦微电子集团股份有限公司 | Data transmission method, data transmission interface and computer readable storage medium |
| CN108090015B (en) * | 2017-12-22 | 2021-06-29 | 西安烽火电子科技有限责任公司 | High-speed serial port communication method for heterogeneous interconnection of multiple types of interfaces |
| CN108737025B (en) * | 2018-04-26 | 2021-06-01 | 北京集创北方科技股份有限公司 | Encoding method and device and decoding method and device |
| CN110781116A (en) * | 2019-11-15 | 2020-02-11 | 广州健飞通信有限公司 | High speed point-to-point serial interface system |
| CN112910467B (en) * | 2019-12-03 | 2022-09-09 | 烽火通信科技股份有限公司 | NRZ coding circuit, encoder and high-speed interface circuit |
| CN116257484A (en) * | 2021-12-10 | 2023-06-13 | 华为技术有限公司 | Data transmission chip and electronic equipment |
| CN115080477B (en) * | 2022-05-30 | 2024-01-30 | 杭州初灵信息技术股份有限公司 | Method and system for serial communication |
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| US6288656B1 (en) * | 1999-12-21 | 2001-09-11 | Lsi Logic Corporation | Receive deserializer for regenerating parallel data serially transmitted over multiple channels |
| US7286572B2 (en) * | 2003-01-10 | 2007-10-23 | Sierra Monolithics, Inc. | Highly integrated, high-speed, low-power serdes and systems |
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| TWI360964B (en) * | 2006-11-08 | 2012-03-21 | Finisar Corp | Serialization/deserialization for use in optoelect |
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2009
- 2009-11-20 CN CN2009102215717A patent/CN101706763B/en not_active Expired - Fee Related
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2010
- 2010-09-27 WO PCT/CN2010/077346 patent/WO2011060669A1/en active Application Filing
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|---|---|---|---|---|
| US6112276A (en) * | 1997-10-10 | 2000-08-29 | Signatec, Inc. | Modular disk memory apparatus with high transfer rate |
Non-Patent Citations (4)
| Title |
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| JP特开2002-217742A 2002.08.02 |
| JP特开2008-283331A 2008.11.20 |
| JP特开平8-163081A 1996.06.21 |
| JP特开平8-335127A 1996.12.17 |
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| Publication number | Publication date |
|---|---|
| WO2011060669A1 (en) | 2011-05-26 |
| CN101706763A (en) | 2010-05-12 |
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