CN101719497B

CN101719497B - New type integrated circuit for resisting full-scale irradiation of NMOS component

Info

Publication number: CN101719497B
Application number: CN200910238271XA
Authority: CN
Inventors: 刘�文; 黄如; 王思浩; 黄德涛; 王健
Original assignee: Peking University
Current assignee: Semiconductor Manufacturing International Beijing Corp
Priority date: 2009-11-24
Filing date: 2009-11-24
Publication date: 2012-01-18
Anticipated expiration: 2029-11-24
Also published as: CN101719497A

Abstract

The invention discloses an integrated circuit for resisting full-scale irradiation of a NMOS component, belonging to the field of electronic technique. The integrated circuit for resisting full-scale irradiation of a NMOS component of the invention comprises a NMOS component and a PMOS component. The components are separated via a tunnel on a substrate. The tunnel is filled with filler materials. In a tunnel adjacent to the NMOS component, a sacrifice material layer is embedded in the filler materials, wherein the sacrifice material is silicon doped with the third main group element. The invention can be applied to the industries relative to full-scale irradiation such as aerospace, military affairs, nuclear power, high energy physics, and the like.

Description

The integrated circuit of resisting NMOS element total dose radiation

Technical field

The present invention relates to integrated circuit, relate in particular to a kind of integrated circuit of resisting NMOS element total dose radiation, belong to electronic technology field.

Background technology

Integrated circuit technique being applied in the industry relevant such as space flight, military affairs, nuclear power and high-energy physics just more and more widely with total dose irradiation.And along with the improving constantly of integrated circuit integrated level, size of semiconductor device reduces day by day, and the shallow-trench isolation technology just becomes in the integrated circuit mainstream technology of electric isolation between the device with its good device isolation performance.But because the total dose irradiation particle for the damage of silicon dioxide oxide layer in the device, can produce a large amount of fixed positive charges in the oxide layer of shallow groove isolation structure.In nmos device; The existence of these a large amount of fixed positive charges can cause near the substrate transoid the shallow-trench isolation oxide layer; And under certain source drain bias, form the phost line electric leakage, and the size of electrical leakage quantity is relevant apart from distance and these positive charge concentrations of silicon substrate with these positive charges, and promptly shallow groove isolation structure material electropositive behind total dose irradiation is strong more; Near more apart from silicon substrate, electric leakage is just big more.Before device was responsible for unlatching, the person in charge was in OFF state, but phost line conducting at this moment forms bigger off-state leakage current.This off-state leakage current can increase power consumption of integrated circuit greatly, and the reliability of integrated circuit is produced bigger negative effect, becomes the total dose irradiation integrity problem that present stage needs to be resolved hurrily.

Therefore; If can propose under the main flow preparation technology's who does not change shallow-trench isolation technology the prerequisite a kind of can reduce total dose irradiation after the electropositive of shallow-trench isolation material; And the distance between increase positive charge and the silicon substrate; Suppress these electropositivies to reach, thereby reduce the isolation technology of CMOS integrated circuit and device off-state leakage current behind the nmos device total dose irradiation, will the anti-irradiation reinforcing of whole integrated circuit be significant.

Summary of the invention

The purpose of this invention is to provide a kind of integrated circuit preventing total dose radiation that can reduce off-state leakage current behind the nmos device total dose irradiation.

The present invention is on existing C MOS integrated circuit shallow-trench isolation technology (shallow-trench isolation:STI) basis; Can in silicon materials, respond to the characteristic that produces negative electrical charge to the positive charge in the silicon dioxide; In conventional shallow groove isolation structure, increase one deck sacrificial material layer; The electric field of a large amount of fixed positive charges inside the silicon dioxide in the shallow groove isolation structure is limited on this one deck sacrificial material layer; Weakening transoid effect, thereby reduce parasitic transistor electric current behind the total dose irradiation, reach the purpose that reduces off-state leakage current behind the nmos device total dose irradiation the body silicon substrate.

Specifically, in order to reach above-mentioned technical purpose, the present invention adopts following technical scheme:

A kind of integrated circuit of resisting NMOS element total dose radiation, said integrated circuit comprises nmos device, also can comprise the PMOS device; Pass through the trench isolations on the substrate between the said device; Be filled with trench fill material in the groove, it is characterized in that, with said nmos device adjacent grooves in; Embed a sacrificial material layer in the said trench fill material, said expendable material is the silicon of the 3rd major element of having mixed.That is to say that in two grooves of each nmos device both sides, it still is that the PMOS device is adjacent irrelevant that this sacrificial material layer and this nmos device and nmos device all are set, shown in Fig. 1 b.

Said sacrificial material layer sandwiches between two parts that said trench fill material is separated, and its first (bottom) is between substrate and said sacrificial material layer, and second portion (top) is then surrounded by said sacrificial material layer three faces.Above-mentioned three-decker generally obtains through each layer deposit successively, that is, and and the said first of deposit successively, said expendable material and said second portion.Therefore; The cross sectional shape of said first and said sacrificial material layer consistent with the profile of said groove (corresponding), that is, because the cross section of said groove generally is trapezoidal (last base is more trapezoidal than the length of side of going to the bottom); Therefore, the cross section of said first and said sacrificial material layer all takes the shape of the letter U.

Said the 3rd major element comprises one or more in boron, aluminium, gallium, indium and the thallium.The doping content of said sacrificial layer material is 5 * 10 ¹⁶To 1 * 10 ¹⁸/ cm ³Scope in; Thickness is preferably in the scope of 10 nanometers and 80 nanometers.

Said trench fill material can be the conventional silicon dioxide that uses, and said backing material can be the conventional silicon that uses.

Fig. 1 a, b have shown conventional shallow-trench isolation technology and the interfacial structure of the present invention between groove and substrate respectively.Fig. 2 has shown that conventional shallow grooved-isolation technique structure and preventing total dose radiation process structure of the present invention are through producing the contrast of transoid carrier concentration behind the total dose irradiation in substrate.

From Fig. 1 and Fig. 2, can find out; In the shallow grooved-isolation technique structure of routine; Mirror image goes out a large amount of transoid charge carriers, promptly a large amount of electronics because the existence of trench fill material, a large amount of fixed positive charges that total dose irradiation produces in groove can be inducted in silicon substrate; These electronics leak in the source under the situation be added with bias voltage can conducting, causes in OFF state, just having bigger leakage current at nmos pass transistor.Preventing total dose radiation process structure of the present invention can be responded to the characteristic that produces negative electrical charge to positive charge in the silicon dioxide in silicon materials; In conventional shallow groove isolation structure, increase one deck silicon materials sacrifice layer; The electric field of a large amount of fixed positive charges inside the silicon dioxide in the shallow groove isolation structure is limited in this above one deck sacrifice layer; The existence of a large amount of fixed negative charges that positive charge produces in the silicon materials sacrifice layer in the silicon dioxide has weakened in the shallow groove isolation structure silicon dioxide greatly to the transoid effect of body silicon substrate; And increased the distance between a large amount of fixed positive charges and substrate in the shallow groove isolation structure; And the skim earth silicon material (being above-mentioned first) that joins with substrate is because very thin (such as 10 nanometer to 20 nanometers), and the amount of the fixed positive charge that the inside produces is considerably less, can ignore the influence of substrate.This structural design can play and suppress even offset trench fill material internal fixation positive charge to the effect of inducting of the mirror image of charge carrier in the silicon substrate; The charge carrier transoid that suppresses silicon substrate; Make the conducting charge carrier of parasitic transistor reduce significantly even be reduced to zero; Thereby reduce the off-state leakage current of nmos device significantly, make the anti-radiation performance of integrated circuit obtain lifting by a relatively large margin.

In addition; Another characteristics of preventing total dose radiation process structure of the present invention are characteristics that the silicon technology material has and traditional CMOS technology is compatible fully that the P type that adopted mixes; And having kept traditional shallow grooved-isolation technique structure in all technical advantages that have aspect the integrated circuit isolation, manufacturing technology steps is very simple.

Compare with prior art; The isolation technology that can reduce off-state leakage current behind the integrated circuit nmos device total dose irradiation significantly proposed by the invention; Can strengthen the preventing total dose radiation performance of integrated circuit greatly; Be significant for power consumption that reduces integrated circuit under the total dose irradiation and the reliability that strengthens integrated circuit, in integrated circuit preventing total dose radiation reinforcement technique is used, remarkable advantages and application prospects arranged.

Description of drawings

Fig. 1 shows conventional shallow-trench isolation technology and integrated circuit of the present invention interfacial structure difference between groove and substrate, and Fig. 1 a representes routine techniques, and Fig. 1 b representes the present invention's technology;

Fig. 2 has shown that conventional shallow grooved-isolation technique structure and preventing total dose radiation process structure of the present invention are through producing the contrast of transoid carrier concentration behind the total dose irradiation in substrate;

Fig. 3-8 shows that embodiment prepares each step of integrated circuit.

Embodiment

Combine accompanying drawing that the present invention is further described through a concrete preparation embodiment below.

The present embodiment preparation mainly comprises the steps: according to the integrated circuit of resisting NMOS element total dose radiation of the present invention

1) formation of silicon dioxide and silicon nitride.As shown in Figure 3; The silicon dioxide that is approximately 100 Ethylmercurichlorendimide to 200 Ethylmercurichlorendimides at thermal oxide growth one layer thickness on the silicon substrate 1 is as the stress-buffer layer between silicon nitride and the silicon substrate 2; And then with low-pressure chemical vapor phase deposition (LPCVD) method deposit one deck 1000 Ethylmercurichlorendimide to 1500 Ethylmercurichlorendimide silicon nitrides, as barrier layer 3.

2) gully photoetching and etching.As shown in Figure 4, behind figure shown in going out with the reticle lithographic definition, with reactive ion etching (RIE) method etching trapezoidal groove 4 between the MOS device, etching gas can be C1 ₂, HBr, and O ₂Deng, groove width is about 100 to 250 nanometers, and groove depth is about 300 nanometer to 500 nanometers, and the angle of inclination on the trapezoid limit of dovetail groove is about 75 °～89 °.

3) earth silicon material of deposit for the first time.As shown in Figure 5, in the groove 4 with first silicon dioxide layer 5 to step 2 etching of high-density plasma CVD (HDPCVD) method deposit.The ratio of etching and deposit is so-called Etch/Depo ratio, remains between 0.14～0.33 usually.The thickness of deposit is approximately 10 nanometer to 20 nanometers.

4) deposit sacrificial layer material.As shown in Figure 6, to the groove 4 of step 2 etching, this P type silicon layer mixes with boron, aluminium, gallium, indium or thallium grade in an imperial examination three major elements with the method deposit sacrificial layer material P type silicon layer 6 of high-density plasma CVD (HDPCVD), and doping content is 5 * 10 ¹⁶-1 * 10 ¹⁸/ cm ³In the scope.The ratio of etching and deposit is so-called Etch/Depo ratio, remains between 0.14～0.33 usually.The thickness of deposit is approximately 10 nanometer to 80 nanometers.

5) earth silicon material of deposit for the second time.As shown in Figure 7, in the groove 4 with second silicon dioxide layer 7 to step 2 etching of high-density plasma CVD (HDPCVD) method deposit.The ratio of etching and deposit is so-called Etch/Depo ratio, remains between 0.14～0.33 usually.

6) all material and the stress-buffer layer of removal barrier layer 3 above deposits.As shown in Figure 8, with chemico-mechanical polishing (CMP), SPA boils, and methods such as rinsing are removed various deposition materials and stress buffer layer material, obtain final isolation structure.

Claims

1. the integrated circuit of a resisting NMOS element total dose radiation, said integrated circuit comprises nmos device, also can comprise the PMOS device; Pass through the trench isolations on the substrate between the said device; Be filled with trench fill material in the groove, it is characterized in that, with said nmos device adjacent grooves in; Embed a sacrificial material layer in the said trench fill material, said expendable material is the silicon of the 3rd major element of having mixed; The doping content of said expendable material is 5 * 10 ¹⁶To 1 * 10 ¹⁸/ cm ³Scope in, in the scope of 80 nanometers, and the distance of said sacrificial material layer and substrate is 10 nanometer to 20 nanometers to the thickness of said sacrificial material layer in 10 nanometers.

2. the integrated circuit of resisting NMOS element total dose radiation as claimed in claim 1 is characterized in that, said the 3rd major element comprises one or more in boron, aluminium, gallium, indium and the thallium.

3. like the integrated circuit of any described resisting NMOS element total dose radiation of claim 1-2, it is characterized in that said trench fill material is a silicon dioxide.

4. like the integrated circuit of any described resisting NMOS element total dose radiation of claim 1-2, it is characterized in that said backing material is a silicon.