CN101741228B - Active load master circuit for eliminating common mode surge interference - Google Patents
Active load master circuit for eliminating common mode surge interference Download PDFInfo
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- CN101741228B CN101741228B CN200810173899A CN200810173899A CN101741228B CN 101741228 B CN101741228 B CN 101741228B CN 200810173899 A CN200810173899 A CN 200810173899A CN 200810173899 A CN200810173899 A CN 200810173899A CN 101741228 B CN101741228 B CN 101741228B
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Abstract
The invention relates to an active load master circuit for eliminating common mode surge interference, which biases between a first voltage and a second voltage and is accompanied with a common mode surge. The active load master circuit comprises a pair of boosting circuits and a pair of active load circuits; the common mode surge is offset through a symmetric structure of the pair of boosting circuits; at least one SET signal and at least one RESET signal respond to a pulse signal or a complementary pulse signal and are provided to a latch; at least one SET signal or at least one RESET signal can be boosted to the first voltage or pulled down to the second voltage; and the voltage difference between the SET signal and the RESET signal is enough to drive the latch.
Description
Technical field
The invention relates to a kind of pulsed filter, particularly can eliminate the pulsed filter that common mode surge disturbs about a kind of, it can be applicable to a half-bridge or the high side driver of full-bridge.
Background technology
Prior art of the present invention is described, the relation of pulsed filter and half-bridge or the high side driver of full-bridge should be introduced earlier.Please with reference to Fig. 1, it shows the structure of a typical half bridge driver 100.As shown in Figure 1, this typical half bridge driver 100 comprises a pulse generator 101, one pulsed filters 102 at least, and a latch unit 103.
This pulse generator 101 is in order to produce a pulse signal and a complementary pulse signal.This pulsed filter 102 is to follow the common mode surge of VBOOT and HBOUT power supply in order to filtering one, and produces a SET signal and a RESET signal to supply with this latch unit 103.This latch unit 103 is in order to see signal to a driver off to switch the on off state of a high side power MOSFET.Between transfer period, because the element characteristic of capacitor C BOOT, that is the voltage at capacitor two ends can flip-flop, and a surging is to give birth to thereupon; And this surging can continue till this capacitor C BOOT reaches stable state.This pulsed filter 102 is in order to handle this surging problem to prevent this latch unit 103 misoperations.
The solution that one this surging of elimination disturbs is to offset with differential with a symmetrical structure.Please with reference to Fig. 2, it shows that a known pulsed filter 300 follows the common mode surge of power supply in order to elimination.As shown in Figure 2, this known pulsed filter 300 has a resistance 301, one PMOS transistors 302, one PMOS transistors 303, one resistance 304, one PMOS transistors 305, one PMOS transistors 306, one resistance 307, and a resistance 308.
In fact this known pulsed filter 300 can be divided into a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 301 to promoting circuit, and this PMOS transistor 302 and this PMOS transistor 303 are the left side for example in a side, and comprise this resistance 304, and this PMOS transistor 305 and this PMOS transistor 306 also are the right side in opposite side.This left side drags down circuit to be made up of this resistance 307, is made up of this resistance 308 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 302 and this PMOS transistor 305 and source voltage can change simultaneously and voltage difference is remained unchanged.If original this PMOS transistor 302 for this PMOS transistor 305 of conducting for closing, then those logical resistance states will remain unchanged.Yet too low if this surging falls, the voltage of being set up at this resistance 307 will be compressed, and possibly cause this latch unit 103 misoperations.In addition, by resistance 301, transistor 302, transistor 303, the direct current guiding path that reaches resistance 307 formation can consume many power, and those resistance also occupy no small chip area.
Hereat, voltage drop, power consumption, and considering of factor such as chip area be to be entangled with in the design process of a pulsed filter.
Hereat, need one badly the SET signal of enough big voltage swing and the strong pulsed filter of RESET signal can be provided, disturb and guarantee the latch unit normal operation to overcome surging.
Summary of the invention
A purpose of the present invention provides a kind of effective and strong mechanism, disturbs in order to the surging of eliminating in the high side driver of a half-bridge or full-bridge.
Another object of the present invention is the active load master circuit that a kind of novelty further is provided, and it can produce enough big voltage swing driving a latch unit, thereby has relaxed the design specification of latch unit, and latch unit is realized easily.
Another object of the present invention is the active load master circuit that a kind of novelty further is provided, and it can produce enough big voltage swing and can not consume direct current power.
Another object of the present invention is the active load master circuit that a kind of novelty further is provided, and it can produce enough big voltage swing and only account for very little chip area.
Another object of the present invention is the active load master circuit that a kind of novelty further is provided, and it can produce at least one SET signal and at least one RESET signal, with the problem of utilizing the instantaneous solution common mode surge of this surging to disturb.
For reaching above-mentioned purpose; The present invention proposes one can eliminate the active load master circuit that common mode surge disturbs; It has a pair of lifting circuit and a pair of active load master circuit; Can provide an enough big voltage swing at least one SET signal and at least one RESET signal and do not consume direct current power according to this, and can eliminate common mode surge and disturb.The present invention does not need resistance to set up direct voltage again, and shared chip area can significantly dwindle.
Active load master circuit of the present invention can be applicable to disturb to eliminate common mode surge such as but not limited to a half-bridge or the high side driver of full-bridge.It is to be biased between a supply power voltage and the reference voltage, and a common mode surging is followed therebetween.This active load master circuit comprises a pair of lifting circuit and pair of active load circuits.This provides a symmetrical structure that this common mode surge can be offseted in this promoting in the circuit to promoting circuit, and the path that is connected to this supply power voltage is provided, and wherein whether this path conducting is to react on a pulse signal or a complementary pulse signal.This is to place this to promoting between circuit and this supply power voltage, in order to produce at least one SET signal and at least one RESET signal to drive a latch unit to active load circuits.
In this circuit, this has at least one pair of active member to react on this pulse signal or should the complementation pulse signal and be connected to this reference voltage to active load circuits.Those SET signals and RESET signal are not to be connected to this supply power voltage via this to promoting circuit, via this active load circuits are connected to this reference voltage exactly.
So the present invention can provide enough big voltage swing; Be based on its design; That is each SET signal and RESET signal be not the power supply that obtains this supply power voltage via this lifting circuit, is pulled low to this reference voltage via this active load circuits exactly, and do not have the direct current guiding path and exist.Because those SET signals and RESET signal do not need direct current to set up voltage, the known resistance that drags down in the circuit can omit, thereby power consumption and chip area can contract to minimum.
Description of drawings
For making the auditor can further understand structure of the present invention, characteristic and purpose thereof, below in conjunction with the detailed description of accompanying drawing and preferred embodiment as after, wherein:
Fig. 1 is a sketch map, and it illustrates the structure chart of a typical half bridge driver.
Fig. 2 is a sketch map, and it illustrates the circuit diagram of a known pulsed filter.
Fig. 3 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs.
Fig. 4 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Fig. 5 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Fig. 6 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Fig. 7 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Fig. 8 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Fig. 9 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Figure 10 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Figure 11 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Figure 12 is a sketch map, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs.
Embodiment
Described in the prior art explanation, this is to form with resistance to dragging down circuit, therefore when setting up a SET signal level or a RESET signal level, will inevitably consume direct current power.Yet,,, all can not consume direct current power no matter its outputting level is to be in supply power voltage or earthing potential according to the CMOS logic.If this latch unit is not reacted, then can avoid this latch unit misoperation during surging again.The present invention has grasped these viewpoints and has proposed some solutions, and its execution mode will specify in following each embodiment.
Please with reference to Fig. 3, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; As shown in Figure 3, active load master circuit 400 of the present invention comprises a resistance 401, one PMOS transistors 402; One PMOS transistor, 403, one resistance, 404, one PMOS transistors 405; One PMOS transistor, 406, one resistance, 407, one nmos pass transistors 408; One resistance 409, and a nmos pass transistor 410.The grid of this PMOS transistor 402 be the drain electrode of grid and this PMOS transistor 406 of the grid that is connected to this nmos pass transistor 408, this PMOS transistor 403 being coupled to a pulse complementary signal (CLKB), and the drain electrode of grid and this PMOS transistor 403 of grid, this PMOS transistor 406 that the grid of this PMOS transistor 405 is connected to this nmos pass transistor 410 is to be coupled to a pulse signal (CLK).
Wherein, this active load master circuit 400 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 401 to promoting circuit, and this PMOS transistor 402 and this PMOS transistor 403 are the left side for example in a side, and comprise this resistance 404, and this PMOS transistor 405 and this PMOS transistor 406 also are the right side in opposite side.This left side drags down circuit to be made up of this resistance 407 and this nmos pass transistor 408, is made up of this resistance 409 and this nmos pass transistor 410 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 402 and this PMOS transistor 405 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 402 for this PMOS transistor 405 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 408 this complementation pulse signal during for low level for closing and this nmos pass transistor 410 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of during surging is instantaneous; SET signal and SET1 signal voltage via these resistance 407 two ends are provided respectively are temporarily different; And RESET signal and RESET1 signal voltage via these resistance 409 two ends are provided respectively are also temporarily different, and the present invention utilizes these characteristics to create a design: just move when or this RESET signal identical with the SET1 signal voltage is identical with the RESET1 signal voltage at this SET signal with 103 of the latch units of its collocation.This measure can be guaranteed this latch unit 103 normal operations.Moreover, because of those SET, SET1, RESET, RESET1 signal all need not direct current to keep high levle,, only account for minimum area so this resistance 407 and this resistance 409 can be small resistor.
Please with reference to Fig. 4, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs; As shown in Figure 4, active load master circuit 400 of the present invention comprises a resistance 401, one PMOS transistors 402; One PMOS transistor, 403, one resistance, 404, one PMOS transistors 405; One PMOS transistor, 406, one resistance, 407, one nmos pass transistors 408; One resistance 409, and a nmos pass transistor 410.The grid of this PMOS transistor 402 be the drain electrode of grid and this PMOS transistor 406 of the grid that is connected to this nmos pass transistor 408, this PMOS transistor 403 being coupled to a complementary pulse signal, and the drain electrode of grid and this PMOS transistor 403 of grid, this PMOS transistor 406 that the grid of this PMOS transistor 405 is connected to this nmos pass transistor 410 is to be coupled to a pulse signal.
Wherein, this active load master circuit 400 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 401 to promoting circuit, and this PMOS transistor 402 and this PMOS transistor 403 are the left side for example in a side, and comprise this resistance 404, and this PMOS transistor 405 and this PMOS transistor 406 also are the right side in opposite side.This left side drags down circuit to be made up of this resistance 407 and this nmos pass transistor 408, is made up of this resistance 409 and this nmos pass transistor 410 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 402 and this PMOS transistor 405 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 402 for this PMOS transistor 405 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 408 this complementation pulse signal during for low level for closing and this nmos pass transistor 410 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of the SET signal that provided via these resistance 407 upper ends with via the RESET signal that these resistance 409 upper ends are provided is that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Fig. 5, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates another preferred embodiment of the present invention disturbs; As shown in Figure 5, active load master circuit 400 of the present invention comprises a resistance 401, one PMOS transistors 402; One PMOS transistor, 403, one resistance, 404, one PMOS transistors 405; One PMOS transistor, 406, one resistance, 407, one nmos pass transistors 408; One resistance 409, and a nmos pass transistor 410.The grid of this PMOS transistor 402 be the drain electrode of grid and this PMOS transistor 406 of the grid that is connected to this nmos pass transistor 408, this PMOS transistor 403 being coupled to a complementary pulse signal, and the drain electrode of grid and this PMOS transistor 403 of grid, this PMOS transistor 406 that the grid of this PMOS transistor 405 is connected to this nmos pass transistor 410 is to be coupled to a pulse signal.
Wherein, this active load master circuit 400 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 401 to promoting circuit, and this PMOS transistor 402 and this PMOS transistor 403 are the left side for example in a side, and comprise this resistance 404, and this PMOS transistor 405 and this PMOS transistor 406 also are the right side in opposite side.This left side drags down circuit to be made up of this resistance 407 and this nmos pass transistor 408, is made up of this resistance 409 and this nmos pass transistor 410 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 402 and this PMOS transistor 405 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 402 for this PMOS transistor 405 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 408 this complementation pulse signal during for low level for closing and this nmos pass transistor 410 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of the SET signal that provided via these resistance 407 lower ends with via the RESET signal that these resistance 409 lower ends are provided is that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Fig. 6, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; As shown in Figure 6, active load master circuit 500 of the present invention comprises a resistance 501, one PMOS transistors 502, one resistance 503, one PMOS transistors 504, one resistance 505, one nmos pass transistors 506, one resistance 507, and a nmos pass transistor 508.The grid of this PMOS transistor 502 be the source electrode of the grid that is connected to this nmos pass transistor 506 and this PMOS transistor 504 being coupled to a complementary pulse signal, and the source electrode of grid and this PMOS transistor 502 that the grid of this PMOS transistor 504 is connected to this nmos pass transistor 508 is to be coupled to a complementary pulse signal.
Wherein, this active load master circuit 500 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises that to promoting circuit this resistance 501 and this PMOS transistor 502 in a side, are the left side for example, and comprises that this resistance 503 and this PMOS transistor 504 in opposite side, also are the right side.This left side drags down circuit to be made up of this resistance 505 and this nmos pass transistor 506, is made up of this resistance 507 and this nmos pass transistor 508 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 502 and this PMOS transistor 504 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 502 for this PMOS transistor 504 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 506 this complementation pulse signal during for low level for closing and this nmos pass transistor 508 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of during surging is instantaneous; SET signal and SET1 signal voltage via these resistance 505 two ends are provided respectively are temporarily different; And RESET signal and RESET1 signal voltage via these resistance 507 two ends are provided respectively are also temporarily different, and the present invention utilizes these characteristics to create a design: just move when or this RESET signal identical with the SET1 signal voltage is identical with the RESET1 signal voltage at this SET signal with 103 of the latch units of its collocation.This measure can be guaranteed this latch unit normal operation.
Please with reference to Fig. 7, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; As shown in Figure 7, active load master circuit 500 of the present invention comprises a resistance 501, one PMOS transistors 502, one resistance 503 ,-PMOS transistor 504, one resistance 505, one nmos pass transistors 506, one resistance 507, and a nmos pass transistor 508.The grid of this PMOS transistor 502 be the source electrode of the grid that is connected to this nmos pass transistor 506 and this PMOS transistor 504 being coupled to a complementary pulse signal, and the source electrode of grid and this PMOS transistor 502 that the grid of this PMOS transistor 504 is connected to this nmos pass transistor 508 is to be coupled to a pulse signal.
Wherein, this active load master circuit 500 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises that to promoting circuit this resistance 501 and this PMOS transistor 502 in a side, are the left side for example, and comprises that this resistance 503 and this PMOS transistor 504 in opposite side, also are the right side.This left side drags down circuit to be made up of this resistance 505 and this nmos pass transistor 506, is made up of this resistance 507 and this nmos pass transistor 508 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 502 and this PMOS transistor 504 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 502 for this PMOS transistor 504 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 506 this complementation pulse signal during for low level for closing and this nmos pass transistor 508 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of the SET signal that provided via these resistance 505 upper ends with via the RESET signal that these resistance 507 upper ends are provided is that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Fig. 8, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; As shown in Figure 8, active load master circuit 500 of the present invention comprises a resistance 501, one PMOS transistors 502, one resistance 503, one PMOS transistors 504, one resistance 505, one nmos pass transistors 506, one resistance 507, and a nmos pass transistor 508.The grid of this PMOS transistor 502 be the source electrode of the grid that is connected to this nmos pass transistor 506 and this PMOS transistor 504 being coupled to a complementary pulse signal, and the source electrode of grid and this PMOS transistor 502 that the grid of this PMOS transistor 504 is connected to this nmos pass transistor 508 is to be coupled to a pulse signal.
Wherein, this active load master circuit 500 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises that to promoting circuit this resistance 501 and this PMOS transistor 502 in a side, are the left side for example, and comprises that this resistance 503 and this PMOS transistor 504 in opposite side, also are the right side.This left side drags down circuit to be made up of this resistance 505 and this nmos pass transistor 506, is made up of this resistance 507 and this nmos pass transistor 508 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 502 and this PMOS transistor 504 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 502 for this PMOS transistor 504 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 506 this complementation pulse signal during for low level for closing and this nmos pass transistor 508 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of the SET signal that provided via these resistance 505 lower ends with via the RESET signal that these resistance 507 lower ends are provided is that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Fig. 9, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; As shown in Figure 9, active load master circuit 600 of the present invention comprises a resistance 601, one PMOS transistors 602; One PMOS transistor, 603, one resistance, 604, one PMOS transistors 605; One PMOS transistor, 606, one nmos pass transistors 607, and a nmos pass transistor 608.The grid of this PMOS transistor 602 be the drain electrode of grid and this PMOS transistor 606 of the grid that is connected to this nmos pass transistor 607, this PMOS transistor 603 being coupled to a complementary pulse signal, and the drain electrode of grid and this PMOS transistor 603 of grid, this PMOS transistor 606 that the grid of this PMOS transistor 605 is connected to this nmos pass transistor 608 is to be coupled to a pulse signal.
Wherein, this active load master circuit 600 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 601 to promoting circuit, and this PMOS transistor 602 and this PMOS transistor 603 are the left side for example in a side, and comprise this resistance 604, and this PMOS transistor 605 and this PMOS transistor 606 also are the right side in opposite side.This left side drags down circuit to be made up of this nmos pass transistor 607, is made up of this nmos pass transistor 608 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 602 and this PMOS transistor 605 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 602 for this PMOS transistor 605 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 607 this complementation pulse signal during for low level for closing and this nmos pass transistor 608 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of being that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively via the SET signal that drain electrode provided of this nmos pass transistor 607 with via the RESET signal that drain electrode provided of this nmos pass transistor 608; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Figure 10, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; Shown in figure 10, active load master circuit 700 of the present invention comprises a resistance 701, one PMOS transistors 702, one resistance 703, one PMOS transistors 704, one nmos pass transistors 705, and a nmos pass transistor 706.The grid of this PMOS transistor 702 be the source electrode of the grid that is connected to this nmos pass transistor 705 and this PMOS transistor 704 being coupled to a complementary pulse signal, and the source electrode of grid and this PMOS transistor 702 that the grid of this PMOS transistor 704 is connected to this nmos pass transistor 706 is to be coupled to a pulse signal.
Wherein, this active load master circuit 700 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises that to promoting circuit this resistance 701 and this PMOS transistor 702 in a side, are the left side for example, and comprises that this resistance 703 and this PMOS transistor 704 in opposite side, also are the right side.This left side drags down circuit to be made up of this nmos pass transistor 705, is made up of this nmos pass transistor 706 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 702 and this PMOS transistor 704 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 702 for this PMOS transistor 704 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 705 this complementation pulse signal during for low level for closing and this nmos pass transistor 706 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of being that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively via the SET signal that drain electrode provided of this nmos pass transistor 705 with via the RESET signal that drain electrode provided of this nmos pass transistor 706; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Figure 11, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; Shown in figure 11, active load master circuit 800 of the present invention comprises a resistance 801, one PMOS transistors 802; One PMOS transistor, 803, one resistance, 804, one PMOS transistors 805; One PMOS transistor, 806, one nmos pass transistors, 807, one resistance 808; One nmos pass transistor 809, and a resistance 810.The grid of this PMOS transistor 802 be the drain electrode of grid and this PMOS transistor 806 of the grid that is connected to this nmos pass transistor 807, this PMOS transistor 803 being coupled to a complementary pulse signal, and the drain electrode of grid and this PMOS transistor 803 of grid, this PMOS transistor 806 that the grid of this PMOS transistor 805 is connected to this nmos pass transistor 809 is to be coupled to a pulse signal.
Wherein, this active load master circuit 800 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises this resistance 801 to promoting circuit, and this PMOS transistor 802 and this PMOS transistor 803 are the left side for example in a side, and comprise this resistance 804, and this PMOS transistor 805 and this PMOS transistor 806 also are the right side in opposite side.This left side drags down circuit to be made up of this nmos pass transistor 807 and this resistance 808, is made up of this nmos pass transistor 809 and this resistance 810 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 802 and this PMOS transistor 805 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 802 for this PMOS transistor 805 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 807 this complementation pulse signal during for low level for closing and this nmos pass transistor 809 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of being that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively via the SET signal that drain electrode provided of this nmos pass transistor 807 with via the RESET signal that drain electrode provided of this nmos pass transistor 809; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
Please with reference to Figure 12, the circuit diagram of the active load master circuit that its common mode surge eliminated that illustrates the present invention's one preferred embodiment disturbs; Shown in figure 12, active load master circuit 900 of the present invention comprises a resistance 901, one PMOS transistors 902, one resistance 903, one PMOS transistors 904, one nmos pass transistors 905, one resistance 906, one nmos pass transistors 907, and a resistance 908.The grid of this PMOS transistor 902 be the source electrode of the grid that is connected to this nmos pass transistor 905 and this PMOS transistor 904 being coupled to a complementary pulse signal, and the source electrode of grid and this PMOS transistor 902 that the grid of this PMOS transistor 904 is connected to this nmos pass transistor 907 is to be coupled to a pulse signal.
Wherein, this active load master circuit 900 comprises a pair of lifting circuit and a pair of circuit that drags down.This comprises that to promoting circuit this resistance 901 and this PMOS transistor 902 in a side, are the left side for example, and comprises that this resistance 903 and this PMOS transistor 904 in opposite side, also are the right side.This left side drags down circuit to be made up of this nmos pass transistor 905 and this resistance 906, is made up of this nmos pass transistor 907 and this resistance 908 and this right side drags down circuit.
Because the effect of symmetrical structure, when a surging resulted from those power supplys, the grid of this PMOS transistor 902 and this PMOS transistor 904 and source voltage can change simultaneously and the voltage difference of this two electrode is remained unchanged.If this pulse signal be high levle and should the complementation pulse signal be low level cause this PMOS transistor 902 for this PMOS transistor 904 of conducting for closing, then those logical resistance states will remain unchanged.Again because this nmos pass transistor 905 this complementation pulse signal during for low level for closing and this nmos pass transistor 907 is conducting at this pulse signal during for high levle, so the left and right sides has any direct current guiding path existence.
In addition; Because of being that mutual exclusion ground is connected to VBOOT and HBOUT via promoting circuit and dragging down circuit respectively via the SET signal that drain electrode provided of this nmos pass transistor 905 with via the RESET signal that drain electrode provided of this nmos pass transistor 907; So the present invention can provide enough big voltage swing with driving latch unit 103; Thereby relaxed the design specification of latch unit 103, latch unit 103 is realized easily.
So; Via enforcement of the present invention, make this drag down circuit and comprise at least one active member, a strong pulsed filter can be provided; The big voltage swing of its tool, minimum power consumption, smallest chip area and loose advantages such as latch unit design specification really can be improved all shortcomings of known pulsed filter.
Disclosed, be preferred embodiment, the change of every part or modification and come from technological thought of the present invention and be have the knack of this technology the people was easy to know by inference, all do not take off claim category of the present invention.
Claims (8)
1. an active load master circuit that disturbs in order to the elimination common mode surge is biased between one first voltage and one second voltage, and it has:
A pair of lifting circuit provides the path that is connected with this first voltage in order to react on a pulse signal or a complementary pulse signal; And
Pair of active load circuits; Place this to promoting between circuit and this second voltage; In order to produce at least one SET signal and at least one RESET signal to drive a latch unit; Wherein this left side to the active load circuits internal structure, right side respectively have at least one active member, to react on this pulse signal or should the complementation pulse signal and the path that is connected with this second voltage is provided; Wherein this has one first resistance and one the one PMOS transistor to the left side that promotes circuit inner structure, and this first resistance is to be series at a PMOS transistor; This has one second resistance and one the 2nd PMOS transistor to the right side that promotes circuit inner structure, and this second resistance is to be series at the 2nd PMOS transistor.
2. as claimed in claim 1 in order to eliminate the active load master circuit that common mode surge disturbs; Wherein this left side to the active load circuits internal structure has one the 3rd resistance and one first nmos pass transistor, and the 3rd resistance is that an end that is series at this first nmos pass transistor and the 3rd resistance is in order to said SET signal to be provided; This right side to the active load circuits internal structure has one the 4th resistance and one second nmos pass transistor, and the 4th resistance is that an end that is series at this second nmos pass transistor and the 4th resistance is in order to said RESET signal to be provided.
3. as claimed in claim 1 in order to eliminate the active load master circuit that common mode surge disturbs; Wherein this left side to the active load circuits internal structure has one the 3rd resistance and one first nmos pass transistor, and the 3rd resistance is to be series at this first nmos pass transistor; This right side to the active load circuits internal structure has one the 4th resistance and one second nmos pass transistor, and the 4th resistance is to be series at this second nmos pass transistor.
4. as claimed in claim 2 it further provides another SET signal by the other end of the 3rd resistance in order to eliminate the active load master circuit that common mode surge disturbs, and by the other end of the 4th resistance another RESET signal is provided.
5. as claimed in claim 3 in order to eliminate the active load master circuit that common mode surge disturbs, wherein the drain electrode of this first nmos pass transistor is in order to said SET signal to be provided, and the drain electrode of this second nmos pass transistor is in order to said RESET signal to be provided.
6. as claimed in claim 1 in order to eliminate the active load master circuit that common mode surge disturbs; Wherein this left side to the active load circuits internal structure has one the 3rd resistance and one first nmos pass transistor, and the 3rd resistance is that an end that is series at this first nmos pass transistor and the 3rd resistance is in order to said SET signal to be provided; This right side to the active load circuits internal structure has one the 4th resistance and one second nmos pass transistor, and the 4th resistance is that an end that is series at this second nmos pass transistor and the 4th resistance is in order to said RESET signal to be provided; And should the complementation pulse signal be the grid that is coupled to the transistorized grid of a PMOS, the transistorized source electrode of the 2nd PMOS and this first nmos pass transistor wherein, and this pulse signal is grid and the transistorized source electrode of a PMOS that is coupled to the transistorized grid of the 2nd PMOS, this second nmos pass transistor.
7. as claimed in claim 1 in order to eliminate the active load master circuit that common mode surge disturbs; Wherein this left side to the active load circuits internal structure has one the 3rd resistance and one first nmos pass transistor, and the 3rd resistance is to be series at this first nmos pass transistor; This right side to the active load circuits internal structure has one the 4th resistance and one second nmos pass transistor, and the 4th resistance is to be series at this second nmos pass transistor; And should the complementation pulse signal be the grid that is coupled to the transistorized grid of a PMOS, the transistorized source electrode of the 2nd PMOS and this first nmos pass transistor wherein, and this pulse signal is grid and the transistorized source electrode of a PMOS that is coupled to the transistorized grid of the 2nd PMOS, this second nmos pass transistor.
8. an active load master circuit that disturbs in order to the elimination common mode surge is biased between one first voltage and one second voltage, and it has:
A pair of lifting circuit provides the path that is connected with this first voltage in order to react on a pulse signal or a complementary pulse signal; And
Pair of active load circuits; Place this to promoting between circuit and this second voltage; In order to produce at least one SET signal and at least one RESET signal to drive a latch unit; Wherein this left side to the active load circuits internal structure, right side respectively have at least one active member, to react on this pulse signal or should the complementation pulse signal and the path that is connected with this second voltage is provided; Wherein this has one first resistance, one the one PMOS transistor and one the 2nd PMOS transistor to the left side that promotes circuit inner structure, this first resistance be parallel to a PMOS transistor and with the 2nd PMOS transistor series; This has one second resistance, one the 3rd PMOS transistor and one the 4th PMOS transistor to the right side that promotes circuit inner structure, this second resistance be parallel to the 3rd PMOS transistor and with the 4th PMOS transistor series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810173899A CN101741228B (en) | 2008-11-21 | 2008-11-21 | Active load master circuit for eliminating common mode surge interference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810173899A CN101741228B (en) | 2008-11-21 | 2008-11-21 | Active load master circuit for eliminating common mode surge interference |
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| CN101741228A CN101741228A (en) | 2010-06-16 |
| CN101741228B true CN101741228B (en) | 2012-09-19 |
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| CN200810173899A Active CN101741228B (en) | 2008-11-21 | 2008-11-21 | Active load master circuit for eliminating common mode surge interference |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572156A (en) * | 1994-09-16 | 1996-11-05 | Sgs-Thomson Microelectronics S.R.L. | Control circuit with a level shifter for switching an electronic switch |
| US5742196A (en) * | 1995-04-10 | 1998-04-21 | U.S. Philips Corporation | Level-shifting circuit and high-side driver including such a level-shifting circuit |
| CN1630929A (en) * | 2000-04-04 | 2005-06-22 | 皇家菲利浦电子有限公司 | A low cost half bridge driver integrated circuit |
-
2008
- 2008-11-21 CN CN200810173899A patent/CN101741228B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5572156A (en) * | 1994-09-16 | 1996-11-05 | Sgs-Thomson Microelectronics S.R.L. | Control circuit with a level shifter for switching an electronic switch |
| US5742196A (en) * | 1995-04-10 | 1998-04-21 | U.S. Philips Corporation | Level-shifting circuit and high-side driver including such a level-shifting circuit |
| CN1630929A (en) * | 2000-04-04 | 2005-06-22 | 皇家菲利浦电子有限公司 | A low cost half bridge driver integrated circuit |
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| CN101741228A (en) | 2010-06-16 |
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Denomination of invention: Active load master circuit for eliminating common mode surge interference Effective date of registration: 20190625 Granted publication date: 20120919 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd Pledgor: Nanjing green core integrated circuit Co., Ltd. Registration number: 2019320000297 |
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Date of cancellation: 20200617 Granted publication date: 20120919 Pledgee: Bank of Nanjing Jiangbei District branch of Limited by Share Ltd. Pledgor: NANJING GREENCHIP SEMICONDUCTOR Co.,Ltd. Registration number: 2019320000297 |