CN101785101B - 微电子封装元件及其制备方法 - Google Patents

微电子封装元件及其制备方法 Download PDF

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CN101785101B
CN101785101B CN2008801038066A CN200880103806A CN101785101B CN 101785101 B CN101785101 B CN 101785101B CN 2008801038066 A CN2008801038066 A CN 2008801038066A CN 200880103806 A CN200880103806 A CN 200880103806A CN 101785101 B CN101785101 B CN 101785101B
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contact
contacts
top surface
dielectric material
exposed
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CN101785101A (zh
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B·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

本申请公开了具有介电层(220)的微电子封装元件(202)和封装(280)，以及制备该元件(202)和封装(280)的方法。所述元件(202)和封装(280)可有利地用于具有高布线密度的微电子组件中。

Description

微电子封装元件及其制备方法
交叉引用
本申请要求享有在2007年7月12日提交的申请号为11/827,676，名称为“微电子封装元件及其制备方法”的申请的权益，其公开内容在此以引用的方式并入本申请中。
技术领域
本发明总体涉及微电子封装，并且特别涉及封装微电子元件的方法和制备微电子封装中使用的封装元件的方法。
背景技术
微电子封装或封装元件(如基板)在电子组件中广泛使用。典型的封装和封装元件通常包括介电材料片或板形式的介电材料，其具有大量在片或板上延伸的导电迹线。所述迹线可设在一个层或多个层中，并由介电材料层隔开。所述封装或封装元件还可以包括导电元件，如延伸穿过介电材料层以对不同层中的迹线进行互连的通孔衬套(liner)。在一些情况中，将电路面板作为微电子封装的元件使用。
微电子封装通常包括具有一个或多个微电子器件的一个或多个基板，所述微电子器件例如安装在该基板上的一个或多个半导体芯片。基板的导电元件可以包括用于与较大的基板或电路面板进行电连接的导电迹线和端子，由此便于获得所期望的器件功能所需要的电连接。芯片可以与迹线电连接，并因此与端子连接，以使所述封装可通过将端子与较大的电路面板上的接触焊盘接合而安装至较大的电路面板。例如，一些用于微电子封装的基板具有从介电元件延伸的引脚或触点形式的端子。
尽管迄今本领域已投入了相当大的努力以开发微电子封装和封装元件及制备这种器件的方法，但仍然需要进一步的改进。
发明内容
本发明的一个方面是制备封装元件的方法。封装元件可以具有顶部表面和远离顶部表面的底部表面。所述封装元件可以通过将金属片变形形成多个空心触点而形成。所述空心触点可以包括朝上的第一触点，所述第一触点暴露在所述顶部表面处，以及多个朝下的第二触点，所述第二触点暴露在底部表面处并可与所述第一触点连接。所述第一和第二触点中的一些触点可以与所述第一和第二触点中的其他触点电绝缘。可在所述第一和第二触点中的一些或所有触点之间的空间内涂布介电材料。所述第一触点中的一些触点可以暴露在顶部表面处，并且所述第二触点中的一些触点可以暴露在底部表面处。
本发明的另一方面是封装微电子元件的方法。所述微电子元件可以通过形成封装元件来进行封装。所述封装元件可以具有顶部表面和远离顶部表面的底部表面。可以通过将金属片变形形成多个空心触点而形成所述封装元件。所述空心触点可以包括朝上的第一触点，所述第一触点暴露在所述顶部表面处，以及多个朝下的第二触点，所述第二触点暴露在所述底部表面处并可与所述第一触点连接。所述第一和第二触点中的一些触点可以与所述第一和第二触点中的其他触点电绝缘。可在所述第一和第二触点中的一些或所有触点之间的空间内涂布介电材料。所述第一触点中的一些触点可以暴露在顶部表面处，并且所述第二触点中的一些触点可以暴露在底部表面处。微电子元件可以安装在所述封装元件的顶部表面，并且可以将所述微电子元件与所述第一触点或所述第二触点中的至少一个触点相互电连接。
在本发明的另一方面中，封装元件具有顶部表面和远离顶部表面的底部表面。所述封装元件可包括具有多个空心触点的变形的金属片。所述空心触点可以包括朝上的第一触点，以及多个朝下的第二触点，所述第二触点可与所述第一触点连接。所述第一和第二触点中的一些触点可以与所述第一和第二触点中的其他触点电绝缘。可在所述第一和第二触点中的一些或所有触点之间的空间内布置介电材料。所述第一触点中的一些触点可以暴露在顶部表面处，并且所述第二触点中的一些触点可以暴露在底部表面处。
在本发明的另一方面中，经封装的微电子元件包含封装元件。封装元件具有顶部表面和远离顶部表面的底部表面。所述封装元件可包括具有多个空心触点的变形的金属片。所述空心触点可以包括朝上的第一触点，以及多个朝下的第二触点，所述第二触点可与所述第一触点连接。所述第一和第二触点中的一些触点可以与所述第一和第二触点中的其他触点电绝缘。可在所述第一和第二触点中的一些或所有触点之间的空间内布置介电材料。所述第一触点中的一些触点可以暴露在顶部表面处，并且所述第二触点中的一些触点可以暴露在底部表面处。微电子元件可以安装在所述封装元件的顶部表面，并且可以与所述第一触点或所述第二触点中的至少一个触点进行相互电连接。
上述发明内容既不意味也不应该被理解为代表本发明的全部内容和范围，从发明详述部分中，特别是当结合附图时，本发明的其他方面将变得更明显。
附图说明
图1是说明根据本发明的一个实施方案的方法的流程图；
图2A-2D是在图1方法的制备步骤中，金属片部分的平面图(图2A、2D)和截面图(图2B、2C)；
图3A-3B是在根据本发明的实施方案的方法的后续步骤期间所制备的微电子元件部分的示意性截面图；
图4A-4C是根据本发明的实施方案的方法的后续步骤期间所制备的微电子元件部分的示意性截面图和平面图(图4C)；
图5是根据本发明的实施方案的方法的后续步骤期间所制备的微电子元件部分的示意图；
图6A-6B是根据本发明的实施方案的方法的后续步骤期间所制备的微电子元件部分的截面图和平面图；以及
图7A-7D是根据本发明的另外实施方案制备的微电子封装的部分的示意性截面图。
在此，在可能的情况下，使用相同的附图标记来表示各图中共有的相同元件。为了举例说明的目的而简化这些附图中的图像，且这些图像不是按比例绘制的。
附图显示本发明的示例性实施方案，因此不能认为是对本发明的范围的限制，本发明的范围也包括其他效果相同的实施方案。
发明详述
图1示出了根据本发明的一个实施方案制备封装元件的方法100的流程图。所述方法100包括在微电子元件封装期间进行的处理步骤。在一些实施方案中，这些处理步骤以所描绘的次序进行。在可选的实施方案中，这些步骤中的至少两个步骤可同时进行或以不同的次序进行。尽管在图1中没有示出，可以在图1中描绘的步骤之间(例如在封装过程中)进行例如子步骤和辅助步骤(如在处理反应器间的转移、清洗子步骤、过程控制子步骤等)。附图中的截面图任意地沿使用方法100制备的微电子封装的金属片的中心线A-A(仅在图2A中示出)取得。
在根据本发明的一个实施方案的方法的步骤104中，提供了导电金属片200。金属片200具有周边202(图2A-2B)。理想地，所述片200主要由金属组成。所述片200的厚度204通常选自约5至75μm的范围。所述金属片主要由铜组成，并且可以包括铜合金(如铜和锌、铜和锡、铜和铝、铜和硅、铜和镍和/或铜和银的合金)，并且包括但不限于黄铜、磷青铜、铝青铜和硅青铜。也可以使用主要由铝或铝合金组成的金属片。
在步骤106中，通过将片200变形而形成多个空心触点210(图2C)。形成朝上的第一触点210A，其暴露在顶部表面210B处。多个朝下的第二触点210C暴露在底部表面210D处。所述第一触点210A和第二触点210C通过在所述变形过程中产生的金属壁205连接。以箭头206指示的触点210的宽度通常在约100至1000μm的范围内选择，如200至300μm。触点210A、210C可以在以箭头207指示的厚度上基本均匀。在图2D的平面图中显示了触点210A和210C的示例性排布。
在步骤106中，触点210通过使用冲压操作来使片200变形而形成。所述冲压操作可以包括对片200施加热和/或压力，任选地，如图3A和3B所示，将所述片200在第一压模212和第二压模214之间挤压，以产生变形的金属片201。可使用多个压模对片200进行变形，以形成空心触点210。
第一压模212是具有突出部216和凹陷部218的阳模，第二压模214是具有互补的突出部221和凹陷部222的阴模，以形成空心触点210。将压模212、214固定于压力机(未示出)，如液压金属冲压机，其在多种方法中都可使用。
压模212在箭头218的方向向上和向下运动(图3B)，从而将金属片200变形，以形成多个空心触点210。可将所述金属片200在一个或多个压力机行程下变形为最终的构造201。本领域技术人员已知获得元件201最佳形状所需的冲压参数，如基本上均匀的壁厚度和最小废品率。
还应该理解，在其他因素中，取决于金属片200的尺寸、所述压模的尺寸、冲压设备的容量、生产需求和经济规模，可将所公开的冲压处理用于形成一个封装元件，或者同时形成多个封装元件。
形成所述触点210的位置便于正在制备中的微电子元件的电路元件之间的连接。这样的触点可以具有不同的形状因子，并且可将其安排在例如间距在100至10000μm范围内的一个或多个栅格状图案中。
在所述方法的下一个阶段中，在步骤108，将介电层220涂布于元件201(图4A-4B)。在触点210之间引入可流动的组合物以形成介电层。所述组合物可包括多种介电或介电形成材料，例如但不限于热塑性和热固性材料、环氧化物、液晶聚合物(LCP)和聚酰亚胺。介电材料的选择将取决于所述涂布方法和对特殊应用的介电要求。
例如，可使用通过化学反应固化以形成聚合介电材料(如环氧化物和聚酰亚胺)的组合物。在其他情况中，所述可流动的组合物可以是在高温下变为可流动的、并且通过冷却可固化为固体状态的组合物。
介电层220可以与变形片201的部分形成界面。所述介电材料还可包括一种或多种影响所述介电层220性质的添加剂。例如，这样的添加剂可包括颗粒材料如二氧化硅或其他的无机介电材料，或纤维状增强物如短玻璃纤维，以增大所述材料的强度、粘合和/或介电性质。
可使用注射成型方法来涂布所述介电材料。在注射成型方法中，变形金属片201夹于压力板222、配合元件(counter element)226(以虚线表示)以及成型工具230(图4B)之间。配合元件226紧靠触点210的底部表面210D，并且将所述可流动的组合物注入或以其他方式提供或引入变形金属片200和配合元件226之间的空间内。
在图4B中示出的具体实施方案中，通过至少一个在配合元件226中的开口或门(gate)227注入所述介电材料(如图所示)。其后，将压力平板222、配合元件226和成型工具230移去(图4A)。一般地，在成型步骤完成时，触点210的表面210D、210B无成型组合物。在一些情况中，成型组合物的薄膜可覆盖所述触点中的一些或所有触点的底部表面210D或顶部表面210B。如果发生这样的情况，可通过将所述已成型介电层的表面暴露于短暂的等离子体蚀刻或灰化过程来去除所述薄膜，所述过程腐蚀所述已成型介电材料，并因此提供洁净、无介电材料的接触表面。
如图4C中所示，金属片200可以是包括多个片200的较大的框架246的一部分。在该实施方案中，成型工具的压力板和配合元件在框架246上延伸，并且可以通过多个定位部件(registration features)244与所述框架定位。在所述成型过程中，将成型组合物通过单独的门引入变形片201和配合元件之间的空间中，所述单独的门可流动地联接到成型工具的流道系统(runner system)(未示出)。在成型过程一完成就将压力板和配合元件移除之后，可从框架上将变形片201分离(例如切开)。这样的分离也可在下述的步骤110后进行。
可选地，可通过模版(stencil)或丝网(screen)在触点210之间的空间中引入流体介质材料以形成介电层220而涂布介电材料220。如图5所示，具有材料可流过的开口区域254和防止材料流动的固体区域258的模版或掩膜材料250可被涂布于变形金属片201的顶部表面或底部表面中的一个或两个表面。可通过使用常规材料和熟知的光刻技术制备所述模版或掩膜。在箭头266方向拉动柔性涂布器(flexible applicator)(如涂刷器262)，以将介电材料220涂布在如上在图4A-B中示出的所述第一和第二触点中至少一些触点之间的空间内。
可手工或通过使用自动化方法来涂布介电材料220，以便例如控制过程参数，例如涂布压力、分配的介电材料的量和速率、涂布器的停留时间以及过程温度。在丝网或模版印刷的情况中，一些介电材料可能不需要在压力下进行涂布。
可在一个或多个步骤中进行介电材料的涂布。当希望掩蔽某些区域以防止所述介电材料的沉积时，可使用模版，同样地，可使用丝网或筛网材料以使受控量的介电材料以任意希望的几何图案流入所述第一和第二触点中至少一些触点之间的空间内。
可采用其他常用方法涂布介电材料，如旋压成形(spin-forming)可流动的介电材料或将介电片材料层压至如前面图4A-B中示出的所述第一和第二触点之间的空间内。不管使用何种涂布方法，可采用如上所述清理技术以从所述触点上去除多余的介电材料。
根据前述内容，介电层219具有主表面214，其可任选地与底触点210C的暴露面210D(图4A-B)共面。介电层219也具有顶部表面218，其可任选地填充上触点210C下方的全部空间。
在步骤110中，可通过以下的方法来限定金属片中的迹线：以光刻方式限定覆盖变形金属片201的掩膜层，并根据所述掩膜层蚀刻所述变形金属片，以使如图6A-B所示的第一触点210A和第二触点210C与其他的第一和第二触点210A、210C电绝缘。可使用任何适合的金属去除技术或方法。
触点210A、210C在封装元件202中电连接在一起(图6A)。各个触点210A、210C可与另一触点连接。但是，一些触点可能“悬空(float)”，即不与其他触点电连接。
如图6A-B所示，至少一个触点210F可以是外围触点，其具有闭合环路图案，并且围绕至少一些触点，如图6A-B中所示。在所述实施方案中，作为外围触点的外围触点210F还可以包括接触区域210E，其宽度比所述触点的其他部分的宽度小。在操作中，所述外围触点可减少相同或相邻器件上的电路间的电磁干扰(EMI)。
迹线230可以具有不同的宽度，包括比触点210的宽度更小或更大的宽度，因此便于制备具有高布线密度(routing density)的微电子封装。一般而言，迹线230的宽度选自约5至100μm(如20-40μm)的范围，但是，迹线的部分或一些迹线可具有大于100μm的宽度。
如在图7A中所示，可通过粘合剂248将微电子元件(如半导体芯片240)安装在封装元件202上，并且可通过接合线244将微电子元件连接至导电触点以形成封装。
可选地，如图7B所示，封装元件202可以包括热导体260，其具有暴露在顶部表面264处的顶部，至少一个暴露在底部表面268处的底面，以及在顶部和底部之间延伸的壁272。可通过基本上如上所讨论的方法制备这样的封装元件。
所述封装元件可包括在变形金属片201的一个或多个区域中的一个或多个热导体。所述热导体可用在任何地方，但在芯片上安装了高功率和/或高密度部件的地方，特别可用于散热。由于散热能力增强，该特征可有助于高密度封装、高功耗芯片的封装和/或可靠性的提高。
如关于图7A所讨论的，用粘合剂248(如芯片粘接剂(die attach adhesive))将微电子元件(如半导体芯片240)安装至封装元件202，该粘合剂248可任选地置于空心空间中，该空心空间覆盖底触点210D并且通过接合线244与芯片的导电触点(未示出)电连接。可使用标准引线接合技术将触点210连接至芯片240。
可将微电子元件240安装并与所述封装元件互连以形成经封装的微电子元件。如图7C所示，用粘合剂248将微电子元件240(如半导体芯片)安装至封装元件202，粘合剂248任选地置于空心空间210中，该空心空间210覆盖底触点210D并且通过接合线246与芯片240的导电触点(未示出)电连接。在该实施方案中，通过标准引线接合方法，接合线246将芯片240的中部区域245与触点210C连接。
在图7D所示出的微电子封装280实施方案中，用粘合剂248将微电子元件(如半导体芯片240)安装至封装元件202，粘合剂248任选地置于空心空间210中，该空心空间210处于底触点210D之上并且通过焊球290与芯片240的导电触点(未示出)电连接。可使用在本工业领域中熟知的标准球焊技术。
可将上述组件互连以形成多组件封装，该多组件封装包含两个以上的组件或不同类型的组件。
尽管在此已经参考特定实施方案描述了本发明，但应该理解这些实施方案仅举例说明了本发明的原理和应用。因此，应该理解可对说明性实施方案进行许多修改，在不脱离所附权利要求所限定的本发明的精神和范围的情况下，可设计其他布置。

Claims (33)

1.制备封装元件的方法，所述封装元件具有顶部表面和远离所述顶部表面的底部表面，所述方法包括以下步骤：
(i)使金属片变形以形成多个空心触点，所述空心触点包括多个朝上的第一触点和多个朝下的第二触点，所述第一触点暴露在所述顶部表面处，所述第二触点暴露在所述底部表面处并与所述第一触点连接，所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘；并
(ii)在所述第一和第二触点中的至少一些触点之间的空间内涂布介电材料，所述第一触点暴露在所述顶部表面处，并且所述第二触点暴露在所述底部表面处。
2.根据权利要求1所述的方法，其中步骤(i)包括冲压所述金属片以形成所述多个空心触点。
3.根据权利要求1所述的方法，其中使所述金属片在第一压模和第二压模之间变形以形成所述多个空心触点。
4.根据权利要求1所述的方法，其还包括以光刻方式限定覆盖变形金属片的掩膜层，并且按照所述掩膜层蚀刻所述变形金属片，以使所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘。
5.根据权利要求1所述的方法，其中通过使介电材料流过模版或丝网中的至少一种来涂布所述介电材料。
6.根据权利要求1所述的方法，其中用旋涂方法来涂布所述介电材料。
7.根据权利要求1所述的方法，其中用注射成型方法来涂布所述介电材料。
8.根据权利要求1所述的方法，其中通过将介电片层压至所述顶部表面或底部表面中的至少一个表面上来涂布所述介电材料。
9.根据权利要求1所述的方法，其中所述金属片主要由铜组成。
10.根据权利要求1所述的方法，其中所述介电材料包括环氧化物。
11.封装微电子元件的方法，其包括以下步骤：
(a)形成具有顶部表面和远离所述顶部表面的底部表面的封装元件，所述封装元件通过以下步骤来成形：(i)使金属片变形以形成多个空心触点，所述空心触点包括多个朝上的第一触点和多个朝下的第二触点，所述第一触点暴露在所述顶部表面处，所述第二触点暴露在所述底部表面处并与所述第一触点连接，所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘；并(ii)在所述第一和第二触点中的至少一些触点之间的空间内涂布介电材料，所述第一触点暴露在所述顶部表面处，并且所述第二触点暴露在所述底部表面处，以及
(b)将微电子元件安装至所述封装元件的顶部表面，并且将所述微电子元件与所述第一触点或第二触点中的至少一个触点相互电连接。
12.根据权利要求11所述的方法，其中步骤(a)包括冲压所述金属片以形成所述多个空心触点。
13.根据权利要求11所述的方法，其中步骤(a)包括使所述金属片在第一压模和第二压模之间变形以形成所述多个空心触点。
14.根据权利要求11所述的方法，其中步骤(a)还包括以光刻方式限定覆盖所述变形金属片的掩膜层，并且按照所述掩膜层蚀刻所述变形金属片，以使所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘。
15.根据权利要求11所述的方法，其中通过使流体介电材料流过模版或丝网中的至少一种来涂布所述介电材料。
16.根据权利要求11所述的方法，其中用旋涂方法来涂布所述介电材料。
17.根据权利要求11所述的方法，其中用注射成型方法来涂布所述介电材料。
18.根据权利要求11所述的方法，其中通过将介电片材料层压至所述顶部表面或底部表面中的至少一个表面上来涂布所述介电材料。
19.根据权利要求11所述的方法，其中所述金属片主要由铜组成。
20.根据权利要求11所述的方法，其中所述介电材料包括环氧化物。
21.封装元件，其具有顶部表面和远离所述顶部表面的底部表面，所述封装元件包括：
(i)具有多个空心触点的变形金属片，所述空心触点包括多个朝上的第一触点，以及多个与所述第一触点连接的朝下的第二触点，所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘；以及
(ii)介电材料，其置于所述第一和第二触点中至少一些触点之间的空间中，其中所述第一触点暴露在所述顶部表面处，并且所述第二触点暴露在所述底部表面处。
22.根据权利要求21所述的封装元件，其中所述变形金属片包括连接所述第一触点与所述第二触点的壁，其中所述变形金属片在所述第一和第二触点以及所述壁具有均匀的厚度。
23.根据权利要求21所述的封装元件，其中所述介电材料包括至少一种选自环氧化物、液晶聚合物和聚酰亚胺的材料。
24.根据权利要求21所述的封装元件，其中所述变形金属片主要由铜组成。
25.根据权利要求21所述的封装元件，其中所述变形金属片还包括热导体，所述热导体具有暴露在所述顶部表面处的顶部、至少一个暴露在所述底部表面处的底面以及在所述顶部和底部之间延伸的壁。
26.根据权利要求25所述的封装元件，其中所述底面的面积大于任何一个所述第二触点的面积。
27.经封装的微电子元件，其包括：
(a)具有顶部表面和远离所述顶部表面的底部表面的封装元件，所述封装元件包括(i)具有多个空心触点的变形金属片，所述空心触点包括多个朝上的第一触点，以及多个与所述第一触点连接的朝下的第二触点，所述第一和第二触点中的至少一些触点与所述第一和第二触点中的其他触点电绝缘；以及(ii)介电材料，其置于所述第一和第二触点中至少一些触点之间的空间中，其中所述第一触点暴露在所述顶部表面处，并且所述第二触点暴露在所述底部表面处，以及
(b)微电子元件，其安装在所述封装元件顶部表面并且与所述第一触点或第二触点中的至少一个触点相互电连接。
28.根据权利要求27所述的经封装的微电子元件，其中所述变形金属片包括连接所述第一触点与所述第二触点的壁，其中所述变形金属片在所述第一和第二触点以及所述壁具有均匀的厚度。
29.根据权利要求27所述的经封装的微电子元件，其中所述介电材料包括至少一种选自环氧化物、液晶聚合物和聚酰亚胺的材料。
30.根据权利要求27所述的经封装的微电子元件，其中所述变形金属片主要由铜组成。
31.根据权利要求27所述的经封装的微电子元件，其中所述变形金属片还包括热导体，所述热导体具有暴露在所述顶部表面处的顶部、至少一个暴露在所述底部表面处的底面以及在所述顶部和底部之间延伸的壁。
32.根据权利要求31所述的经封装的微电子元件，其中所述底面的面积大于任何一个所述第二触点的面积。
33.根据权利要求31所述的经封装的微电子元件，其中所述底面与所述微电子元件对齐。
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US20090014861A1 (en) 2009-01-15
EP2176882A2 (en) 2010-04-21
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US7767497B2 (en) 2010-08-03
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