CN101796637B - 热增强的薄半导体封装件 - Google Patents
热增强的薄半导体封装件 Download PDFInfo
- Publication number
- CN101796637B CN101796637B CN200880105612XA CN200880105612A CN101796637B CN 101796637 B CN101796637 B CN 101796637B CN 200880105612X A CN200880105612X A CN 200880105612XA CN 200880105612 A CN200880105612 A CN 200880105612A CN 101796637 B CN101796637 B CN 101796637B
- Authority
- CN
- China
- Prior art keywords
- semiconductor chip
- lead frame
- chuck
- chip package
- moulding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/3754—Coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Abstract
披露一种半导体芯片封装件。该半导体芯片封装件包括半导体芯片,该半导体芯片具有位于第一半导体芯片顶表面的输入以及位于第二半导体芯片底表面的输出。具有第一引线框表面以及与第一引线框表面相对的第二引线框表面的引线框位于半导体芯片封装件中并联接于第一半导体芯片顶表面。具有第一夹头表面和第二夹头表面的夹头联接于第二半导体芯片底表面。具有外模制材料表面的模制材料覆盖引线框、夹头和半导体芯片的至少一部分。第一引线框表面和第一夹头表面由模制材料露出,而第一引线框表面、第一夹头表面和模制材料的外模制材料表面形成半导体芯片封装件的外表面。
Description
关联申请的交叉引用
无
背景
半导体芯片封装件是半导体业内公知的,但可予以改善。例如,诸如无线电话等电子设备正变得越来越小。希望制造出更薄的半导体芯片封装件以将其纳入这类电子设备中。还希望提高传统半导体芯片封装件的散热性。
存在的另一技术难题是这种半导体芯片封装件的形成。在示例性半导体芯片封装件中,夹头或引线框可夹住芯片。如果夹头和引线框不彼此正确对齐和与半导体芯片对齐,则制造出的半导体芯片封装件可能存在缺陷并且需要重制。
本发明的诸个实施例单独或集体地解决这些和其它的问题。
简单概述
本发明的实施例针对半导体芯片封装件、制造半导体芯片封装件的方法以及使用这种半导体芯片封装件的组合件和系统。
本发明的一个实施例针对一种半导体芯片封装件。该半导体芯片封装件包括半导体芯片,该半导体芯片具有位于第一半导体芯片顶表面的输入以及位于第二半导体芯片底表面的输出。具有第一引线框表面以及与第一引线框表面相对的第二引线框表面的引线框位于半导体芯片封装件中并联接于第一半导体芯片顶表面。具有第一夹头表面和第二夹头表面的夹头联接于第二半导体芯片底表面。具有外模制材料表面的模制材料覆盖引线框、夹头和半导体芯片的至少一部分。第一引线框表面和第一夹头表面通过模制材料露出,并且第一引线框表面、第一夹头表面和模制材料的外模制材料表面形成半导体芯片封装件的外表面。
本发明的另一实施例针对用于形成半导体芯片封装件的方法。该方法包括:获得半导体芯片,该半导体芯片具有位于第一半导体芯片顶表面的输入以及位于第二半导体芯片底表面的输出;并将具有第一引线框表面和与第一引线框表面相对的第二引线框表面附连于半导体芯片。第二引线框表面联接于第一半导体芯片顶表面。夹头附连于第二半导体芯片底表面。夹头具有第一夹头表面和第二夹头表面。模制材料模制在引线框、夹头和半导体芯片的至少一部分周围。在模制后,第一引线框表面和第一夹头表面通过模制材料露出。第一引线框表面、第一夹头表面和模制材料的外模制材料表面形成半导体芯片封装件的外表面。
本发明的这些和其它实施例在下文中予以进一步详细的说明。
附图简述
图1示出根据本发明一个实施例的半导体芯片封装件的俯视立体图。
图2示出图1所示半导体芯片封装件的仰视立体图。
图3示出根据本发明一个实施例的半导体芯片封装件的俯视立体图,其示出模制材料的轮廓。
图4示出根据本发明一个实施例的半导体芯片封装件的仰视立体图,其示出模制材料的轮廓。
图5示出根据本发明一个实施例的半导体芯片封装件的俯视立体图,其中一部分模制材料被去除。
图6示出根据本发明一个实施例的半导体芯片封装件的仰视立体图,其中一部分模制材料被去除。
图7示出根据本发明一个实施例的半导体芯片封装件的侧视横截面图。
图8示出根据本发明一个实施例的半导体芯片封装件的前视横截面图。
图9示出根据本发明一个实施例的半导体芯片封装件的分解图。
图10示出根据本发明一个实施例的半导体芯片封装件的俯视图。
图11示出附连于引线框的引线框结构的俯视立体图。
图12示出热漏极夹头的仰视立体图。
图13示出内引线框芯片粘连焊点区的仰视立体图。
图14示出具有粘连的热漏极夹头的经组装的引线框的立体仰视图。
图15是具有粘连的热漏极夹头的经组装的引线框的立体俯视图。
图16是模制后具有粘连的热漏极夹头的组装引线框的俯视立体图。
图17是模制后具有粘连的热漏极夹头的组装引线框的仰视立体图。
图18是本发明一个实施例在组装和模制后的侧视横截面图。
图19(a)和19(c)示出芯片焊接和布局。
图20(a)-(k)示出在形成时半导体芯片封装件的各个部分。
图21示出具有带沟道栅极的垂直MOSFET的半导体芯片。
在附图中,相同附图标记表示相同部件,并且在某些情形下对这些部件的描述不再予以重复。
详细说明
本发明的一个实施例针对半导体芯片封装件。半导体芯片封装件包括半导体芯片,该半导体芯片具有在第一半导体芯片顶表面的输入(例如源极区)以及在第二半导体芯片表面的输出(例如漏极区)。具有第一引线框表面和与第一引线框表面相对的第二引线框表面的引线框位于半导体芯片封装件中并联接于第一半导体芯片顶表面。具有第一夹头表面和第二夹头表面的夹头(例如漏极夹头)联接于第二半导体芯片底表面。具有外模制材料表面的模制材料覆盖引线框、夹头和半导体芯片中的至少一部分。第一引线框表面和第一夹头表面通过模制材料露出,并且第一引线框表面、第一夹头表面以及模制材料的外模制材料表面可形成半导体芯片封装件的外表面。
图1示出根据本发明一个实施例的半导体芯片封装件10的俯视立体图。半导体芯片封装件10包括含源极引线结构214(a)和栅极引线结构214(b)的引线框214。源极引线结构214(a)包括源极焊点14、露出的源极表面14(a)(它例如为第一引线框表面的至少一部分)以及源极引线12。引线框214还包括含栅极引线11的栅极引线结构。另外示出露出的热夹头15并且在下文中结合图2予以更详细的说明。模制材料13可形成在引线框214、夹头215以及位于引线框214和夹头215之间的半导体芯片(未示出)的至少一部分上。模制材料13可使用包括基于环氧树脂的模制材料的任何合用材料形成。如果需要,可在表面14(a)顶部设置散热件(未示出)以提高散热性。
如图1所示,半导体芯片封装件10的模制材料13的顶部外表面基本共面于并露出所暴露的源极焊点表面14(a)。源极引线12(以及栅极引线11)的延伸段在本例中通过模制材料13露出。因此,封装件的最高层表面可至少部分地通过露出的源极表面14(a)和模制材料13的顶部外表面来形成。这种特定结构导致具有良好散热性的非常薄的半导体芯片封装件。热量可通过栅极引线11、源极引线12和露出的热夹头15散发。
图2示出图1所示的半导体芯片封装件10的仰视图。如图所示,热夹头15的夹头底表面15(a)(其作为第一夹头表面的一个离子)可通过模制材料13露出。夹头底表面15(a)可基本与模制材料13的底表面共面。引线11、12的端部也可基本与夹头底表面15(a)共面以使半导体芯片封装件10安装在印刷电路板等。
在图2所示的实施例中,引线框11、12可从半导体芯片封装件10的一端伸出到模制材料之外,而夹头15的一部分可从半导体芯片封装件10的另一端伸出到模制材料13之外。因此,图2所示封装件10是带引线的封装件。然而在本发明的另一实施例中,可制造“无引线”封装件。无引线封装件可仍然包括引线,但它们根本不延伸过模制材料13的侧表面或仅延伸至任何可接受的程度。
图3是图1所示半导体芯片封装件的顶部立体图,其模制材料的轮廓由虚线表示。图4示出图1所示半导体芯片封装件的底部立体图,其模制材料的轮廓由虚线表示。图3和图4更清楚地示出包含栅极引线结果11和源极引线结构12的引线框。栅极引线结构11和源极引线结构彼此电绝缘。
半导体(例如硅)芯片32夹在引线框和热漏极夹头15之间。热漏极夹头15和引线框可电联接于半导体芯片封装件10中的半导体芯片32的输出区。
引线框214和热漏极夹头15可由任意合用的导电材料形成,例如铜、铝、贵金属及其合金。引线框和热漏极夹头15也可电镀以可焊接层(例如下部凸起的冶金层)。
根据本发明较佳实施例的用于半导体封装件的半导体芯片包括垂直功率晶体管。垂直功率晶体管包括VDMOS晶体管。VDMOS晶体管是具有通过扩散形成的两个或更多个半导体区的MOSFET。它具有源极区、漏极区和栅极区。该器件是垂直的,因为源极区和漏极区位于半导体芯片的相反表面上。栅极可以是沟道式栅极结构或平面栅极结构,并形成在与源极区相同的表面。沟道式栅极结构是较佳的,由于沟道式栅极结构相比平面式栅极结构更窄并占据更小的空间。工作时,在VDMOS器件中从源极区流向漏极区的电流基本垂直于芯片表面。包含带沟道式栅极的垂直MOSFET的半导体芯片800的一个示例示出于图21。可出现在半导体芯片中的其它器件可包括二极管、BHT(双极型结晶体管)以及其它类型的电子器件。
再次参见图3,可蚀去引线框214的一部分以使模制材料13锁定于引线框。如图3所示,栅极引线框11具有栅极焊点31和用于锁定的部分蚀刻区31(a)。源极引线结构214(a)具有带露出的源极焊点表面14(a)的露出源极焊点14。源极区14(a)也可由部分蚀去的区34界定以供模具锁定。源极焊点表面14(a)可以是从源极焊点14其它部分凸出的凸出区的一部分。
如图4所示,漏极夹头15也可部分地蚀去并具有部分蚀刻区311以使模制材料13锁定于漏极夹头15。漏极焊点表面15(a)可以是产生自源极区其它部分的凸起区的一部分。
可采用任意合用的蚀刻工艺蚀刻引线框和/或夹头15,并且蚀刻可发生在任何合适的深度。合用的蚀刻工艺可包括湿蚀或干蚀工艺。在一些实施例中,引线框可蚀去引线框厚度的大约一半。在这些情形下蚀刻后的引线框可特征化为半蚀刻。
图5示出模制材料13的一部分被蚀去的半导体芯片封装件10的顶部立体图。如图所示,模制材料13可覆盖形成引线框214的部分蚀去区31(a)、34的台肩,而不覆盖源极焊点表面14(a)。模制材料13的顶部外表面可基本与源极焊点表面14(a)共面。如图1所示,模制材料13可覆盖栅极焊点31的顶表面31(b)。然而在本发明其它实施例中,栅极焊点31的顶表面31(b)可露出。
图6示出半导体芯片封装件的仰视立体图,其中一部分模制材料13被去除。图6更清楚地示出夹头15的部分蚀刻区域311。模制材料13可覆盖部分蚀刻区311的表面,但不覆盖漏极表面15(a)。漏极表面15(a)可基本与模制材料13的底部外表面共面。如图所示,夹头15也可用侧向槽127来提高将模制材料13锁定于夹头15的能力。
图7是半导体芯片封装件的横截面图。图7更清楚地示出将半导体芯片32的第一表面32(a)联接于源极区14的焊料凸起76。焊膏99可接触焊料凸起76和源极焊点14。半导体芯片32也可包括联接于漏极夹头15的第二表面32(b)。焊料也可用来将漏极夹头15的第二表面15(b)联接于半导体芯片32的第二表面32(b)。模制材料13不覆盖源极焊点14的第一顶表面14(a)和夹头15的底表面,并进一步填充在部分蚀刻区311中以使模制材料13锁定于漏极夹头15。如图7所示,夹头15的底表面15(a)也基本与模制材料13的底表面共面。在本例中,源极引线12从半导体芯片封装件的一侧伸出,而漏极夹头15从半导体芯片封装件的另一侧伸出。
在本发明的一些实施例中,焊料凸起76和焊膏99可具有不同的熔点,并可使用任意合适的焊料,包括基于Pb的焊料和无铅焊料。例如导电环氧树脂的其它类型导电粘合剂也可用于将封装件10中的部件电气和机械联接在一起。
图8示出图7中的半导体芯片封装件10的前视横截面图。图8另行示出源极区14的部分蚀刻区34以及填充在部分蚀刻34中以提供模制锁定的模制材料13。
图9示出前述引线框214、模制材料13、半导体芯片32和夹头15的分解图。
图10示出半导体芯片封装件10的俯视图。
现在描述一种形成上述半导体芯片封装件的方法。在一个实施例中,该方法包括:获得半导体芯片,该半导体芯片具有位于第一半导体芯片顶表面的输入和位于第二半导体芯片底表面的输出;并将具有第一引线框表面和与第一引线框表面相对的第二引线框表面的引线框附连于半导体芯片。第二引线框表面联接于第一半导体芯片顶表面。具有第一夹头表面和第二夹头表面的夹头在半导体芯片附连于第二引线框表面之前或之后附连于半导体芯片。不管怎样,第二夹头表面联接于第二半导体芯片底表面,且模制材料模制在引线框、夹头和半导体芯片的至少一部分周围,其中在模制后,第一引线框表面和第一夹头表面通过模制材料露出,并且第一引线框表面、第一夹头表面和模制材料的外模制材料表面形成半导体芯片封装件的外表面。
引线框可取自任意合用的先驱结构,所述结构可通过任意合用工艺形成,包括压印、蚀刻或这些工艺的任意合适组合。图11示出根据本发明一个实施例的引线框先驱结构的俯视立体图。其包括在附连于引线框112的引线框先驱结构111的第一端处的基准平台113。引线框112可界定一引线框窗1111以供模制。基准平台(anvil)113的上表面可位于不同平面并相对于引线框112的上表面向下设置。水平狭槽1112平行于基准平台113以及水平狭槽1112的相对两端上的两垂直定位狭槽1113的方向。垂直狭槽1113可用于热漏极夹头钩定位。
引线框先驱结构1111还包括具有源极焊点14和整体源极引线12的源极引线结构以及具有栅极焊点31和整体栅极引线11的栅极引线结构,其在与第一端相对的第二端处通过连接杆118附连于引线框112。如前面附图所示,部分蚀刻区34、31(a)分别表示在源极焊点14和栅极焊点31中。
图12示出漏极夹头15的立体图。其包括漏极夹头表面15(a)和用于模制锁定的带狭槽区127以及在集成工艺中用于切割的卸荷狭槽126。其还包括从热夹头焊点124伸出的热夹头定位钩125。漏极夹头15可通过任何适当的工艺形成,包括蚀刻和压印。
图13示出图11中翻转过来的引线框先驱结构111。图13示出基准平台113上夹头15的支承区1216。焊膏1215位于支承区1216上。焊膏99设置在栅极焊点和源极焊点的内表面上。平坦的引线框表面1213也出现在引线框先驱结构111上。
图14示出具有附连的热漏极夹头的组装框的仰视立体图。图15示出具有附连的漏极夹头的组装框的俯视立体图。图15还示出热芯片附连夹头焊点159。图18示出图16-17所示的组合件的横截面图。图18另行示出将芯片32联接于漏极夹头15的导电粘合剂(例如焊料)186以及在夹头15和基准平台113之间的校准点1710。
如图14所示,夹头15可设置在源极和栅极焊点上以使钩125配合在水平狭槽1112中界定垂直狭槽1113的两相对边约束钩125的侧向移动,由此使夹头15相对于源极和栅极焊点14、31(见图15)的侧向和垂直定位变得稳定。如前面附图所示,半导体芯片32夹在源极焊点/栅极焊点14、31和漏极夹头15之间。半导体芯片32可使用传统焊料沉积工艺而通过焊料凸起。
如图16和17所示,在将半导体芯片32附连于先驱111和夹头15后,可形成模制材料113以使其覆盖半导体芯片32、先驱111中的框214和夹头15中的至少一部分。如图16所示,源极焊点14、栅极引线11和源极引线12的顶表面通过模制材料13露出,并基本与模制材料13的顶部外表面共面。如图17所示,漏极夹头15的底表面基本与模制材料13的底表面共面。模制材料13位于通过引线框先驱111形成的框窗179内。
模制可使用任意合适模制工具或模制工艺来实现。在示例性实施例中,模制工具可具有两个模具,其中模具的表面接触引线框和夹头的表面以使其在模制工艺中不用模制材料所覆盖。任何合适的模制温度和压力可用于本发明的实施例。
在模制后,参见图16-17,引线11、12以及夹头15带狭槽124的部分可通过锯等切割。引线11、12则可弯曲(如果尚未弯曲的话)以形成半导体芯片封装件。
尽管图示出一个半导体芯片封装件,然而半导体芯片封装件可成排地形成。
图19(a)-19(b)示出如图16-18所示的那些组合件的俯视平面图,其具有两种芯片尺寸。图19(a)示出2.66mm×3.66mm的芯片尺寸。图19(b)示出4mm×4mm的芯片尺寸。因此,如图19(a)-19(b)所示,本发明的实施例可包含任何适宜的芯片尺寸或芯片类型。
图20(a)-20(k)示出在构造时半导体芯片封装件的一部分。图20(a)-20(k)中的多数步骤已在上面描述,且其说明适用于此。
图20(a)-20(k)表示如下:图20(a)示出热漏极夹头15;图20(b)示出使用软焊料和芯片附连工艺(使用回流)附连于热漏极夹头15的芯片32;图20(c)-(d)示出在集成后并随后将夹头15和芯片32一体(倒装地)安装到引线框先驱111上而形成的结构。图20(e)示出在执行回流工艺后形成的结构,其中芯片32、夹头15和先驱111结合在一起;图20(f)示出在执行薄膜辅助模制工艺后形成的结构,籍此在封装件的选定部分周围形成模制材料13;图20(g)示出在执行喷水去毛刺后形成的结构。图20(h)示出在执行激光标志工艺后形成的结构,通过该工艺可对芯片封装件作出激光标志以供识别;图20(i)示出在集成工艺执行后形成的结构,籍此可将该封装件与一列中的其它封装件分开;图20(j)示出在单元测试步骤完成后形成的结构;而图20(k)示出就在包装和运输步骤前形成的结构。
本发明的实施例具有许多优势。本发明的实施例具有下列优势中的一些、全部或不具有这些优势。首先,通过模制材料露出引线框和夹头的一些部分,封装件非常薄并可用于例如无线电话、PDA等轻薄设备。其次,由于夹头和引线框露出较大的表面,则热易于从根据本发明一个实施例的半导体芯片封装件中的半导体芯片中散发出去。第三,可使用相同标准覆盖面积来安装较大的芯片尺寸。第四,如上面提到的,可使用钩将夹头恰当地与芯片和引线框对齐,由此减小制造过程中潜在的对位误差。第五,如果使用预电镀框的话则不需要去毛刺工艺和电镀工艺。第六,本发明的实施例具有灵活性并可铜墩凸起和无电极NiAu凸起两者。这些凸起可出现在之前描述的芯片上。第七,本发明的实施例是结实的并可用于诸如汽车之类的应用场合中。第八,由于封装件的两侧可与模具型腔的表面形成金属-金属接触,因此不需要使用薄膜辅助的模制工艺。
本文中使用的“顶”和“底”表面用于相对概念,即相对于其上安装根据本发明实施例的半导体芯片封装件的电路板的位置。这种位置术语可表示或者不表示这些封装件的绝对位置。
上述的半导体芯片封装件可用于包含其上安装有封装件的电路板的电子组合件。它们也可用于例如电话、计算机等系统中。
对“一”、“一个”和“该”的任何引述旨在表示一个或多个,除非具体声明为相反情形之外。
本文中采用的术语和表达作为描述款项而非限制,并且不打算使用这些术语和表达来排除图示和所描述的特征的等效物,可以理解多种修改也可用于本发明的权利要求范围内。
此外,本发明的一个或多个实施例的一个或多个特征可与本发明其它实施例的一个或多个特征结合而不脱离本发明的范围。
前面提到的全部专利、专利申请、公开物和说明书全篇地纳入于此以供参考。没有任何内容被认为是现有技术。
Claims (21)
1.一种半导体芯片封装件,包括:
半导体芯片,所述半导体芯片具有位于半导体芯片顶表面的输入以及位于半导体芯片底表面的输出;
具有第一引线框表面、与所述第一引线框表面相对的第二引线框表面和多个引线的引线框,其中所述第二引线框表面联接于半导体芯片顶表面;
具有第一夹头表面和第二夹头表面的夹头,其中所述第二夹头表面联接于所述半导体芯片底表面;以及
具有外模制材料表面并覆盖所述引线框、所述夹头和所述半导体芯片的至少一部分的模制材料,
其中所述第一引线框表面和所述第一夹头表面通过模制材料露出,并且所述第一引线框表面、所述第一夹头表面和所述模制材料的外模制材料表面形成所述半导体芯片封装件的外表面;以及
引线框引线从半导体芯片封装件的一端伸出到模制材料之外,其中引线的端部与第一夹头表面共面,而夹头的一部分从半导体芯片封装件的相反端伸出到模制材料之外。
2.如权利要求1所述的半导体芯片封装件,其特征在于,所述半导体芯片包括垂直器件。
3.如权利要求1所述的半导体芯片封装件,其特征在于,所述第一引线框表面界定所述引线框的突出引线框部分。
4.如权利要求3所述的半导体芯片封装件,其特征在于,所述第一夹头表面界定所述夹头的突出夹头部分。
5.如权利要求3所述的半导体芯片封装件,其特征在于,所述模制材料的外表面基本与所述第一夹头表面和所述第一引线框表面共面,且其中所述模制材料覆盖住所述突出引线框部分和所述突出夹头部分的边。
6.如权利要求1所述的半导体芯片封装件,其特征在于,所述半导体芯片使用焊料联接于所述引线框。
7.如权利要求6所述的半导体芯片封装件,其特征在于,所述焊料包括高温焊料材料和低温焊料材料。
8.如权利要求1所述的半导体芯片封装件,其特征在于,所述半导体芯片包括带沟道的栅极。
9.如权利要求1所述的半导体芯片封装件,其特征在于,所述引线框包括铜或铜合金。
10.一种包含如权利要求1所述的半导体芯片封装件的系统。
11.一种用于形成半导体芯片封装件的方法,所述方法包括:
获得半导体芯片,所述半导体芯片具有位于半导体芯片顶表面的输入以及位于半导体芯片底表面的输出;
将具有第一引线框表面和与所述第一引线框表面相对的第二引线框表面的引线框附连于所述半导体芯片,其中所述第二引线框表面联接于所述半导体芯片顶表面,所述引线框还具有多个引线;
附连具有第一夹头表面和第二夹头表面的夹头,其中所述第二夹头表面联接于所述半导体芯片底表面;以及
将模制材料模制在所述引线框、所述夹头和所述半导体芯片的至少一部分周围,
其中在模制后,所述第一引线框表面和所述第一夹头表面通过模制材料露出,并且所述第一引线框表面、所述第一夹头表面和所述模制材料的外模制材料表面形成所述半导体芯片封装件的外表面;以及
引线框引线从半导体芯片封装件的一端伸出到模制材料之外,其中引线的端部与第一夹头表面共面,而夹头的一部分从半导体芯片封装件的相反端伸出到模制材料之外。
12.如权利要求11所述的方法,其特征在于,将所述引线框附连于所述半导体芯片包括使用焊料将所述引线框附连于所述半导体芯片。
13.如权利要求11所述的方法,其特征在于,将所述夹头附连于所述半导体芯片包括使用焊料将所述夹头附连于所述半导体芯片。
14.如权利要求11所述的方法,其特征在于,还包括在将所述引线框附连于所述半导体芯片前,部分地蚀刻所述引线框以形成包含所述第一引线框表面的突出部分。
15.如权利要求14所述的方法,其特征在于,还包括在将所述夹头附连于所述半导体芯片前,部分地蚀刻所述夹头以形成包含所述第一夹头表面的突出部分。
16.如权利要求14所述的方法,其特征在于,所述模制包括使用具有与所述夹头和所述引线框的表面接触的模具的模制工具。
17.如权利要求14所述的方法,其特征在于,所述半导体芯片包括垂直MOSFET。
18.如权利要求14所述的方法,其特征在于,所述引线框包括铜。
19.如权利要求14所述的方法,其特征在于,将所述引线框附连于所述半导体芯片发生在将所述夹头附连于所述半导体芯片之后。
20.如权利要求14所述的方法,其特征在于,当形成所述半导体芯片封装件时,所述半导体芯片封装件呈一半导体芯片封装件阵列。
21.如权利要求11所述的方法,其特征在于,所述引线框由引线框先驱结构提供,所述先驱结构有槽;
其中,所述夹头还包括定位钩;以及
连接所述夹头包括将定位钩配合在所述槽中。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/845,560 US20090057852A1 (en) | 2007-08-27 | 2007-08-27 | Thermally enhanced thin semiconductor package |
US11/845,560 | 2007-08-27 | ||
PCT/US2008/072207 WO2009029397A1 (en) | 2007-08-27 | 2008-08-05 | Thermally enhanced thin semiconductor package |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101796637A CN101796637A (zh) | 2010-08-04 |
CN101796637B true CN101796637B (zh) | 2012-05-30 |
Family
ID=40387695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200880105612XA Active CN101796637B (zh) | 2007-08-27 | 2008-08-05 | 热增强的薄半导体封装件 |
Country Status (6)
Country | Link |
---|---|
US (2) | US20090057852A1 (zh) |
KR (1) | KR101539250B1 (zh) |
CN (1) | CN101796637B (zh) |
DE (1) | DE112008002338T5 (zh) |
TW (1) | TWI464833B (zh) |
WO (1) | WO2009029397A1 (zh) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7791084B2 (en) * | 2008-01-09 | 2010-09-07 | Fairchild Semiconductor Corporation | Package with overlapping devices |
US8193618B2 (en) * | 2008-12-12 | 2012-06-05 | Fairchild Semiconductor Corporation | Semiconductor die package with clip interconnection |
US7973393B2 (en) * | 2009-02-04 | 2011-07-05 | Fairchild Semiconductor Corporation | Stacked micro optocouplers and methods of making the same |
US8354303B2 (en) * | 2009-09-29 | 2013-01-15 | Texas Instruments Incorporated | Thermally enhanced low parasitic power semiconductor package |
CN102473653B (zh) * | 2010-02-01 | 2016-05-04 | 丰田自动车株式会社 | 半导体装置的制造方法以及半导体装置 |
US8324025B2 (en) * | 2010-04-22 | 2012-12-04 | Team Pacific Corporation | Power semiconductor device packaging |
TWI453831B (zh) | 2010-09-09 | 2014-09-21 | 台灣捷康綜合有限公司 | 半導體封裝結構及其製造方法 |
JP5921072B2 (ja) * | 2011-03-05 | 2016-05-24 | 新電元工業株式会社 | 樹脂封止型半導体装置 |
CN103035631B (zh) * | 2011-09-28 | 2015-07-29 | 万国半导体(开曼)股份有限公司 | 联合封装高端和低端芯片的半导体器件及其制造方法 |
US9478484B2 (en) * | 2012-10-19 | 2016-10-25 | Infineon Technologies Austria Ag | Semiconductor packages and methods of formation thereof |
US9966330B2 (en) | 2013-03-14 | 2018-05-08 | Vishay-Siliconix | Stack die package |
US9589929B2 (en) | 2013-03-14 | 2017-03-07 | Vishay-Siliconix | Method for fabricating stack die package |
US20150060123A1 (en) * | 2013-09-04 | 2015-03-05 | Texas Instruments Incorporated | Locking dual leadframe for flip chip on leadframe packages |
KR102153041B1 (ko) * | 2013-12-04 | 2020-09-07 | 삼성전자주식회사 | 반도체소자 패키지 및 그 제조방법 |
JP2015142072A (ja) * | 2014-01-30 | 2015-08-03 | 株式会社東芝 | 半導体装置 |
EP4148779A1 (en) * | 2021-09-14 | 2023-03-15 | Nexperia B.V. | A semiconductor device and a method of manufacture |
US9673097B2 (en) * | 2015-05-11 | 2017-06-06 | Texas Instruments Incorporated | Integrated clip and lead and method of making a circuit |
US10256207B2 (en) * | 2016-01-19 | 2019-04-09 | Jmj Korea Co., Ltd. | Clip-bonded semiconductor chip package using metal bumps and method for manufacturing the package |
US9892997B2 (en) * | 2016-04-19 | 2018-02-13 | Infineon Technologies Americas Corp. | Adaptable molded leadframe package and related method |
DE102016107792B4 (de) | 2016-04-27 | 2022-01-27 | Infineon Technologies Ag | Packung und halbfertiges Produkt mit vertikaler Verbindung zwischen Träger und Klammer sowie Verfahren zum Herstellen einer Packung und einer Charge von Packungen |
CN106449578A (zh) * | 2016-09-21 | 2017-02-22 | 无锡罗姆半导体科技有限公司 | 半导体封装件及其封装方法 |
TWI608583B (zh) * | 2016-12-14 | 2017-12-11 | Taiwan Semiconductor Co Ltd | 共源極式封裝結構 |
US10121742B2 (en) * | 2017-03-15 | 2018-11-06 | Amkor Technology, Inc. | Method of forming a packaged semiconductor device using ganged conductive connective assembly and structure |
EP3462482A1 (en) * | 2017-09-27 | 2019-04-03 | Nexperia B.V. | Surface mount semiconductor device and method of manufacture |
EP3584832A1 (en) | 2018-06-20 | 2019-12-25 | Nexperia B.V. | A lead frame assembly for a semiconductor device |
CN111261596A (zh) * | 2018-12-03 | 2020-06-09 | 杰米捷韩国株式会社 | 利用多个夹件结构的半导体封装及其制造方法 |
US20200194347A1 (en) * | 2018-12-18 | 2020-06-18 | Alpha And Omega Semiconductor (Cayman) Ltd. | Semiconductor package and method of making the same |
US11302615B2 (en) | 2019-12-30 | 2022-04-12 | Texas Instruments Incorporated | Semiconductor package with isolated heat spreader |
US11600498B2 (en) * | 2019-12-31 | 2023-03-07 | Texas Instruments Incorporated | Semiconductor package with flip chip solder joint capsules |
CN111524868B (zh) * | 2020-03-25 | 2024-03-12 | 长电科技(宿迁)有限公司 | 一种引线框架和金属夹片的组合结构及铆接装片工艺 |
EP4270476A1 (en) * | 2022-04-29 | 2023-11-01 | Infineon Technologies Austria AG | Semiconductor package and method for marking a semiconductor package |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
CN1360814A (zh) * | 1999-05-27 | 2002-07-24 | 理查德·K·威廉斯 | 功率半导体器件的表面安装封装 |
CN1685504A (zh) * | 2002-09-30 | 2005-10-19 | 费查尔德半导体有限公司 | 包含漏极夹的半导体管芯封装 |
Family Cites Families (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3956821A (en) * | 1975-04-28 | 1976-05-18 | Fairchild Camera And Instrument Corporation | Method of attaching semiconductor die to package substrates |
US4058899A (en) * | 1976-08-23 | 1977-11-22 | Fairchild Camera And Instrument Corporation | Device for forming reference axes on an image sensor array package |
US4680613A (en) * | 1983-12-01 | 1987-07-14 | Fairchild Semiconductor Corporation | Low impedance package for integrated circuit die |
US4751199A (en) * | 1983-12-06 | 1988-06-14 | Fairchild Semiconductor Corporation | Process of forming a compliant lead frame for array-type semiconductor packages |
US4772935A (en) * | 1984-12-19 | 1988-09-20 | Fairchild Semiconductor Corporation | Die bonding process |
US4890153A (en) * | 1986-04-04 | 1989-12-26 | Fairchild Semiconductor Corporation | Single bonding shelf, multi-row wire-bond finger layout for integrated circuit package |
US4720396A (en) * | 1986-06-25 | 1988-01-19 | Fairchild Semiconductor Corporation | Solder finishing integrated circuit package leads |
US4791473A (en) * | 1986-12-17 | 1988-12-13 | Fairchild Semiconductor Corporation | Plastic package for high frequency semiconductor devices |
US4839717A (en) * | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
US4731701A (en) * | 1987-05-12 | 1988-03-15 | Fairchild Semiconductor Corporation | Integrated circuit package with thermal path layers incorporating staggered thermal vias |
US4796080A (en) * | 1987-07-23 | 1989-01-03 | Fairchild Camera And Instrument Corporation | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate |
US5327325A (en) * | 1993-02-08 | 1994-07-05 | Fairchild Space And Defense Corporation | Three-dimensional integrated circuit package |
US5646446A (en) * | 1995-12-22 | 1997-07-08 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
US6424035B1 (en) * | 1998-11-05 | 2002-07-23 | Fairchild Semiconductor Corporation | Semiconductor bilateral switch |
KR100335480B1 (ko) * | 1999-08-24 | 2002-05-04 | 김덕중 | 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지 |
KR100335481B1 (ko) * | 1999-09-13 | 2002-05-04 | 김덕중 | 멀티 칩 패키지 구조의 전력소자 |
US6720642B1 (en) * | 1999-12-16 | 2004-04-13 | Fairchild Semiconductor Corporation | Flip chip in leaded molded package and method of manufacture thereof |
US6989588B2 (en) * | 2000-04-13 | 2006-01-24 | Fairchild Semiconductor Corporation | Semiconductor device including molded wireless exposed drain packaging |
US6556750B2 (en) * | 2000-05-26 | 2003-04-29 | Fairchild Semiconductor Corporation | Bi-directional optical coupler |
KR100370231B1 (ko) * | 2000-06-13 | 2003-01-29 | 페어차일드코리아반도체 주식회사 | 리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지 |
KR100403608B1 (ko) * | 2000-11-10 | 2003-11-01 | 페어차일드코리아반도체 주식회사 | 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법 |
KR100374629B1 (ko) * | 2000-12-19 | 2003-03-04 | 페어차일드코리아반도체 주식회사 | 얇고 작은 크기의 전력용 반도체 패키지 |
US6469384B2 (en) * | 2001-02-01 | 2002-10-22 | Fairchild Semiconductor Corporation | Unmolded package for a semiconductor device |
US6777786B2 (en) * | 2001-03-12 | 2004-08-17 | Fairchild Semiconductor Corporation | Semiconductor device including stacked dies mounted on a leadframe |
US6891257B2 (en) * | 2001-03-30 | 2005-05-10 | Fairchild Semiconductor Corporation | Packaging system for die-up connection of a die-down oriented integrated circuit |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US6893901B2 (en) * | 2001-05-14 | 2005-05-17 | Fairchild Semiconductor Corporation | Carrier with metal bumps for semiconductor die packages |
US7061080B2 (en) * | 2001-06-11 | 2006-06-13 | Fairchild Korea Semiconductor Ltd. | Power module package having improved heat dissipating capability |
US6683375B2 (en) * | 2001-06-15 | 2004-01-27 | Fairchild Semiconductor Corporation | Semiconductor die including conductive columns |
US6449174B1 (en) * | 2001-08-06 | 2002-09-10 | Fairchild Semiconductor Corporation | Current sharing in a multi-phase power supply by phase temperature control |
US6633030B2 (en) * | 2001-08-31 | 2003-10-14 | Fiarchild Semiconductor | Surface mountable optocoupler package |
US6774465B2 (en) * | 2001-10-05 | 2004-08-10 | Fairchild Korea Semiconductor, Ltd. | Semiconductor power package module |
US6891256B2 (en) * | 2001-10-22 | 2005-05-10 | Fairchild Semiconductor Corporation | Thin, thermally enhanced flip chip in a leaded molded package |
US6674157B2 (en) * | 2001-11-02 | 2004-01-06 | Fairchild Semiconductor Corporation | Semiconductor package comprising vertical power transistor |
US6566749B1 (en) * | 2002-01-15 | 2003-05-20 | Fairchild Semiconductor Corporation | Semiconductor die package with improved thermal and electrical performance |
US6830959B2 (en) * | 2002-01-22 | 2004-12-14 | Fairchild Semiconductor Corporation | Semiconductor die package with semiconductor die having side electrical connection |
US6867489B1 (en) * | 2002-01-22 | 2005-03-15 | Fairchild Semiconductor Corporation | Semiconductor die package processable at the wafer level |
AU2003218085A1 (en) * | 2002-03-12 | 2003-09-29 | Fairchild Semiconductor Corporation | Wafer-level coated copper stud bumps |
US7122884B2 (en) * | 2002-04-16 | 2006-10-17 | Fairchild Semiconductor Corporation | Robust leaded molded packages and methods for forming the same |
US6836023B2 (en) * | 2002-04-17 | 2004-12-28 | Fairchild Semiconductor Corporation | Structure of integrated trace of chip package |
KR100843737B1 (ko) * | 2002-05-10 | 2008-07-04 | 페어차일드코리아반도체 주식회사 | 솔더 조인트의 신뢰성이 개선된 반도체 패키지 |
US7061077B2 (en) * | 2002-08-30 | 2006-06-13 | Fairchild Semiconductor Corporation | Substrate based unmolded package including lead frame structure and semiconductor die |
US6943434B2 (en) * | 2002-10-03 | 2005-09-13 | Fairchild Semiconductor Corporation | Method for maintaining solder thickness in flipchip attach packaging processes |
US6806580B2 (en) * | 2002-12-26 | 2004-10-19 | Fairchild Semiconductor Corporation | Multichip module including substrate with an array of interconnect structures |
KR100958422B1 (ko) * | 2003-01-21 | 2010-05-18 | 페어차일드코리아반도체 주식회사 | 고전압 응용에 적합한 구조를 갖는 반도체 패키지 |
US7217594B2 (en) * | 2003-02-11 | 2007-05-15 | Fairchild Semiconductor Corporation | Alternative flip chip in leaded molded package design and method for manufacture |
JP4173751B2 (ja) * | 2003-02-28 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置 |
US7271497B2 (en) * | 2003-03-10 | 2007-09-18 | Fairchild Semiconductor Corporation | Dual metal stud bumping for flip chip applications |
US6867481B2 (en) * | 2003-04-11 | 2005-03-15 | Fairchild Semiconductor Corporation | Lead frame structure with aperture or groove for flip chip in a leaded molded package |
JP3759131B2 (ja) * | 2003-07-31 | 2006-03-22 | Necエレクトロニクス株式会社 | リードレスパッケージ型半導体装置とその製造方法 |
JP4294405B2 (ja) * | 2003-07-31 | 2009-07-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US7196313B2 (en) * | 2004-04-02 | 2007-03-27 | Fairchild Semiconductor Corporation | Surface mount multi-channel optocoupler |
US7242076B2 (en) * | 2004-05-18 | 2007-07-10 | Fairchild Semiconductor Corporation | Packaged integrated circuit with MLP leadframe and method of making same |
US7256479B2 (en) * | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
US7576429B2 (en) * | 2005-12-30 | 2009-08-18 | Fairchild Semiconductor Corporation | Packaged semiconductor device with dual exposed surfaces and method of manufacturing |
US7371616B2 (en) * | 2006-01-05 | 2008-05-13 | Fairchild Semiconductor Corporation | Clipless and wireless semiconductor die package and method for making the same |
TWM423084U (en) * | 2011-05-26 | 2012-02-21 | Vp Components Co Ltd | Bicycle upper baffle structure |
-
2007
- 2007-08-27 US US11/845,560 patent/US20090057852A1/en not_active Abandoned
-
2008
- 2008-08-05 WO PCT/US2008/072207 patent/WO2009029397A1/en active Application Filing
- 2008-08-05 DE DE112008002338T patent/DE112008002338T5/de not_active Withdrawn
- 2008-08-05 CN CN200880105612XA patent/CN101796637B/zh active Active
- 2008-08-05 KR KR1020107006496A patent/KR101539250B1/ko active IP Right Grant
- 2008-08-13 TW TW097130802A patent/TWI464833B/zh active
-
2010
- 2010-03-03 US US12/717,012 patent/US8193622B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6040626A (en) * | 1998-09-25 | 2000-03-21 | International Rectifier Corp. | Semiconductor package |
CN1360814A (zh) * | 1999-05-27 | 2002-07-24 | 理查德·K·威廉斯 | 功率半导体器件的表面安装封装 |
CN1685504A (zh) * | 2002-09-30 | 2005-10-19 | 费查尔德半导体有限公司 | 包含漏极夹的半导体管芯封装 |
Also Published As
Publication number | Publication date |
---|---|
TWI464833B (zh) | 2014-12-11 |
WO2009029397A1 (en) | 2009-03-05 |
TW200915498A (en) | 2009-04-01 |
DE112008002338T5 (de) | 2010-07-08 |
US8193622B2 (en) | 2012-06-05 |
KR20100061700A (ko) | 2010-06-08 |
CN101796637A (zh) | 2010-08-04 |
US20090057852A1 (en) | 2009-03-05 |
US20100155913A1 (en) | 2010-06-24 |
KR101539250B1 (ko) | 2015-07-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101796637B (zh) | 热增强的薄半导体封装件 | |
CN102308383B (zh) | 半导体管芯封装件及其制造方法 | |
US7166496B1 (en) | Method of making a packaged semiconductor device | |
CN101595560B (zh) | 预模制夹头结构 | |
KR101410514B1 (ko) | 리드프레임과 클립을 이용하는 반도체 다이 패키지 및 그제조방법 | |
CN100409443C (zh) | 含侧向电气连接的半导体管芯的半导体管芯封装 | |
JP4878030B2 (ja) | エッチング処理されたリードフレームを用いる再分散型ハンダパッド | |
US10262948B2 (en) | Semiconductor module having outflow prevention external terminals | |
US7972906B2 (en) | Semiconductor die package including exposed connections | |
US8106501B2 (en) | Semiconductor die package including low stress configuration | |
US8188587B2 (en) | Semiconductor die package including lead with end portion | |
US20070045785A1 (en) | Reversible-multiple footprint package and method of manufacturing | |
US20090194856A1 (en) | Molded package assembly | |
US10373897B2 (en) | Semiconductor devices with improved thermal and electrical performance | |
US9275983B2 (en) | Integrated circuit package | |
US10985093B2 (en) | Semiconductor device and method for producing semiconductor device | |
US20090127681A1 (en) | Semiconductor package and method of fabricating the same | |
CN114823597A (zh) | 半导体器件封装和制造半导体器件封装的方法 | |
US9640474B1 (en) | Power semiconductor package having power semiconductor die in a support substrate with bar vias | |
TWI323932B (en) | Semiconductor device | |
CN111354703A (zh) | 一种封装电子元件及其制造方法 | |
JP6065500B2 (ja) | 半導体装置 | |
US20230245954A1 (en) | Semiconductor device, and production method for semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |