CN101826501A - 高密度接点的无引脚集成电路元件 - Google Patents

高密度接点的无引脚集成电路元件 Download PDF

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CN101826501A
CN101826501A CN200910147481A CN200910147481A CN101826501A CN 101826501 A CN101826501 A CN 101826501A CN 200910147481 A CN200910147481 A CN 200910147481A CN 200910147481 A CN200910147481 A CN 200910147481A CN 101826501 A CN101826501 A CN 101826501A
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contact areas
end points
weld zone
integrated circuit
chip
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CN101826501B (zh
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李同乐
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Abstract

本发明涉及一种无引脚集成电路元件，包括安装在金属引线框上的IC芯片和大量与IC芯片电连接的电接点；所述IC芯片、电接点和部分金属引线框被封装材料所覆盖，而所述电接点的一部分从封装材料的底面引出。

Description

高密度接点的无引脚集成电路元件
相关申请的交叉引用
本申请要求享有于2009年3月6日提交的申请号为61/158,170和2009年4月3日提交的申请号为61/166,547的美国临时专利申请的优先权，两者的全文通过引用而结合于此。
技术领域
本发明涉及集成电路封装技术，更具体地说，但不仅仅是，具有更高密度的接点和晶粒粘贴垫的无引脚集成电路元件以及它的相关制造方法。
背景技术
集成电路(Integrated circuit，IC)封装是IC元件生产过程中的最后几个步骤之一。在IC封装过程中，一个或多个IC芯片被贴在一个封装基板上，并与电接点连接，然后又被盖上一层由电绝缘材料(如：环氧或有机硅模塑封料)构成的封装材料。最终成型的形状就是我们通常所说的“IC封装元件”，其可以被安装到印刷电路板(Printed circuitboard，PCB)上和/或与其它电气元件连接。
在大多数的IC封装元件中，IC芯片被成型材料完全覆盖，而电接点会至少部分外露，以便它们能被粘贴到其它电子元件上。换句话说，电接点是用来在IC元件内部的IC芯片和IC元件外部的电子元件之间形成电连接。IC封装中最具有成本效益的做法是：用金属引线框来代替层压板或胶纸材料。金属引线框使用了比层压材料成本更低的铜、镍、其他金属或合金，且采用的冲压或蚀刻工艺的成本也比多步层压工艺的成本要低得多。最常见的一种接点设计方式是：从成型材料的四周延伸出“引脚”。这些引脚常常向下弯曲，从而可在印刷电路板上与电子元件连接起来。
通常情况下，外部引脚的存在会使IC封装元件的尺寸增大。例如：常常由于引脚的横向延伸而增大了IC封装元件的长度和宽度。尺寸增大后对PCB空间有限的系统来说是不利的。另外，由于外部引脚常常沿着IC封装元件的四周排列，所以IC封装元件的引脚数会受到IC封装元件四周的直线距离的限制。另一个不利之处是，这些引脚还要求额外的检查步骤来判断平坦度，高低脚和其它尺寸要求(如果检查项目达不到规格，就应重新加工或废弃)。最终，引脚(从焊接指到外部顶端)长度会加在电信号的总长度中(焊线长度+引脚长度)，从而影响IC芯片的电气性能。
意识到传统IC封装元件中出现的这些问题后，我们的研究人员设计出一种新的封装方法，即：用电接点代替外部引脚，且IC封装元件正面的电接点是被封装材料盖住的，而底面的接点却外露出来。这样便可使这些接点与位于IC封装元件下方的电子元件连接起来。这些IC封装元件(即熟称的“无引脚”IC封装元件)跟传统的IC封装元件相比，由于外部引脚的不复存在而占用了较少的空间。另外，再也不需要通过弯曲引脚来形成电连接了。专利号6498099和7049177的美国专利分别公开了几种常用的“无引脚”IC封装元件，在这里引用作为参考。除其他外，这些专利描述并说明了无引脚IC封装元件的设计变更及制造和使用该无引脚IC封装元件的各种技术。
图1A和图1B是无引脚IC封装件的一个实例。图1A是一个IC封装元件100的仰视图，其拥有一个顶部表面安装了一块IC芯片104(图1A虚线所示)的晶粒粘贴垫(Die attach pad，DAP)102。可以看到多个接点106被布置在DAP102的周边。在将IC封装元件100安装到PCB上时，接点106可以用来在IC芯片104和PCB之间形成电连接。DAP102和大量接点106之间可浇注一层封装材料108，例如，用来隔离接点106与DAP102。图1B是图1A中IC封装元件100在A-A线处的剖面图。IC芯片104可通过导电银胶110贴在DAP102上。引线112可用于在IC芯片104和多个焊点116之间于端点处形成电连接，端点与DAP102电隔离。引线114可用于在IC芯片104和多个焊点118之间形成电连接，焊点118未与DAP102电隔离。由于接点106与DAP102是隔离开的，接点106可以用来在印刷电路板(图中未显示)和IC芯片104上的输入/输出(I/O)端口之间传递信号。由于DAP的焊点118未与DAP102隔离开，这些电连接只能用于在IC芯片104的电接地功能。
这种IC封装元件的一个局限之处是：可用来在IC芯片I/O端口传递电信号的端点的最大数量受到DAP四周可排布的端点数的限制。如图2所示，人们尝试通过减少端点的间距来在DAP四周排布更多的端点，以及增加DAP四周可排布端点的行数，以便增加能够与IC芯片的I/O端口建立电连接的端点数量。然而，增加端点的行数需要通过减少IC芯片的尺寸或增加IC封装元件的尺寸来实现。此外，端点间距离能够被缩减的量仍然受到PCB上连接点的间距的限制，而PCB上连接点的间距是比较大的。
发明内容
本申请公开的多种实施例是涉及接点密度更高的无引脚集成电路及其制造方法。在一实施例中，一种无引脚集成电路元件，包括金属引线框；所述金属引线框有顶面和底面，并包括大量从顶面延伸到底面的端点，每个所述端点都包括位于顶部表面的焊接区、位于底面的接点区和一连接两者的金属轨迹线；所述无引脚集成电路元件还包括IC芯片；所述IC芯片安装在金属引线框的顶面，并包括大量焊接盘；所述无引脚集成电路元件还包括大量引线；所述每根引线都与一焊接区及一焊接盘连接；所述无引脚集成电路元件还包括封装材料；其覆盖所述IC芯片、所述大量引线和所述大量端点中每个端点的至少一部分；其特征在于，所述大量端点的接点区没有被封装材料完全封装；所述大量端点中至少有一个端点包括电连接到焊接区的金属轨迹线，该焊接区从接点区横向延伸；因此不再需要与金属引线框顶面垂直的导线来连接焊接区和接点区，而是通过金属轨迹线来对焊接区和接点区进行电连接。
在某些实施例中，所述无引脚集成电路元件可能包括接点区，所述接点区位于IC芯片下方与位于IC芯片周边的焊接区之间形成电连接；该无引脚集成电路元件还包括位于金属轨迹线和IC芯片之间的粘合层。在某些实施例中，从接点区延伸来焊接区是以下列方式中的一种或多种方式实现的：相对于IC芯片，从接点区向外排布；相对于IC芯片，从接点区向内排布；排布在与IC芯片边缘平行的位置。
在某些实施例中，所述大量端点中第一端点焊接区和所述大量端点中第二端点焊接区的中心距小于所述第一端点接点区和所述第二端点接点区的中心距。在某些实施例中，无引脚集成电路元件包括所述大量端点中的第一端点；所述第一端点有一连接到第一接点区的第一焊接区，所述接点区直接位于其底面；该无引脚集成电路元件还包括所述大量端点中的第二端点；所述第二端点有一连接到第二接点区的第一焊接区，所述接点区直接位于其底面；以及所述大量端点中的第三端点；所述第三端点有一连接到第三接点区的第一焊接区；其特征在于，第三焊接区位于第一焊接区和第二焊接区之间；并且所述第三接点区从第一接点区和第二接点区之间的区域横向延伸。其他一些实施例中，可能还包括所述大量端点中的第四端点；所述第四端点有一连接到第四接点区的第四焊接区；其特征在于，所述第四焊接区位于第一焊接区和第二焊接区之间；并且所述第四接点区从第一接点区和第二接点区之间的区域横向延伸。
在某些实施例中，无引脚集成电路元件，可能包括：所述大量端点中的第一端点；所述第一端点有一第一接点区；所述大量端点中的第二端点；所述第二端点有一与第一接点区邻近的第二接点区；以及所述大量端点中的第三端点；所述第三端点有一从第一接点区延伸到第二接点区的金属轨迹线。在某些实施例中，所述金属引线框的底面被选择性蚀刻，从而使金属引线框底面与封装材料底面大致贴合；和/或所述金属引线框的底面被选择性蚀刻，从而使金属引线框底面的至少一部分与封装材料底面大致贴合。在某些实施例中，所述的无引脚集成电路元件包括，所述金属引线框的底面被选择性蚀刻，从而使金属引线框位于封装材料内部的至少一部分被移除；和/或所述金属轨迹线的底面被选择性蚀刻，从而使金属轨迹线位于封装材料内部的至少一部分被移除。
在某些实施例中，所述的无引脚集成电路元件进一步包括一金属镀层；所述金属镀层位于所述焊接区中至少一个的顶面；并且其特征在于，金属引线框位于金属镀层下的至少一部分被蚀刻移除。在某些实施例中，所有的位于金属镀层下的金属引线框被充分地蚀刻移除。在某些实施例中，所述第大量焊接区述金属引线框底面的至少一部分被蚀刻掉，以充分与封装层的底面贴合。在某些实施例中，所述的制造无引脚集成电路元件的方法，所述IC芯片被安装在金属引线框的晶粒粘贴区上；所述晶粒粘贴区与封装层底面之间构成第一距离，所述接点区与成型层的底面构成第二距离；且所述第一距离小于第二距离。
在某些实施例中，在所述封装材料的内部，至少一个所述金属轨迹线下底面的至少一部分被蚀刻掉。在某些实施例中，所述的制造无引脚集成电路元件的方法，包括：在金属引线框的顶面部分蚀刻出通道；并且通过所述通道，将一部分所述封装材料浇注在金属引线框和IC芯片之间，以使得封装材料是隔离的并且不能到达部分凹槽。在某些实施例中，所述的制造无引脚集成电路元件的方法，可能包括：从一个多单元引线框剥落器封装隔离无引脚IC封装元件。
上述本发明的发明内容并不代表本发明的每一个实施方式或本发明的所有方面。
附图说明
通过参照以下详细说明并结合附图可对本发明的各项实施例有一个较完整的理解。
图1A-B是一个无引脚四方扁平封装(QFN)无引脚IC封装元件的实施例示意图；
图2是一个热无引脚阵列(TLA)IC封装元件的实施例示意图；
图3A-B是与封装元件相比具有较大尺寸IC芯片的无引脚IC封装元件的实施例示意图；
图4A-B是顶部表面形成了大量金属轨迹线的金属引线框的实施例示意图；
图5A-E是一个无引脚IC封装元件实施例在制造过程中不同阶段的示意图；
图6A-C是具有两排焊接区和多排接点区的IC封装元件实施例在不同角度的示意图；
中的第一焊接区的宽度小于5密耳；所述第一焊接区边缘和第二焊接区边缘之间的距离小于5密耳；和/或所述至少一个金属轨迹线的底面涂有一层保护材料；所述保护材料为银胶、氧化物或阻焊剂。
在某些实施例中，所述的无引脚集成电路元件，包括：在接点区底面形成的阻焊保护层；其特征在于，所述阻焊保护层从以下几组中选取：镍、钯和金的电镀叠层；镍和金的电镀叠层；镍和银的电镀叠层；银、金或镍和金的金属镀层；锡的电镀层或置换镀层；由锡和铅组成的焊料涂层，或锡合金焊料；由锡和铅组成的焊球，或锡合金焊料；以及具有有机可焊性防腐剂涂层的裸铜。在某些实施例中，所述金属引线框的顶面包括晶粒粘贴垫；且至少一部分IC芯片被安装在晶粒粘贴垫上。在某些实施例中，所述无引脚集成电路元件包括安装到所述IC芯片上，并与金属引线框电连接的一个或多个IC芯片。
在某些实施例中，一种制造无引脚集成电路元件的方法，包括：对金属引线框的顶面部分蚀刻以在内部形成凹槽；所述凹槽定义了大量金属轨迹线的上部，所述大量金属轨迹线中的每个金属轨迹线都有一位于其上部的焊接区；在金属引线框上安装一IC芯片；通过引线对IC芯片和焊接区进行电连接；应用成型材料覆盖IC芯片、引线和大量金属轨迹线并填充金属引线框的凹槽；对金属引线框的底面进行选择性地蚀刻来使所述大量金属轨迹线中的每个金属轨迹线彼此间隔开，所述大量金属轨迹线中的每个金属轨迹线有一位于其下表面的接点区，并且没有被封装材料完全覆盖；并且，其特征在于，至少一个所述金属轨迹线包括从焊接区横向延伸的接点区，使得不需要垂直金属引线框顶面的导线来连接接点区和焊接区。
在某些实施例中，所述的制造无引脚集成电路元件的方法，可能包括：所述金属轨迹线下表面的至少一部分被蚀刻掉，以充分与封装层的底面贴合。在某些实施例中，所述的制造无引脚集成电路元件的方法可能包括：将所述金属轨迹线下表面的至少一部分涂上保护层。在某些实施例中，所述的制造无引脚集成电路元件的方法，可能包括，所述保护层包括以下涂层中的一种或多种：抗氧化涂层、环氧树脂涂层和保护油墨。
在某些实施例中，所述的制造无引脚集成电路元件的方法，可能包括：所
图7A-B是具有晶粒粘贴垫的无引脚IC封装元件多个实施例的示意图；
图7C-J是图7B中IC封装元件的各个面在制造过程中不同阶段的示意图；
图8A-D是无引脚IC封装元件多个实施例的示意图；
图9A-C是具有两个倒晶封装IC芯片和引线阵列的无引脚IC封装元件的典型实施例示意图；
图10A-B是内部有气孔的无引脚IC封装元件的典型实施例示意图；
图11A-B是无引脚IC封装元件引线框的典型实施例示意图；
图12A-H是各种IC封装元件构型的图例，以及各实施例中I/O端口数的表格。
具体实施方式
下方将结合附图对本发明的各具体实施例进一步说明。虽然本发明结合了具体实施例进行说明，但是应当理解本发明可以有多种方式实施，而不仅限于这里所公布的具体实施例；本发明提供的具体实施例使得本发明公开更加充分和完整，且使得本领域技术人员能够完全掌握本发明的范围。
图3A-B是无引脚IC封装元件300实施例的两个不同角度的视图。图3A是IC封装元件300在封装之前的俯视图，图3B是图3A中IC封装元件300在A-A线处的剖面图。如图3B中实施例所示，IC封装元件300包括IC芯片304，其安装在IC封装元件300的中部，并被封装材料308所覆盖，且便于与外部元件(图中未显示，如PCB)之间通过大量端点形成电连接；每个端点包括焊接区318、接点区306和连接在焊接区318与接点区306之间的金属轨迹线322。在此实施例中，IC芯片304和焊接区318之间通过引线314形成了电连接。IC封装元件300还包括大量金属轨迹线322，其在焊接区318和接点区306之间形成电连接。这样，可以减少任何两个焊接区318的间距，而非必须减少相应接点区306的间距。例如，在图3A中，焊接区318A和318B的中心距大约为0.2mm，但是相关接点区306A和306B的中心距大约为0.5mm。在各个实施例中，可以增加焊接区的数量，而不需要减小IC芯片的尺寸。
如图4A所示，金属引线框(LF)424的顶部表面构建了大量金属轨迹线422。在某些实施例中，LF424可能实际上是一块平板金属片。图4B为图4A中细节A的放大图。在LF424的顶面根据预定的图案进行蚀刻，就形成了凹槽426，而凹槽426之间保留的部分就形成了金属轨迹线422(如细节A所示)。图4A中，LF424上的阴影部分即金属轨迹线422，而LF424上没有阴影的部分即是凹槽426。虽然本发明给出了一种具体的蚀刻图案，但是可选用任意图案对金属LF424进行蚀刻。焊接区418(用于通过引线连接到IC芯片)可以包括一部分位于LF424四周的金属轨迹线422。更具体地说，接点区406(用于在IC芯片和PCB上相关的接点之间形成电连接)可以被布置到金属轨迹线422的相对于焊接区418的另一端。在图4A中，相对于焊接区418而言，所有的接点区406(图中为正方形)都位于IC封装元件靠内的位置。然而，在不同实施例中，一些接点区406可能被直接放置在焊接区418的下方，或可能被放置在靠近LF424周边的焊接区418表面。
一般情况下，当IC芯片被安装到一个LF上时，LF位于IC芯片下方的部分被叫做晶粒粘贴区(DA区)。当LF的顶面的某些部分被选择性的蚀刻后，LF上就形成了凹槽，而凹槽间突起的部分就形成了金属轨迹线。当IC芯片被安装在带有的凹槽(延伸到DA区)的LF上时，IC芯片将被由蚀刻的凹槽所确定的金属轨迹线所支撑，IC芯片和凹槽间将形成空隙。为了确保IC芯片和金属轨迹线的之间的贴合，在IC芯片的底面涂布了粘合层。在某些实施例中，粘合层可能是不导电的介质，使得IC芯片的底面和IC芯片的金属轨迹线之间相互绝缘。在确保IC芯片与金属轨迹线电隔离后，可采用模塑、滴胶、喷雾或其他封装技术，使用封装材料(如银胶、硅树脂或其他成型材料)进行浇注，覆在IC芯片的表面、金属轨迹线以及填充在LF的凹槽内，包括填充位于DA区凹槽和IC芯片间的空隙。
图5A至图5D是一个无引脚IC封装元件实施例在制造过程中不同阶段的示意图。如图5A所示，制造过程从金属引线框524开始。在图5B中，对金属引线框524的顶面进行蚀刻构建凹槽526，从而确定金属轨迹线522。焊接区528同样被布置在金属轨迹线顶面的一部分上。在金属轨迹线522的顶面的一部分附上一层可焊接材料，即可构建焊接区528。例如，在金属轨迹线522上镀上或包上一层金属，如银(Ag)、金(Au)、铜(Cu)或其它可焊接的材料。在图5C中，用一种粘接胶510对IC芯片504和金属引线框524进行封装，例如，银胶。在某些实施例中，在将IC芯片504粘贴到金属引线框524上的晶粒粘贴区之前，IC芯片504的整个底面表面被均匀地涂上一层粘接胶510。在某些实施例中，粘接胶510只涂布在IC芯片504底面的部分区域或金属引线框524上。在将IC芯片安装到金属引线框524上后，IC芯片和位于晶粒粘贴区外面的焊接区528之间可形成电连接。在本实施例中，引线514作为电连接介质。
如图5D所示，封装材料508(图中阴影所示部分)用于对IC芯片504和引线514进行封装。此外，封装材料508还填充在凹槽526中，包括填充在位于晶粒粘贴区的凹槽526中。
如图5E所示，LF524的底面被回蚀。在各实施例中，回蚀的部位包括LF524底面上与LF顶面形成的凹槽相对应的部位，并将LF的这些区域完全蚀刻掉，从而暴露出封装材料508的底面。在一些实施例中，回蚀可能包括对一些金属轨迹线进行部分蚀刻。在一些实施例中，金属轨迹线522的一部分可能被涂上一层可焊接材料528，如金属镀层528。在一些是实例中，金属轨迹线522底面的一部分可能被回蚀，从而与封装材料508的底面大致贴合。在某些实施例中，在金属轨迹线522底面的一部分涂上了保护涂层529。
图6A-C是一个无引脚IC封装元件600的不同角度视图。图6A是IC封装元件600的俯视图。为了便于描述，图中没有显示引线，而只显示了封装材料608的轮廓和LF上粘贴IC芯片604的晶粒粘贴区(DA区)602的轮廓。在本实施例中，外排端点的焊接区616直接位于其所对应的接点区606(如阴影线所示)的上方，且通过金属轨迹线622与内排的端点形成电连接，内排端点的焊接区618位于其所对应的接点区606横向较远的位置，并与其通过金属轨迹线622形成电连接。可以看到，内排焊接区618可能连接到DA区602下方的接点区606。
图6B是图6A中的IC封装元件600在线A-A处的剖面图。IC封装元件600包括IC芯片604，IC芯片604的下方有一粘合层610，用来将IC芯片604固定到金属轨迹线622上。在某些实施例中，粘合层610可能由绝缘的银胶材料组成。在某些实施例中，IC芯片604与外排的焊接区616通过引线612形成电连接，并与内排的焊接区618之间通过引线614形成电连接。在某些实施例中，金属轨迹线622构成了内排焊接区618和DA区602下方接点区606之间的电连接通道。可以看到封装材料608(图中阴影所示部分)将IC芯片604以及引线612和614封装起来。此外，还可看到封装材料608位于IC芯片604下方的金属轨迹线622之间的区域。
图6C是IC封装元件600的仰视图。IC封装元件600的底面包括封装材料608(图中无阴影的部分)、金属轨迹线622(图中阴影所示部分)和接点区606(图中无阴影的正方形)。在某些实施例中，位于IC封装元件600周边的接点区606之间被相互间隔开。在某些实施例中，由于这些接点没有轨迹延伸到外面，所以其间距可能大于或等于PCB设计规格要求的最小间距。在某些实施例中，金属轨迹线622提供了内排焊接区618与位于DA区下方接点区606之间的电连接，使内排焊接区618的间距小于PCB设计规格要求的最小间距，同时也使接点区606之间可至少保持彼此间的最小间距。从而使安装在LF上的IC芯片和安装了IC封装元件600的PCB之间建立更多的电连接。
图7A和B所示为IC封装元件700的两个实施例的俯视图。为了便于描述，图中将没有显示引线，而只显示了封装材料708和IC芯片704的轮廓。在本实施例中，通过对LF顶面蚀刻形成了凹槽726，从而确定了焊接区716和718，以及金属轨迹线722。此外，蚀刻后形成的凹槽726还确定了晶粒粘贴垫(DAP，Die Attach Pad)702。在不同实施例中，DAP702可能位于LF顶面的中部，即安装IC芯片的位置。在本实施例中，晶粒粘贴区(DA区)是LF上用于安装IC芯片的部位，其可能包括DAP702和一部分金属轨迹线722。在一些实施例中，最好包含DAP702，以对IC芯片704进行散热，同时能为IC芯片704提供支撑结构，和/或为IC芯片704提供电气接地。例如，本实施例里，通过将金属轨迹线722a电连接到DAP702上提供额外的接地。
如图7B所示为具有两排焊接区的IC封装元件700的实施例示意图。在本实施例中，第一排焊接区的尺寸和形状与第二排焊接区的尺寸和形状不同。为了便于描述，图中没有显示引线，而只显示了封装材料708和IC芯片704的轮廓。细节B是位于IC封装元件700接点区外排的三个焊接区的放大图。细节C是位于IC封装元件700两排接点区的三个焊接区的放大图。如细节B所示，焊接区716直接位于接点区706的上方，因此焊接区716中线之间必须间隔与接点区706中心距相同的距离。从细节C可以看到，当接点区中的一个接点区没有直接位于焊接区718下方时，焊接区716和718间的距离可以更近。在某些实施例中，在DAP702上构建了通道703，使封装材料能够顺利地流入，否则封装材料将不能或很难到达所需部位。
图7I-J所示为细节B和细节C的放大图。图7C-H所示的是细节B和细节C制作过程中不同阶段的侧视图。图7C中，在LF724上形成的凹槽726，确定了焊接区716的位置。另外，LF724的顶面和底面被选择性地镀上一层物质。在图7D中，封装材料708浇注在LF724的顶部以及凹槽726内。在图7E中，选择性蚀刻掉LF的底面，从而使得焊接区716彼此之间隔离开，并确定了接点区706。如本实施例所示，焊接区716和接点区706的直径大致相同。即使焊接区716的直径减小，特定区域内的焊接区716的数量仍然受到位于此区域内接点区706数量的限制。
如图7B中细节C是焊接区之一718的放大图，其金属轨迹线位于两个焊接区716之间，焊接区716包括直接位于其下方的接点区706。在本实施例中，焊接区716和718位于LF的顶面并呈长方形，而接点区706则位于LF的底面并呈圆形。如细节C所示，内排的焊接区716和718的宽度相对于外排焊接区来说减小了(如细节B所示)。因为焊接区716和718的宽度小于接点区706的宽度，所以焊接区716和718之间可以比接点区706之间放置得更接近。此外，为了减少焊接区716和718之间的距离，焊接区718下方将不直接放置接点区706。
如图7F-H所示的是IC封装元件700在具体实施例中构建焊接区716和718，以及接点区706的各阶段示意图。图7F所示的是LF724的一部分，LF724的顶面进行了部分蚀刻，构建了凹槽726，并进一步确定了焊接区716、焊接区718以及从焊接区718延伸出的金属轨迹线722(细节C中即有一金属轨迹线)。在图7G中，封装材料708用来覆盖焊接区和凹槽。此外，在LF724的底面位于焊接区716下方的位置选择性地镀上金属镀层728。在图7H中，对LF724的底面进行选择性回蚀后，位于焊接区718下方的LF724被部分移除，从而使焊接区718与焊接区716及其下方的接点区706电隔离。
部分蚀刻的步骤可以由多次蚀刻加工来完成，例如，在LF724顶面涂一层可光成像阻蚀剂，像可光成像银胶。光阻剂可以被旋转涂布在LF724上，然后附上一层光掩膜，暴露在紫外光下，其中，暴露的部分会被去除。因此，阻蚀剂根据图案在LF724的顶面确定了凹槽726的位置。接下来，通过浸泡或加压喷雾，对LF724进行蚀刻，部分形成焊接区716、718以及金属轨迹线722。然后，阻蚀剂可用常规方法去除。
图8A-D为各实施例的LF顶面的焊接区如何通过金属轨迹线与具有不同构型的IC封装元件连接的图例。图8A为装有两块IC芯片804a和804b的IC封装元件800实施例，其中一块芯片叠在另一块上，可以看到底部的IC芯片804b被安装在IC芯片下方延伸出的金属轨迹线上。图8B为装有两块IC芯片804a和804b的IC封装元件800实施例，其中一块芯片叠在另一块上。如下面的更详细的描写中所述，底部的IC芯片804b为倒晶封装构型。图8C为装有两块IC芯片804a和804b的IC封装元件800实施例，两块芯片并排安装在多芯片模块(multi-chip module，MCM)中。虽然本实施例只包含两块IC芯片804a和804b，但可在LF上安装大量IC芯片。图8D为系统封装构型的IC封装元件800实施例，LF上装有IC芯片804及一个或多个无源组件830，如电阻或电容。虽然本实施例只包括一块IC芯片804和两个无源组件830，但是仍可在IC封装元件中的LF上安装大量IC芯片和无源组件。
过去，在两块IC芯片间、IC芯片与其它接点和/或无源组件间使用接点和/或无源组件是昂贵的，因为其连接到PCB的接点被其它接点所包围。为了提供连接到接点的独立电气通路，PCB需要第二层、第三层，这样显著增加了生产成本。使用金属轨迹线连接焊接盘与其它位置，如DA区下方，可以建立独立的电连接，无需因使用多层PCB而增加费用。
图9A-C中，图9B的IC封装元件的实施例具有两块IC芯片904a和904b，两块芯片倒晶封装在一起。从图9B中可以看到，底部的IC芯片904b通过倒晶焊接技术直接贴附在电接点上，例如，其中IC芯片904b的焊接盘包括其上的焊接凸点，该焊接凸点可以回流以结合LF上电接点的上表面。本实施例中，顶部的IC芯片904a可以通过引线连接到位于IC封装元件900周边的大量焊接区916。金属轨迹线可以用于在大量焊接区916和倒装芯片(flip chip，FC)的接点之间形成电连接。图9C是IC封装元件900的仰视图。金属轨迹线922(图中阴影部分所示)可以将IC封装元件900周边的焊接区与底部的IC芯片904b下方的FC接点相连接。
图10A和10B中，图10A是用于建立有气腔IC封装元件的LF1024的实施例，图10B是已完成的有气腔IC封装元件1000的实施例，其LF1024上安装了一块IC芯片1004。在图10A中，对LF1024的顶面进行部分蚀刻，从而构建凹槽1026并因此确定了位于凹槽1026之间的金属轨迹线1022。在金属轨迹线1022顶面的焊接区和LF1024底面的接点区上镀有金属镀层1028。在LF1024上还使用了封装材料1008，因此凹槽中填入了封装材料1008，且形成了从LF1024边缘向上延伸的两个立柱。图10B所示已完成的有气腔IC封装元件1000是由图10A中的LF1024构建的，LF1024上粘合了IC芯片1004，并且通过引线将IC芯片1004与LF1024的焊接区相连接。此外，横跨立柱顶端有一个盖子，将IC封装元件密封起来，在IC芯片1004上方建立气腔。盖子由固体材料制造，比如：金属，塑料，玻璃，陶瓷，或其它固体材料，或者这些材料中的一种或多种的组合。此外，LF1024的底面已被蚀刻，以隔离接点区和金属轨迹线。
图11A和11B为用在IC封装元件中的LF1124的实施例。图11A为LF1124的俯视图，其中凹槽1126(图中阴影所示区域)通过选择性蚀刻法在远离LF1124的部分顶面处根据预定样式构。LF1124上凹槽1126之间未被蚀刻的部分是金属轨迹线1118，其被用于为安装在其上的IC电路提供支持和/或为LF1024顶面的焊接区和LF1024底面的接点区之间的线路信号提供电气通路。图11B是LF1024的仰视图，其中金属轨迹线(图中阴影所示区域)为LF1024顶面的焊接区和LF1024底面的接点区1106提供线路。通常，LF1024上接点区1106的位置由将要安装IC封装元件的PCB上接点的样式决定。例如，本实施例中，要求接点区1106在IC封装元件周围等间距排列成两排。可以看到，使用复杂的金属轨迹线样式允许从非等间距焊接区向两排等间距接点区传递电信号，而以前使用金属LF是没有这一能力的。
除上述图11A-B相关改进之外，使用金属轨迹线允许接点区远离它们各自的焊接区，同时也显著增加了可用于规定的IC封装元件和芯片尺寸组合的I/O连接数目，而且也允许IC芯片增加的尺寸连同规定的IC封装元件尺寸一起被使用。在图12A-H中，有一张给出了对于各种IC封装元件构型典型的可用I/O连接数的表，以及各种IC封装元件构型的实例。图12A所示表为对于具有0.5mm接触点间距的三种不同类型5x5mm IC封装元件，当三种不同尺寸IC芯片安装在其中时，可用的I/O连接的典型数目。这三类IC封装元件是：QFN封装元件(图12B和12C)、TAPP封装元件(图12D和12E)和HLA封装元件(图12F-H)。如表中第一列的模具尺寸所示，4x4mm的IC芯片太大了，而不能被装在5x5mm的QFN或TAPP型IC封装元件中。然而，利用金属轨迹线在远离焊接区处放置接点区，允许4x4mm的IC芯片用在5x5mm的HLA型IC封装元件中，关于此的一个实例如图12F所示。如表所示，典型的实施例可能有大约64个I/O连接，用于连接PCB上的两排接点。虽然此表用了4x4mm IC芯片的实施例，但甚至更大的IC芯片也可能装在5x5mm的HLA型IC封装元件上。
下一列所示为当3x3mm IC芯片连同三种不同类型5x5mm IC封装元件一起使用时，I/O连接的典型数目。当一块3x3mm的IC芯片与QFN或TAPP类型IC封装元件一起使用时，在IC电路周围仅有够一排接点，仅32或36个I/O连接的空间供可用。当同样的的IC芯片和封装元件尺寸组合与HLA型IC封装元件一起使用时，可用I/O连接的数量升至88个，有4排接点区可用于连接到PCB。
最后一列所示为当2x2mm IC芯片连同三种不同类型5x5mm IC封装元件一起使用时，I/O连接的典型数目。当一块2x2mm的IC芯片与QFN或TAPP类型IC封装元件一起使用时，在IC电路周围可有多达两排的接点区，分别通过最多44和60个I/O连接与PCB相连。当同样的的IC芯片和封装元件尺寸组合与HLA型IC封装元件一起使用时，可用I/O连接的数量升至100个，有多达5排的接点区(1201-1205所示)可用于连接到PCB。
图12A的表格列出了对于HLA型封装元件中IC芯片、接点间距和封装元件尺寸的具体组合，其可用I/O连接的具体数量，这只是起到说明的作用。这些数量不应被理解为可用接点的最大数量。例如，在不同的设计中，内部安装了一个2x2mm IC芯片的5x5mm HLA型IC封装元件，其I/O接口的数量可能是图12H中数量的大约两倍。其它不同的实施例中，也可能会超过这些数量。此外，虽然表格只给出了三种5x5mm IC型号的数量对比，但HLA型IC封装元件相对于另外两种型号的IC封装元件，其I/O接口数量的显著增加，可以理解为在其它尺寸大于5x5mm或小于5x5mm的IC封装元件中，接口数量也会显著增加。
下面对图12H进行特别说明，该实施例所示为在焊接区表面利用金属轨迹线连接焊接区和接点区。从IC芯片附近的焊接区到离IC芯片较远的接点区进行布线，就可以使用较短的引线来连接IC芯片与焊接区。这样减少了连接次数，从而显著节约了成本，尤其是当引线采用昂贵的金属(如：金)时。图12H中可以看待，不同的实施例可以采用表面布线和内部布线相结合的方式。在某些实施例中，可能只采用表面布线的方式，而其它某些实施例可能只采用内部布线的方式。
虽然通过附图和前面的详细描述对本发明方法和系统的各个实施例进行了说明，但是应该理解本发明不仅限于在此公开的实施例，而可以在不违背本发明实质的前提下进行多种重排、修正和等效变换。

Claims (30)

1.一种无引脚集成电路元件，包括：
金属引线框，所述金属引线框有顶面和底面，并包括大量从顶面延伸到底面的端点，每个所述端点都包括位于顶部表面的焊接区、位于底面的接点区和一连接两者的金属轨迹线；
IC芯片，所述IC芯片安装在金属引线框的顶面，并包括大量焊接盘；
大量引线，所述每根引线都与一焊接区及一焊接盘连接；
封装材料，其覆盖所述IC芯片、所述大量引线和所述大量端点中每个端点的至少一部分；
其特征在于，所述大量端点的接点区没有被封装材料完全封装；
所述大量端点中至少有一个端点包括电连接到焊接区的金属轨迹线，该焊接区从接点区横向延伸；
因此不再需要与金属引线框顶面垂直的导线来连接焊接区和接点区，而是通过金属轨迹线来对焊接区和接点区进行电连接。
2.根据权利要求1所述的无引脚集成电路元件，其特征在于，至少有一个所述端点包括金属轨迹线，该金属轨迹线在位于IC芯片下方的接点区和位于IC芯片周边的焊接区之间形成电连接。
3.根据权利要求2所述的无引脚集成电路元件，其特征在于，包括位于金属轨迹线和IC芯片之间的粘合层。
4.根据权利要求1所述的无引脚集成电路元件，其特征在于，从接点区横向延伸的焊接区是以下列方式中的一种或多种方式实现的：相对于IC芯片，从接点区向外排布；相对于IC芯片，从接点区向内排布；排布在与IC芯片边缘平行的位置。
5.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述至少一个端点上焊接区的表面积小于连接到焊接区的接点区的表面积。
6.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述大量端点中第一端点焊接区和所述大量端点中第二端点焊接区的中心距小于所述第一端点接点区和所述第二端点接点区的中心距。
7.根据权利要求1所述的无引脚集成电路元件，包括：
所述大量端点中的第一端点，所述第一端点有一连接到第一接点区的第一焊接区，所述接点区直接位于其底面；
所述大量端点中的第二端点，所述第二端点有一连接到第二接点区的第一焊接区，所述接点区直接位于其底面；
所述大量端点中的第三端点，所述第三端点有一连接到第三接点区的第一焊接区；
其特征在于，第三焊接区位于第一焊接区和第二焊接区之间；且
所述第三接点区在第一接点区和第二接点区之间区域横向延伸。
8.根据权利要求7所述的无引脚集成电路元件，包括：
所述大量端点中的第四端点；所述第四端点有一连接到第四接点区的第四焊接区；
其特征在于，所述第四焊接区位于第一焊接区和第二焊接区之间；且
所述第四接点区在第一接点区和第二接点区之间区域横向延伸。
9.根据权利要求1所述的无引脚集成电路元件，其特征在于，包括：
所述大量端点中的第一端点，所述第一端点有一第一接点区；
所述大量端点中的第二端点，所述第二端点有一与第一接点区邻近的第二接点区；以及
所述大量端点中的第三端点，所述第三端点有一从第一接点区延伸到第二接点区的金属轨迹线。
10.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述金属引线框的底面被选择性蚀刻，从而使金属引线框底面大致与封装材料底面贴合。
11.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述金属引线框的底面被选择性蚀刻，从而使金属引线框底面的至少一部分大致与封装材料底面贴合。
12.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述金属引线框的底面被选择性蚀刻，从而使金属引线框位于封装材料内部的至少一部分被移除。
13.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述金属轨迹线的底面被选择性蚀刻，从而使金属轨迹线位于封装材料内部的至少一部分被移除。
14.根据权利要求1所述的无引脚集成电路元件，包括：
金属镀层，所述金属镀层位于所述焊接区中至少一个的顶面；且
其特征在于，金属引线框位于金属镀层下的至少一部分被蚀刻移除。
15.根据权利要求14所述的无引脚集成电路元件，其特征在于，所有的位于金属镀层下的金属引线框被充分地蚀刻移除。
16.根据权利要求1所述的无引脚集成电路元件，其特征在于：
所述第大量焊接区中的第一焊接区的宽度小于5密耳；
所述第一焊接区边缘和第二焊接区边缘之间的距离小于5密耳。
17.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述至少一个金属轨迹线的部分底面涂有一层保护材料。
18.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述保护材料为环氧树脂、氧化物或阻焊剂。
19.根据权利要求1所述的无引脚集成电路元件，包括在接点区底面形成的阻焊保护层；其特征在于，所述阻焊保护层从以下几组中选取：
镍、钯和金的电镀叠层；
镍和金的电镀叠层；
镍和银的电镀叠层；
银、金或镍和金的金属镀层；
锡的电镀层或置换镀层；
由锡和铅组成的焊料涂层，或锡合金焊料；
由锡和铅组成的焊球，或锡合金焊料；以及
具有有机可焊性防腐剂涂层的裸铜。
20.根据权利要求1所述的无引脚集成电路元件，其特征在于，所述金属引线框的顶面包括晶粒粘贴垫；且至少一部分IC芯片被安装在晶粒粘贴垫上。
21.根据权利要求1所述的无引脚集成电路元件，其特征在于，包括安装到所述IC芯片上，并与金属引线框电连接的一个或多个IC芯片。
22.一种制造无引脚集成电路元件的方法，包括：
对金属引线框的顶面部分蚀刻形成凹槽；所述凹槽显露出大量金属轨迹线的上部，所述大量金属轨迹线中的每个金属轨迹线都有一位于其上部的焊接区；
在金属引线框上安装一IC芯片；
通过引线对IC芯片和焊接区进行电连接；
应用成型材料覆盖IC芯片、引线和大量金属轨迹线并填充金属引线框的凹槽；
对金属引线框的底面进行选择性地蚀刻来使所述大量金属轨迹线中的每个金属轨迹线彼此间隔开，所述大量金属轨迹线中的每个金属轨迹线有一位于其下表面的接点区，并且没有被封装材料完全覆盖；并且
其特征在于，至少一个所述金属轨迹线包括从焊接区横向延伸的接点区，使得不需要垂直金属引线框顶面的导线来连接接点区和焊接区。
23.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，所述金属轨迹线底面的至少一部分被蚀刻掉，以充分与封装层的底面贴合。
24.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，包括：将所述金属轨迹线下表面的至少一部分涂上保护层。
25.根据权利要求24所述的制造无引脚集成电路元件的方法，其特征在于，所述保护层包括以下涂层中的一种或多种：抗氧化涂层、环氧树脂涂层和保护油墨。
26.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，所述金属引线框底面的至少一部分被蚀刻掉，以充分与封装层的底面贴合。
27.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于：
所述IC芯片被安装在金属引线框的晶粒粘贴区上；
所述晶粒粘贴区与封装层底面之间构成第一距离，所述接点区与成型层的底面构成第二距离；且
所述第一距离小于第二距离。
28.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，在所述封装材料的内部，至少一个所述金属轨迹线底面的至少一部分被蚀刻掉。
29.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，包括：
在金属引线框的顶面部分蚀刻出通道；且
通过所述通道，将一部分所述封装材料注塑在金属引线框和IC芯片之间，以使得封装材料是隔离的并且不能到达部分凹槽。
30.根据权利要求22所述的制造无引脚集成电路元件的方法，其特征在于，包括：从一条多单元引线框中分割成独立的无引脚IC封装元件。
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CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN102280431A (zh) * 2011-08-01 2011-12-14 日月光半导体制造股份有限公司 具有保护层的半导体封装及其制作方法
CN102569101A (zh) * 2010-12-15 2012-07-11 南茂科技股份有限公司 无外引脚封装结构及其制作方法
CN102738016A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于框架载体开孔的aaqfn产品的二次塑封制作工艺
CN102738017A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于喷砂的aaqfn产品的二次塑封制作工艺
CN102738009A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺
CN102779763A (zh) * 2012-06-05 2012-11-14 华天科技（西安）有限公司 一种基于腐蚀的aaqfn产品的二次塑封制作工艺
CN102800660A (zh) * 2011-05-26 2012-11-28 英飞凌科技股份有限公司 模块和制造模块的方法
CN102891137A (zh) * 2011-07-19 2013-01-23 矽品精密工业股份有限公司 半导体封装件
CN103021883A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于腐蚀塑封体的扁平封装件制作工艺
CN103021875A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于aaqfn框架产品二次塑封的扁平封装件制作工艺
CN103021994A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN103021882A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于磨屑塑封体的扁平封装件制作工艺
CN103531565A (zh) * 2012-07-03 2014-01-22 乐依文半导体(东莞)有限公司 具有裸片附接焊盘锁定特征的热无引线阵列封装
CN104319269A (zh) * 2013-05-27 2015-01-28 德克萨斯仪器股份有限公司 多级引线框架

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8461694B1 (en) * 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US8531022B2 (en) * 2009-03-06 2013-09-10 Atmel Corporation Routable array metal integrated circuit package
WO2010099673A1 (en) 2009-03-06 2010-09-10 Kaixin Inc. Leadless integrated circuit package having high density contacts
US7858443B2 (en) * 2009-03-09 2010-12-28 Utac Hong Kong Limited Leadless integrated circuit package having standoff contacts and die attach pad
KR101753416B1 (ko) 2009-04-03 2017-07-19 카이씬, 인코포레이티드 Ｉｃ 패키지용 리드프레임 및 제조방법
US20100314728A1 (en) * 2009-06-16 2010-12-16 Tung Lok Li Ic package having an inductor etched into a leadframe thereof
US9449900B2 (en) 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
WO2011026261A1 (en) 2009-09-02 2011-03-10 Tunglok Li Ic package and method for manufacturing the same
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US20110248392A1 (en) * 2010-04-12 2011-10-13 Texas Instruments Incorporated Ball-Grid Array Device Having Chip Assembled on Half-Etched metal Leadframe
US8455304B2 (en) * 2010-07-30 2013-06-04 Atmel Corporation Routable array metal integrated circuit package fabricated using partial etching process
US8476772B2 (en) 2010-09-09 2013-07-02 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with recesses for capturing bumped semiconductor die
US8304277B2 (en) 2010-09-09 2012-11-06 Stats Chippac, Ltd. Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking
TWI420630B (zh) * 2010-09-14 2013-12-21 Advanced Semiconductor Eng 半導體封裝結構與半導體封裝製程
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8735224B2 (en) 2011-02-14 2014-05-27 Stats Chippac Ltd. Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US8557638B2 (en) 2011-05-05 2013-10-15 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
US8633063B2 (en) 2011-05-05 2014-01-21 Stats Chippac Ltd. Integrated circuit packaging system with pad connection and method of manufacture thereof
US9275877B2 (en) 2011-09-20 2016-03-01 Stats Chippac, Ltd. Semiconductor device and method of forming semiconductor package using panel form carrier
US8513788B2 (en) 2011-12-14 2013-08-20 Stats Chippac Ltd. Integrated circuit packaging system with pad and method of manufacture thereof
US9312194B2 (en) 2012-03-20 2016-04-12 Stats Chippac Ltd. Integrated circuit packaging system with terminals and method of manufacture thereof
US8569112B2 (en) * 2012-03-20 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof
WO2013165352A1 (en) * 2012-04-30 2013-11-07 Hewlett-Packard Development Company, L.P. Socket with routed contacts
US9717146B2 (en) 2012-05-22 2017-07-25 Intersil Americas LLC Circuit module such as a high-density lead frame array (HDA) power module, and method of making same
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US8916422B2 (en) 2013-03-15 2014-12-23 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
JP2014203861A (ja) * 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
CN103390563B (zh) * 2013-08-06 2016-03-30 江苏长电科技股份有限公司 先封后蚀芯片倒装三维系统级金属线路板结构及工艺方法
JP6494341B2 (ja) 2015-03-13 2019-04-03 株式会社ジャパンディスプレイ 表示装置
US10546847B2 (en) * 2015-03-27 2020-01-28 Fairchild Semiconductor Corporation Substrate interposer on a leadframe
US9728510B2 (en) 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate
JP6221184B2 (ja) * 2015-07-21 2017-11-01 本田技研工業株式会社 自動二輪車の車体フレーム構造
JP6222852B2 (ja) * 2015-07-21 2017-11-01 本田技研工業株式会社 自動二輪車の車体フレーム構造
US9922843B1 (en) 2015-11-10 2018-03-20 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
JP2017147272A (ja) * 2016-02-15 2017-08-24 ローム株式会社 半導体装置およびその製造方法、ならびに、半導体装置の製造に使用されるリードフレーム中間体
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US11094633B2 (en) * 2016-06-30 2021-08-17 Intel Corporation Bridge die design for high bandwidth memory interface
JP6644978B2 (ja) * 2016-07-25 2020-02-12 大口マテリアル株式会社 半導体素子搭載用基板及び半導体装置、並びにそれらの製造方法
US9972558B1 (en) 2017-04-04 2018-05-15 Stmicroelectronics, Inc. Leadframe package with side solder ball contact and method of manufacturing

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5468994A (en) * 1992-12-10 1995-11-21 Hewlett-Packard Company High pin count package for semiconductor device
JP2735509B2 (ja) 1994-08-29 1998-04-02 アナログ デバイセス インコーポレーテッド 改善された熱放散を備えたｉｃパッケージ
US5661337A (en) * 1995-11-07 1997-08-26 Vlsi Technology, Inc. Technique for improving bonding strength of leadframe to substrate in semiconductor IC chip packages
US5866939A (en) * 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
CN1222252A (zh) * 1996-04-18 1999-07-07 德塞拉股份有限公司 制造半导体封装的方法
US6001671A (en) 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
SG60102A1 (en) * 1996-08-13 1999-02-22 Sony Corp Lead frame semiconductor package having the same and method for manufacturing the same
TW351008B (en) * 1996-12-24 1999-01-21 Matsushita Electronics Corp Lead holder, manufacturing method of lead holder, semiconductor and manufacturing method of semiconductor
JPH10200009A (ja) * 1997-01-08 1998-07-31 Dainippon Printing Co Ltd リードフレーム部材とリードフレーム部材の製造方法
US6670222B1 (en) * 1997-06-14 2003-12-30 Jds Uniphase Corporation Texturing of a die pad surface for enhancing bonding strength in the surface attachment
KR100300666B1 (ko) * 1997-08-04 2001-10-27 기타지마 요시토시 수지밀봉형반도체장치와거기에사용되는회로부재및회로부재의제조방법
JPH1168006A (ja) * 1997-08-19 1999-03-09 Mitsubishi Electric Corp リードフレーム及びこれを用いた半導体装置及びこれらの製造方法
JP3884552B2 (ja) * 1998-01-06 2007-02-21 大日本印刷株式会社 半導体装置とそれに用いられる回路部材および半導体装置の製造方法
US6229200B1 (en) * 1998-06-10 2001-05-08 Asat Limited Saw-singulated leadless plastic chip carrier
US6294100B1 (en) * 1998-06-10 2001-09-25 Asat Ltd Exposed die leadless plastic chip carrier
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US6498099B1 (en) * 1998-06-10 2002-12-24 Asat Ltd. Leadless plastic chip carrier with etch back pad singulation
US6585905B1 (en) * 1998-06-10 2003-07-01 Asat Ltd. Leadless plastic chip carrier with partial etch die attach pad
US7270867B1 (en) * 1998-06-10 2007-09-18 Asat Ltd. Leadless plastic chip carrier
US7247526B1 (en) * 1998-06-10 2007-07-24 Asat Ltd. Process for fabricating an integrated circuit package
JP3764587B2 (ja) * 1998-06-30 2006-04-12 富士通株式会社 半導体装置の製造方法
US6281568B1 (en) * 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
JP3780122B2 (ja) 1999-07-07 2006-05-31 株式会社三井ハイテック 半導体装置の製造方法
JP2001077287A (ja) * 1999-09-06 2001-03-23 Mitsubishi Electric Corp 半導体装置用リードフレーム
EP1122778A3 (en) * 2000-01-31 2004-04-07 Sanyo Electric Co., Ltd. Circuit device and manufacturing method of circuit device
US6306685B1 (en) 2000-02-01 2001-10-23 Advanced Semiconductor Engineering, Inc. Method of molding a bump chip carrier and structure made thereby
US6238952B1 (en) * 2000-02-29 2001-05-29 Advanced Semiconductor Engineering, Inc. Low-pin-count chip package and manufacturing method thereof
US6372539B1 (en) * 2000-03-20 2002-04-16 National Semiconductor Corporation Leadless packaging process using a conductive substrate
JP3759572B2 (ja) * 2000-03-28 2006-03-29 三洋電機株式会社 半導体装置
JP3883784B2 (ja) * 2000-05-24 2007-02-21 三洋電機株式会社 板状体および半導体装置の製造方法
JP3500362B2 (ja) * 2001-02-14 2004-02-23 松下電器産業株式会社 樹脂封止型半導体装置及びその製造方法
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
JP3470111B2 (ja) * 2001-06-28 2003-11-25 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
SG120858A1 (en) * 2001-08-06 2006-04-26 Micron Technology Inc Quad flat no-lead (qfn) grid array package, methodof making and memory module and computer system including same
US7102216B1 (en) * 2001-08-17 2006-09-05 Amkor Technology, Inc. Semiconductor package and leadframe with horizontal leads spaced in the vertical direction and method of making
US6664615B1 (en) * 2001-11-20 2003-12-16 National Semiconductor Corporation Method and apparatus for lead-frame based grid array IC packaging
JP4173346B2 (ja) * 2001-12-14 2008-10-29 株式会社ルネサステクノロジ 半導体装置
KR100989007B1 (ko) * 2002-04-11 2010-10-20 엔엑스피 비 브이 반도체 디바이스
SG105544A1 (en) 2002-04-19 2004-08-27 Micron Technology Inc Ultrathin leadframe bga circuit package
US7799611B2 (en) * 2002-04-29 2010-09-21 Unisem (Mauritius) Holdings Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6777265B2 (en) 2002-04-29 2004-08-17 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US6940154B2 (en) * 2002-06-24 2005-09-06 Asat Limited Integrated circuit package and method of manufacturing the integrated circuit package
JP2004071670A (ja) * 2002-08-02 2004-03-04 Fuji Photo Film Co Ltd Ｉｃパッケージ、接続構造、および電子機器
US7309923B2 (en) 2003-06-16 2007-12-18 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
JP2004007022A (ja) * 2003-09-30 2004-01-08 Sanyo Electric Co Ltd 半導体装置
US7880282B2 (en) 2003-12-18 2011-02-01 Rf Module & Optical Design Ltd. Semiconductor package with integrated heatsink and electromagnetic shield
JP2005303039A (ja) * 2004-04-13 2005-10-27 Matsushita Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
KR101070890B1 (ko) * 2004-04-16 2011-10-06 삼성테크윈 주식회사 다열리드형 반도체 팩키지 제조 방법
US7411289B1 (en) * 2004-06-14 2008-08-12 Asat Ltd. Integrated circuit package with partially exposed contact pads and process for fabricating the same
US6995458B1 (en) * 2004-06-17 2006-02-07 Mindspeed Technologies, Inc. Cavity down no lead package
US7186588B1 (en) * 2004-06-18 2007-03-06 National Semiconductor Corporation Method of fabricating a micro-array integrated circuit package
US7064419B1 (en) * 2004-06-18 2006-06-20 National Semiconductor Corporation Die attach region for use in a micro-array integrated circuit package
US7095096B1 (en) * 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
US7161232B1 (en) * 2004-09-14 2007-01-09 National Semiconductor Corporation Apparatus and method for miniature semiconductor packages
US7217991B1 (en) * 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
JP4091050B2 (ja) * 2005-01-31 2008-05-28 株式会社三井ハイテック 半導体装置の製造方法
WO2006105734A1 (en) * 2005-04-07 2006-10-12 Jiangsu Changjiang Electronics Technology Co., Ltd. A packaging substrate with flat bumps for electronic devices and method of manufacturing the same
KR100618898B1 (ko) 2005-05-24 2006-09-01 삼성전자주식회사 리드 본딩시 크랙을 방지하는 테이프 패키지
KR101146973B1 (ko) * 2005-06-27 2012-05-22 페어차일드코리아반도체 주식회사 패키지 프레임 및 그를 이용한 반도체 패키지
JP3947750B2 (ja) 2005-07-25 2007-07-25 株式会社三井ハイテック 半導体装置の製造方法及び半導体装置
WO2007018237A1 (ja) * 2005-08-10 2007-02-15 Mitsui High-Tec, Inc. 半導体装置及びその製造方法
JP4032063B2 (ja) 2005-08-10 2008-01-16 株式会社三井ハイテック 半導体装置の製造方法
US7361977B2 (en) 2005-08-15 2008-04-22 Texas Instruments Incorporated Semiconductor assembly and packaging for high current and low inductance
CN100485893C (zh) 2005-09-09 2009-05-06 鸿富锦精密工业（深圳）有限公司 影像感测芯片封装的制程和结构
US7410830B1 (en) * 2005-09-26 2008-08-12 Asat Ltd Leadless plastic chip carrier and method of fabricating same
US8163604B2 (en) * 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
JP4199774B2 (ja) 2006-02-09 2008-12-17 京セラ株式会社 電子部品搭載構造体
CN101601133B (zh) * 2006-10-27 2011-08-10 宇芯（毛里求斯）控股有限公司 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US7834435B2 (en) 2006-12-27 2010-11-16 Mediatek Inc. Leadframe with extended pad segments between leads and die pad, and leadframe package using the same
JP5543058B2 (ja) * 2007-08-06 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置の製造方法
US7671452B1 (en) * 2007-08-17 2010-03-02 National Semiconductor Corporation Microarray package with plated contact pedestals
CN100464415C (zh) * 2007-09-13 2009-02-25 江苏长电科技股份有限公司 半导体器件无脚封装结构及其封装工艺
US7749809B2 (en) * 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8084299B2 (en) * 2008-02-01 2011-12-27 Infineon Technologies Ag Semiconductor device package and method of making a semiconductor device package
US7786557B2 (en) * 2008-05-19 2010-08-31 Mediatek Inc. QFN Semiconductor package
US8022516B2 (en) * 2008-08-13 2011-09-20 Atmel Corporation Metal leadframe package with secure feature
US7888259B2 (en) 2008-08-19 2011-02-15 Ati Technologies Ulc Integrated circuit package employing predetermined three-dimensional solder pad surface and method for making same
WO2010099673A1 (en) 2009-03-06 2010-09-10 Kaixin Inc. Leadless integrated circuit package having high density contacts
CN201655791U (zh) * 2009-06-04 2010-11-24 李同乐 高密度接点的无引脚集成电路元件

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569101A (zh) * 2010-12-15 2012-07-11 南茂科技股份有限公司 无外引脚封装结构及其制作方法
CN102569101B (zh) * 2010-12-15 2014-05-21 南茂科技股份有限公司 无外引脚封装结构及其制作方法
US9691687B2 (en) 2011-05-26 2017-06-27 Infineon Technologies Ag Module and method of manufacturing a module
CN102800660A (zh) * 2011-05-26 2012-11-28 英飞凌科技股份有限公司 模块和制造模块的方法
CN102231376A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN102231372A (zh) * 2011-06-30 2011-11-02 天水华天科技股份有限公司 多圈排列无载体ic芯片封装件及其生产方法
CN102231376B (zh) * 2011-06-30 2013-06-26 天水华天科技股份有限公司 多圈排列无载体双ic芯片封装件及其生产方法
CN102231372B (zh) * 2011-06-30 2014-04-30 天水华天科技股份有限公司 多圈排列无载体ic芯片封装件及其生产方法
CN102891137A (zh) * 2011-07-19 2013-01-23 矽品精密工业股份有限公司 半导体封装件
CN105448877A (zh) * 2011-08-01 2016-03-30 日月光半导体制造股份有限公司 半导体封装
CN105448877B (zh) * 2011-08-01 2019-08-23 日月光半导体制造股份有限公司 半导体封装
CN102280431A (zh) * 2011-08-01 2011-12-14 日月光半导体制造股份有限公司 具有保护层的半导体封装及其制作方法
CN102779763A (zh) * 2012-06-05 2012-11-14 华天科技（西安）有限公司 一种基于腐蚀的aaqfn产品的二次塑封制作工艺
CN102738009A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于刷磨的aaqfn框架产品扁平封装件制作工艺
CN102738017A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于喷砂的aaqfn产品的二次塑封制作工艺
CN102738016A (zh) * 2012-06-13 2012-10-17 华天科技（西安）有限公司 一种基于框架载体开孔的aaqfn产品的二次塑封制作工艺
CN103531565A (zh) * 2012-07-03 2014-01-22 乐依文半导体(东莞)有限公司 具有裸片附接焊盘锁定特征的热无引线阵列封装
CN103021882A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于磨屑塑封体的扁平封装件制作工艺
CN103021875A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于aaqfn框架产品二次塑封的扁平封装件制作工艺
CN103021883A (zh) * 2012-12-09 2013-04-03 华天科技（西安）有限公司 一种基于腐蚀塑封体的扁平封装件制作工艺
CN103021994A (zh) * 2012-12-28 2013-04-03 华天科技（西安）有限公司 一种aaqfn二次塑封与二次植球优化的封装件及其制作工艺
CN104319269A (zh) * 2013-05-27 2015-01-28 德克萨斯仪器股份有限公司 多级引线框架
US10804114B2 (en) 2013-05-27 2020-10-13 Texas Instruments Incorporated Methods for making a multilevel leadframe by etching a conductive sheet from two opposite sides

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