CN101840972B - Semiconductor photoelectric element structure of inverted chip type and making method thereof - Google Patents
Semiconductor photoelectric element structure of inverted chip type and making method thereof Download PDFInfo
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- CN101840972B CN101840972B CN200910119833A CN200910119833A CN101840972B CN 101840972 B CN101840972 B CN 101840972B CN 200910119833 A CN200910119833 A CN 200910119833A CN 200910119833 A CN200910119833 A CN 200910119833A CN 101840972 B CN101840972 B CN 101840972B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention relates to a semiconductor photoelectric element structure of an inverted chip type and a making method thereof. The making method comprises the following steps of: firstly, forming a sacrifice layer on an extensive substrate; forming a semiconductor luminous structure on the sacrifice layer; etching the semiconductor luminous structure; fixing a semiconductor photoelectric bare chip on the encapsulated substrate in the inverted chip mode, and then separating the extensive substrate by using a lift-off technology. The making method of the semiconductor photoelectric element structure of the inverted chip type has simple process, and the semiconductor photoelectric element made by using the making method has high luminous efficiency and good heat dispersion.
Description
Technical field
The present invention is about a kind of structure and manufacturing approach thereof of flip-chip type semiconductor photoelectric cell; Particularly relevant for after with flip chip nude film being fixed in base plate for packaging, again with structure and the manufacturing approach thereof of lift-off technology (Lift Off) with the semiconductor optoelectronic element of temporary transient extension separation.
Background technology
Light-emitting diode (Light Emitting Diode; Be called for short LED), can electric energy be converted into the electronic component of luminous energy for a kind of, and possess the characteristic of diode simultaneously.The special feature of light-emitting diode is to have only just to be understood luminously from the positive pole energising, when generally giving direct current, light-emitting diode can be stably luminous.If but connected alternating current, light-emitting diode could present the kenel of flicker.The frequency of flicker is decided according to the frequency of input AC electricity.The principle of luminosity of light-emitting diode is an applied voltage, makes electronics with after the hole combines in semiconductor, and the form of energy with light discharged.
For light-emitting diode, it is its biggest advantage that life-span length, lower calorific value and low power consumption, energy savings and minimizing are polluted.The application surface of light-emitting diode is very wide, but luminous efficiency is one of them problem that has much room for improvement, and is also perplexing popularizing of led lighting technology all the time.Luminous efficiency will improve, and will effectively increase light output efficiency.
The potted element of light-emitting diode can be divided into two kinds of horizontal cell and perpendicular elements.Please refer to Fig. 1 a and Fig. 1 b, it is the encapsulating structure comparison diagram of traditional routing joining technique and flip chip technology (fct).So-called horizontal cell is that the employed substrate of extension is nonconducting sapphire substrate, and its n type electrode 105 and p type electrode 107 be positioned at element same towards.Component package is mainly with routing joining technique (Wire Bonding) and flip chip technology (fct) (Flip Chip) dual mode.Shown in Fig. 1 a; The arrow that makes progress among Fig. 1 a is main light emission direction; Downward arrow is main heat dissipation direction, and the routing joining technique is that light-emitting diode nude film 123 directly is pasted on the base plate for packaging 115, utilizes metal wire 311 to electrically connect light-emitting diode nude film 123 and base plate for packaging 115 again.Shown in Fig. 1 b, the arrow that makes progress among Fig. 1 b is main light emission direction, and downward arrow is main heat dissipation direction, and flip chip technology (fct) is that light-emitting diode nude film 123 is inverted on projection 113, again by projection 113 and base plate for packaging 115 fixing and electric connections.The routing joining technique is the widest technology of using at present, but a large amount of volume production of its snatch.But flip chip technology (fct) disturbs on light-emitting area because of electrodeless and metal wire, thus flip chip technology (fct) relative can be higher than the brightness of routing joining technique.In addition, flip chip technology (fct) is with projection bed hedgehopping nude film, relative also good than the routing joining technique that directly is bonded on the base plate for packaging of its thermal diffusivity.
Please refer to Fig. 2, it is the perpendicular elements structure chart of prior art, and the arrow that makes progress among this figure is main light emission direction, and downward arrow is main heat dissipation direction.So-called perpendicular elements is the light emitting diode construction that development in recent years goes out, and its characteristic is to use preferable substrate of conductivity such as carborundum (SiC) replacement sapphire substrate instead, or with lift-off technology (Lift off) sapphire substrate is separated with ray structure.In addition; The opposite face that first electrode 215 of perpendicular elements can be positioned at element for n type electrode or p type electrode and second electrode 217 to; Wherein first electrode 215 be n type electrode then second electrode 217 be p type electrode, first electrode 215 be p type electrode then second electrode 217 be n type electrode.During encapsulation, first electrode 215 of an end can be directly and base plate for packaging 115 bind, 217 need of second electrode of the other end just can reach electric connection with metal wire 311 routing junctures.Perpendicular elements is better than the thermal diffusivity and the luminance of horizontal cell, especially removes substrate with lift-off technology, more makes the conductivity of element increase.Because an end second electrode 217 of perpendicular elements is formed on the light-emitting zone, when element was luminous, second electrode 217 can influence the luminous intensity of element because of covering light-emitting area.Especially at the element light-emitting area more hour, the relative dead area of its electrode is big more, and luminous intensity is influenced more.In theory for to avoid covering of electrode, change to encapsulate and to reach the good and brightness advantages of higher of thermal diffusivity, but its degree of difficulty is arranged on the technology with flip chip technology (fct).Please refer to Fig. 3 a, Fig. 3 b and Fig. 3 c, it is etching, peel off the rough schematic of epitaxial substrate and Flip-Chip Using.Shown in Fig. 3 a, after epitaxial substrate 101 forms a ray structure 309, on said ray structure 309, form one first electrode 215 again.Then be etched to ray structure 309 and expose n type conductive layer.Again by shown in Fig. 3 b, form second electrode 217 in n type conductive layer top with the mode of sputter, place second electrode 217 and first electrode, 215 tops to reach electric connection projection 113 individually again.Next remove said epitaxial substrate 101.Fig. 3 c then for the nude film cutting, forms other nude film, and dotted arrow is a cut direction among this figure.In fact, there is several sections to overcome in the said technology.First is an etching process.Because the actual (real) thickness ratio between the ray structure 309 and first electrode 215 can reach 1: 20 above gap, could arrive ray structure 309 after in etched process, wanting earlier first electrode 215 to be removed fully.So etching must be considered the thickness of first electrode, but often be difficult to be affectedly bashful the ray structure etched depth.Second portion is for forming the process of second electrode.Generally the mode with sputter forms electrode.Visible by Fig. 3 a, the position that forms second electrode 217 is a dark U type space 313.For the sputter technology, increased the degree of difficulty that it forms second electrode 217.The height that also comprises electrode when the requirement that forms second electrode 217 and first electrode 215 need with space etc. high, that second electrode 217 must keep with the distance of first electrode 215 and ray structure 309 just can not cause electrical short circuit and keep the cutting of back segment nude film, be in dark U type space 313 the formation electrode with regard to difficulty more.Third part is the thermal stress between first electrode 215 and the ray structure 309.The material of electrode is mainly metal material, and ray structure then is the III-V compounds of group.Common metal material coefficient of thermal expansion coefficient (Thermal expansion coefficient; TEC) thermal coefficient of expansion than GaN is high.Please refer to Fig. 3 b, when carrying out laser lift-off technology (Laser Lift Off; When LLO) removing epitaxial substrate 101, its temperature will arrive about 400 degree, and making easily wins produces thermal stress between electrode 215 and the ray structure 309, thereby cause distortion and ray structure 309 cracked of first electrode 215.
Therefore, the present invention provides a kind of flip-chip type semiconductor photoelectric element-packaging structure, in order to improve above-mentioned deficiency.
Summary of the invention
In view of the deficiency in the described background technology, in order to meet the demand in market, the technical problem that the present invention will solve provides a kind of flip-chip type semiconductor photoelectric element-packaging structure and manufacturing approach thereof, and its technology is simple, luminance is high, thermal diffusivity is good.
For solving the problems of the technologies described above; The present invention provides a kind of flip-chip type semiconductor photoelectric cell structure; Comprise: a base plate for packaging has a first surface and with respect to the second surface of first surface, wherein this first surface has one first weld pad and one second weld pad; One first projection is positioned on this first weld pad, and one second projection is positioned on this second weld pad; The semiconductor ray structure; Has a first surface and with respect to the second surface of first surface; Wherein this first surface comprises a n type electrode and a p type electrode, and this n type electrode and this first projection electrically connect, and this p type electrode and this second projection electrically connect; One insulating barrier, between this n type electrode and this p type electrode, this n type electrode of electrical isolation and this p type electrode; And a transparent adhesive tape material, between the first surface of the first surface of this base plate for packaging and this semiconductor light emitting structure, coat this first weld pad, this second weld pad, this first projection and this second projection.
For solving above-mentioned another technical problem, the present invention provides a kind of manufacturing approach of flip-chip type semiconductor photoelectric cell, and this method is: an epitaxial substrate is provided; Form a sacrifice layer on an epitaxial substrate; Form the semiconductor ray structure on said sacrifice layer, this semiconductor light emitting structure has a first surface and with respect to the second surface of first surface, this sacrifice layer is positioned at the second surface of this semiconductor light emitting structure; Form a n type electrode and a p type electrode on the first surface of this semiconductor light emitting structure; Be inverted this semiconductor light emitting structure on a base plate for packaging; This base plate for packaging has a first surface and with respect to the second surface of first surface, wherein this first surface has one first weld pad and one second weld pad, also comprises one first projection and one second projection on this base plate for packaging; This first projection is positioned on this first weld pad; This second projection is positioned on this second weld pad, and this n type electrode and this first projection electrically connect, and this p type electrode and this second projection electrically connect; Fill a transparent adhesive tape material between the first surface of the first surface of this base plate for packaging and semiconductor light emitting structure, coat this first weld pad, this second weld pad, this first projection and this second projection; The said sacrifice layer of etching is to peel off said epitaxial substrate.
Useful technique effect of the present invention is: the luminance of more general conventional semiconductors photoelectricity horizontal cell; Semiconductor optoelectronic element of the present invention is peeled off epitaxial substrate after encapsulating with flip chip technology (fct) again; The light that its element penetrates receives substrate and the electrode interference is few, so its luminance is higher than the luminance of general conventional semiconductors photoelectricity horizontal cell.In addition, semiconductor optoelectronic element is also good than the thermal diffusivity of general semiconductor optoelectronic element aspect thermal diffusivity.In addition, the process of semiconductor optoelectronic element of the present invention is simpler.
Description of drawings
Fig. 1 a and Fig. 1 b are the encapsulating structure comparison diagram of traditional routing joining technique and flip chip technology (fct);
Fig. 2 is the perpendicular elements structure chart of prior art;
Fig. 3 a to Fig. 3 c is etching, peel off the rough schematic of epitaxial substrate and Flip-Chip Using;
Fig. 4 is a main method flow chart of the present invention;
Fig. 5 a to Fig. 5 q is that each step of flip-chip type semiconductor photoelectric cell of the present invention forms sketch map (Fig. 5 a to Fig. 5 e is that first kind of each step that forms the sacrifice layer method of the present invention forms sketch map);
Fig. 6 a to Fig. 6 e is that second kind of each step that forms the sacrifice layer method of the present invention forms sketch map; And
Fig. 7 a to Fig. 7 e is that each step that the third forms the sacrifice layer method of the present invention forms sketch map.
Wherein, description of reference numerals is following:
101 epitaxial substrates, 121 cylinders
103 shades, 123 nude films
109 light-emitting zones 201 an III group-III nitride
111 Cutting platforms, 203 III-th family nitrides
113 projections 205 the 3rd III group-III nitride
115 base plate for packaging, 207 ohmic contact layers
117 weld pads, 209 insulating barriers
119 holes, 305 electronic barrier layers
211 transparent adhesive tape material 307p type conductive layers
213 protective layers, 309 ray structures
215 first electrodes, 311 metal wires
217 second electrode 313U type spaces
301n type conductive layer 303 luminescent layers
Embodiment
The present invention is a kind of flip-chip type semiconductor photoelectric element-packaging structure and manufacturing approach thereof in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, enforcement of the present invention is not defined in the specific details that the technical staff knew of optical semiconductor galvanic process.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these detailed descriptions, the present invention can also be embodied among other the embodiment widely, and scope of the present invention constrained not, and it is as the criterion with the scope that claims define.
The present invention provides a kind of flip-chip type semiconductor photoelectric element-packaging structure, comprises a base plate for packaging, has a first surface and with respect to the second surface of first surface.Wherein said first surface has one first weld pad and one second weld pad.One first projection is positioned on said first weld pad, and one second projection is positioned on said second weld pad.The semiconductor ray structure has a first surface and with respect to the second surface of first surface.Wherein said first surface comprises a n type electrode and a p type electrode.Said n type electrode and said first projection electrically connect.Said p type electrode and said second projection electrically connect.One insulating barrier, between said n type electrode and said p type electrode, electrical isolation said n type electrode and said p type electrode.And a transparent adhesive tape material is between the first surface of the first surface of said base plate for packaging and said semiconductor light emitting structure.Said transparent adhesive tape material coats said first weld pad, said second weld pad, said first projection and said second projection simultaneously.
Above-mentioned base plate for packaging can be printed circuit board (PCB) (Printed Circuit Board; PCB), BT resin printed circuit plate (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), high hot coefficient aluminium base (Metal Core Printed Circuit Board; MCPCB), flexible printed wiring board (Flexible Printed Circuit Board; Flexible PCB), ceramic substrate (Ceramic), silicon substrate.
Above-mentioned projection can be palladium ashbury metal (Pd/Tin).
Above-mentioned n type electrode can be titanium/aluminium/titanium/billon (Ti/Al/Ti/Au), chromium billon (Cr/Au) or plumbous billon (Pd/Au).
Above-mentioned p type electrode can be nickel billon (Ni/Au), platinum alloy (Pt/Au), chromium billon (Cr/Au), tungsten (W) or palladium (Pd).
Above-mentioned insulating barrier can be silicon dioxide (SiO
2), epoxy resin (Epoxy), silicon nitride (Si
3N
4), titanium dioxide (TiO2) or aluminium nitride (AlN).
Above-mentioned transparent adhesive tape material can be silicon dioxide (SiO
2), epoxy resin (Epoxy) or silicon nitride (Si
3N
4).
Above-mentioned protective layer can be silicon dioxide (SiO
2).
In addition, the present invention also provides a kind of manufacturing approach of flip-chip type semiconductor photoelectric cell structure, and comprising provides an epitaxial substrate.Form a sacrifice layer on said epitaxial substrate.Form the semiconductor ray structure on said sacrifice layer.Said semiconductor light emitting structure has a first surface and with respect to the second surface of first surface.Said sacrifice layer is positioned at the second surface of said semiconductor light emitting structure.Form a n type electrode and a p type electrode on the first surface of said semiconductor light emitting structure.The said semiconductor light emitting structure of upside-down mounting is on a base plate for packaging.Said base plate for packaging has a first surface and with respect to the second surface of first surface.Wherein said first surface has one first weld pad and one second weld pad.One first projection is positioned on said first weld pad, and one second projection is positioned on said second weld pad.Comprise one first projection and one second projection on the said substrate.Said n type electrode and said first projection electrically connect, and said p type electrode and said second projection electrically connect.Fill a transparent adhesive tape material between the first surface of the first surface of said base plate for packaging and semiconductor light emitting structure.Said transparent adhesive tape material coats said first weld pad, said second weld pad, said first projection and said second projection simultaneously.The said sacrifice layer of etching is to peel off said epitaxial substrate.
The step of the said sacrifice layer of above-mentioned formation on said epitaxial substrate comprises formation one the one III group-III nitride on said epitaxial substrate.Next the shade that forms a patterning is on a said III group-III nitride.The said III group-III nitride of etching, and the shade that removes said patterning again.
In addition, form the step of said sacrifice layer on said epitaxial substrate, comprise formation one the one III group-III nitride on said epitaxial substrate.The shade that forms a patterning is in a said III group-III nitride.Form one the 2nd III group-III nitride on the shade of said patterning, and the shade that removes said patterning forms a plurality of holes.
In addition, form the step of said sacrifice layer on this epitaxial substrate, comprise formation one shade on said epitaxial substrate.Annealing forms the shade of a patterning.The said epitaxial substrate of etching, and the shade that removes said patterning.
Above-mentioned etching can be wet etching, dry ecthing or inductance type plasma etch system (Inductively coupled plasma etcher; ICP).
Above-mentioned method also comprises formation one insulating barrier between said n type electrode and said p type electrode, can increase structural rigidity and the electrical isolation said n type electrode and the said p type electrode of semiconductor light emitting structure.
Above-mentioned method also comprises elder generation and forms a protective layer in said semiconductor light emitting structure periphery, and the said sacrifice layer of etching is to peel off said epitaxial substrate again.
Above-mentioned epitaxial substrate can be sapphire (Al
2O
3) substrate, carborundum (SiC) substrate, lithium aluminate substrate (AlLiO
2), lithium gallium oxide substrate (LiGaO
2), silicon (Si) substrate, gallium nitride (GaN) substrate, zinc oxide (ZnO) substrate, aluminum zinc oxide substrate (AlZnO), GaAs (GaAs) substrate, gallium phosphide (GaP) substrate, gallium antimonide substrate (GaSb), indium phosphide (InP) substrate, indium arsenide (InAs) substrate or zinc selenide (ZnSe) substrate.
Please refer to Fig. 4, it is the main method flow diagram of the present invention that forms.First step, the present invention forms a sacrifice layer earlier, and said sacrifice layer three kinds of methods capable of using form.First method comprises formation one the one III group-III nitride on said epitaxial substrate.Next the shade that forms a patterning is on a said III group-III nitride.The said III group-III nitride of etching, and the shade that removes said patterning again.Second method comprises elder generation and forms one the one III group-III nitride on said epitaxial substrate.Next the shade that forms a patterning is in a said III group-III nitride.Form one the 2nd III group-III nitride again on the shade of said patterning, and the shade that removes said patterning forms a plurality of holes.The third method comprises elder generation and forms a shade on said epitaxial substrate.Form the shade of a patterning again with annealing way.Next the said epitaxial substrate of etching, and the shade that removes said patterning at last.Form a kind of easy mode of sacrifice layer after technology removing said epitaxial substrate, and need not utilize laser.
Second step forms the semiconductor ray structure on above-mentioned sacrifice layer.Organic metal vapour deposition process capable of using (Metal Organic Chemical Vapor Deposition; MOCVD) or molecular beam epitaxy (Molecular Beam Epitaxy; MBE) etc. technology is deposited on semiconductor light emitting structure on the said sacrifice layer.Said semiconductor light emitting structure can comprise n type conductive layer, luminescent layer, electronic barrier layer and p type conductive layer.In addition, can on said p type conductive layer, form one deck ohmic contact layer again, make current-voltage characteristic curve present linearity, increase the stability of element.
Third step, the above-mentioned semiconductor light emitting structure of etching forms a light-emitting zone, Cutting platform and exposes n type conductive layer.Indivedual n type electrodes that form are on n type conductive layer, and p type electrode is on ohmic contact layer, to reach electric connection.In addition, provide an insulating barrier to be formed between n type electrode and the p type electrode, but not only support semiconductor ray structure and the hardness that increases structure also can let the mutual interference of n type electrode and p type electrode minimizing.
The 4th step is inverted above-mentioned semiconductor light emitting structure on a base plate for packaging.Prior to respectively forming a projection on the n type electrode of above-mentioned semiconductor light emitting structure and the p type electrode.Utilize flip chip technology (fct),, can avoid electrode to cover light-emitting zone and influence luminance the weld pad electric connection of a said projection and a base plate for packaging.
The 5th step, the above-mentioned sacrifice layer of etching is to peel off above-mentioned epitaxial substrate.Before carrying out etching, need protection component not receive the injury of etching solution and cause impaired.So, provide a transparent adhesive tape material to be filled between said semiconductor light emitting structure and the said base plate for packaging, coat said projection and weld pad to keep electric connection.In addition, be coated on semiconductor light emitting structure with a protective layer and base plate for packaging is not influenced by etching solution.To suitably select the hole destruction sacrifice layer of the etching solution of ratio then, and reach and peel off said epitaxial substrate via sacrifice layer.At last, remove described protective layer.
Above-mentioned its implementation content of the inventive method flow chart with the structural representation of collocation diagram with each step, is introduced the generation type of structure of the present invention and each step in detail.
At first form a sacrifice layer on an epitaxial substrate.The present invention proposes three kinds of methods that form said sacrifice layer.First kind of method that forms sacrifice layer please refer to Fig. 5 a to Fig. 5 e.Shown in Fig. 5 a, form one the one III group-III nitride 201 on said epitaxial substrate 101.Shown in Fig. 5 b, the shade 103 that forms a patterning again is on a said III group-III nitride 201.Shown in Fig. 5 c, the said III group-III nitride 201 of etching next.Shown in Fig. 5 d, the shade 103 that removes said patterning from a said III group-III nitride 201 forms a sacrifice layer, and said sacrifice layer comprises a plurality of grooves 127 and a plurality of cylinder 121.At last, shown in Fig. 5 e, form one the 2nd III group-III nitride 203 and be used as resilient coating, be positioned on the said sacrifice layer.About this first kind step its detailed content and generation type that forms sacrifice layer; Can consult the patent application motion of Advanced Development Photoelectric Co., Ltd.; TaiWan, China number of patent application 097107609, patent name are the manufacturing approach and the structure thereof of III-family nitrogen compound semiconductor photoelectric cell.
In addition, the another kind of method that forms sacrifice layer please refer to Fig. 6 a to Fig. 6 e.Shown in Fig. 6 a, at first form one the one III group-III nitride 201 on said epitaxial substrate 101.Shown in Fig. 6 b, the shade 103 that next forms a patterning is on a said III group-III nitride 201.Shown in Fig. 6 c, form one the 2nd III group-III nitride 203 again on the shade 103 of said patterning.Shown in Fig. 6 d, the shade 103 that removes said patterning forms a plurality of holes 119, makes said the 2nd III group-III nitride 203 become a sacrifice layer.At last, shown in Fig. 6 e, form one the 3rd III group-III nitride 205 and be used as resilient coating, be positioned on the said sacrifice layer.About this second kind step its detailed content and generation type that forms sacrifice layer; Can consult the patent application motion of Advanced Development Photoelectric Co., Ltd.; TaiWan, China number of patent application 097115512, patent name are the manufacturing approach and the structure thereof of III-family nitrogen compound semiconductor photoelectric cell.
In addition, the method that another forms sacrifice layer please refer to Fig. 7 a to Fig. 7 e.Shown in Fig. 7 a, form one first electrode 215 at first on said epitaxial substrate 101.Shown in Fig. 7 b, with the shade 103 of said first electrode 215 annealing formation patterning.Shown in Fig. 7 c, the said epitaxial substrate 101 of etching forms a sacrifice layer again.Said sacrifice layer comprises a plurality of grooves 127 and a plurality of cylinder 121.Shown in Fig. 7 d, remove the shade 103 of said patterning.At last, shown in Fig. 7 e, form an III group-III nitride 201 and be used as resilient coating, be positioned on the said sacrifice layer.Form step its detailed content and generation type of sacrifice layer about this third; Can consult the patent application motion of Advanced Development Photoelectric Co., Ltd.; TaiWan, China number of patent application 097117099, patent name are the method for separating semiconductor and substrate thereof.
Follow-up step explanation will be that example is described in detail with first kind of method that forms sacrifice layer.
Next, shown in Fig. 5 f, the atom of four families of mixing is to form n type conductive layer 301 on the 2nd III group-III nitride 203.Doping in the present embodiment is silicon atom (Si), and the precursor of silicon can use silicomethane (SiH in the Metalorganic chemical vapor deposition board
4) or silicon ethane (Si
2H
6).The generation type of n type conductive layer 301 is mixed the gallium nitride layer (GaN) of silicon atom (Si) or gallium nitride layer or the aluminium gallium nitride alloy layer (AlGaN) that aluminium gallium nitride alloy layer (AlGaN) to low concentration mixes silicon atom (Si) by high concentration in regular turn.Gallium nitride layer (GaN) or aluminium gallium nitride alloy layer (AlGaN) that high concentration is mixed silicon atom (Si) can provide preferable conductive effect between the n type electrode.
Then be to form a luminescent layer 303 on n type conductive layer 301.Wherein luminescent layer 303 can be single heterojunction structure, double-heterostructure, single quantum well layer or multiple quantum trap layer structure.At present multiple quantum trap layer structure, just structures of multiple quantum trap layer/barrier layer of adopting more.Quantum well layer can use InGaN (InGaN), and barrier layer can use the ternary structural of aluminium gallium nitride alloy (AlGaN) etc.In addition, also can adopt quad arrangement, just use aluminum indium gallium nitride (Al
xIn
yGa
1-x-yN) simultaneously as quantum well layer and barrier layer.The ratio of wherein adjusting aluminium and indium makes the ability rank of aluminum indium gallium nitride lattice can become the barrier layer on high energy rank and the quantum well layer on low energy rank respectively.Luminescent layer 303 can Doped n-type or the doping of p type (dopant), can be that Doped n-type is sub with the doping of p type simultaneously, also can undope fully.And, can be quantum well layer mix and barrier layer undopes, quantum well layer undopes and barrier layer doping, quantum well layer and barrier layer all doping or quantum well layer and barrier layer all undope.In addition, also can carry out the doping (delta doping) of high concentration in the part zone of quantum well layer.
Afterwards, on luminescent layer 303, form the electronic barrier layer 305 of p type conduction.The electronic barrier layer 305 of p type conduction comprises first kind of III-V family semiconductor layer and second kind of III-V family semiconductor layer.The energy gap of these two kinds of III-V family semiconductor layers is different; And has periodically repeated deposition on above-mentioned luminescent layer 303; Before periodically repeated deposition action can form the higher electronic barrier layer of energy barrier (energy barrier is higher than the energy barrier of active illuminating layer), in order to stop polyelectron (e-) overflow luminescent layer 303.Said first kind of III-V family semiconductor layer can be aluminum indium nitride gallium (Al
xIn
yGa
1-x-yN) layer, said second kind of III-V family semiconductor layer can be aluminum indium nitride gallium (Al
uIn
vGa
1-u-vN) layer.Wherein, 0＜x≤1,0≤y＜1, x+y≤1,0≤u＜1,0≤v≤1 and u+v≤1.When x=u, y ≠ v.In addition, said III-V family semiconductor layer also can be gallium nitride (GaN), aluminium nitride (AlN), indium nitride (InN), aluminium gallium nitride alloy (AlGaN), InGaN (InGaN) or aluminum indium nitride (AlInN).
At last, mix the atom of two families to form p type conductive layer 307 on electronic barrier layer 305.Be magnesium atom in the present embodiment.And the precursor of magnesium can use CP in the Metalorganic chemical vapor deposition board
2Mg.The generation type of p type conductive layer 307 is mixed the gallium nitride layer (GaN) of magnesium atom (Mg) or gallium nitride layer or the aluminium gallium nitride alloy layer (AlGaN) that aluminium gallium nitride alloy layer (AlGaN) to high concentration is mixed magnesium atom (Mg) by low concentration in regular turn.Gallium nitride layer (GaN) or aluminium gallium nitride alloy layer that high concentration is mixed magnesium atom (Mg) can provide preferable conductive effect between the p type electrode.
Shown in Fig. 5 g, then form an ohmic contact layer 207 and be positioned at ray structure 309 tops.Generally with vapor deposition, physical vaporous depositions such as sputter form ohmic contact layer 207 on ray structure 309.Its material can be nickel/gold (Ni/Au), tin indium oxide (Indium Tin Oxide; ITO), indium zinc oxide (Indium Zinc Oxide; IZO), indium oxide tungsten (Indium Tungsten Oxide; IWO), indium oxide gallium (Indium Gallium Oxide; IGO), platinum/gold (Pt/Au), chromium/gold (Cr/Au), nickel/chromium (Ni/Cr) or nickel/magnesium/nickel/chromium (Ni/Mg/Ni/Cr).
Shown in Fig. 5 h, after covering ohmic contact layer 207, the surface of photoresist being coated comprehensively ohmic contact layer 207 with centrifugal force through photoresist spin coating machine is to form photoresist film.With light lithography method (Photolithography) the photoresist film patterning is formed shade again, make and estimate that etching partly appears.Again with Wet-type etching, dry-etching or inductance type plasma etch system (Inductively coupled plasma etcher; ICP) carry out mesa (desk-top) technology.Said mesa technology is etching ray structure 309, to form a light-emitting zone 109 and Cutting platform 111, exposes n type conductive layer 301 simultaneously.With the laser cutting disk is cut into nude film 123 more at last, the dotted arrow direction among this figure is a cut direction.
Shown in Fig. 5 i, form a n type electrode 105 on n type conductive layer 301, a p type electrode 107 is on ohmic contact layer 207.The method of physical vapour deposition (PVD)s such as said n type electrode 105 and p type electrode 107 sputters capable of using, vapor deposition with Metal Deposition on said n type conductive layer 301 and ohmic contact layer 207.Said n type electrode 105 can be titanium/aluminium/titanium/gold (Ti/Al/Ti/Au), chromium billon (Cr/Au) or plumbous billon (Pd/Au).P type electrode 107 can be nickel billon (Ni/Au), platinum alloy (Pt/Au), tungsten (W), chromium billon (Cr/Au) or palladium (Pd).
Shown in Fig. 5 j, form an insulating barrier 209 between n type electrode 105 and p type electrode 107.Said insulating barrier 209 can reduce interfering with each other between said n type electrode 105 and the p type electrode 107, also can strengthen said ray structure 309, makes it to be difficult for broken.Said insulating barrier can be silicon dioxide (SiO
2), epoxy resin (Epoxy), silicon nitride (Si
3N
4), titanium dioxide (TiO
2) or aluminium nitride (AlN).
Shown in Fig. 5 k and Fig. 5 l, one or more nude films 123 are electrically connected on the base plate for packaging on 115 with the flip-chip bond technology.Indivedual earlier formation projections 113 correspond respectively to the weld pad 117 on the base plate for packaging with projection 113, to reach electric connection again on n type electrode 105 and p type electrode 107.Projection 113 compositions of flip-chip bond generally use terne metal, and the kind and the assembly program of substrate depended in the selection of its ratio.The ratio that the most often is used is 95% lead-5% tin.Said base plate for packaging 115 can be printed circuit board (PCB) (Printed Circuit Board; PCB), BT resin printed circuit plate (Bismaleimide Triazine resin Printed Circuit Board; BT PCB), high hot coefficient aluminium base (Metal Core Printed Circuit Board; MCPCB), flexible printed wiring board (Flexible Printed Circuit Board; Flexible PCB), ceramic substrate (Ceramic) or silicon substrate.About the detailed content and the step of said silicon substrate encapsulation, can consult the patent application motion of Advanced Development Photoelectric Co., Ltd., TaiWan, China patent No. I292962, patent name are the encapsulating structure and the manufacturing approach thereof of solid-state light emitting element.
Shown in Fig. 5 m and Fig. 5 n, before peeling off epitaxial substrate 101, protection projection 113 does not receive the chemical solution erosion to cause infringement with the electric connection and the whole light-emitting component of base plate for packaging 115 earlier.Cover projection 113 and base plate for packaging 115 with a transparent material earlier, coat whole light-emitting component with a protective layer again, but do not comprise an epitaxial substrate 101 and an III group iii nitride layer 201.Described transparent adhesive tape material can be silicon dioxide (SiO
2), epoxy resin (Epoxy) or silicon nitride (Si
3N
4).Said protective layer 213 can be silicon dioxide (SiO
2).
Shown in Fig. 5 o, element protection will be peeled off said epitaxial substrate 101 with Wet-type etching after accomplishing.Through the choosing and allocating of chemical solution, said chemical solution is injected an III group iii nitride layer 201.The said III group iii nitride layer 201 of winning that will make produces chemical reaction with chemical solution, and causes the structure of an III group iii nitride layer 201 to be disintegrated.Therefore, the epitaxial substrate 101 on an III group iii nitride layer 201 is stripped from immediately.
At last, shown in Fig. 5 p and Fig. 5 q, remove the protective layer 213 on the element after, the cutting base plate for packaging 115 (the dotted arrow direction among Fig. 5 p is a cut direction), promptly form a plurality of semiconductor optoelectronic elements 125.Two kinds of methods of wet type capable of using and dry type are removed described protective layer 213.The wet method is the use of the protective material is dissolved organic solution to achieve the purpose of the protective layer, the use of an organic solvent such as acetone (Acetone), methyl pyrrolidone (N-Methyl-Pyrolidinone; NMP), dimethyl sulfoxide Feng (Dimethyl? Sulfoxide; DMSO), 2 - (2 - amino-ethoxy) ethanol, 2 - (2-Aminoethoxy? ethanol), ethanolamine (MonoEthanolAmine; MEA), and ethylene glycol monobutyl ether (ButoxyDiGlycol; BDG) and so on.Another wet method then can be used the mixed solution (SPM) of inorganic solution such as sulfuric acid and hydrogen peroxide solution, and the method technology cost is lower.Dry type goes the shade rule to be to use oxygen or its plasma that photoresist is removed.After removing protective layer 213, cut base plate for packaging 115, form a plurality of semiconductor optoelectronic elements 125 with general cutter worker.
Above-mentioned method step can make technology more can reach actual demand according to the order of replacing under different condition.
Comprehensive above-mentioned explanation; The luminance of more general conventional semiconductors photoelectricity horizontal cell; Semiconductor optoelectronic element of the present invention is peeled off epitaxial substrate after encapsulating with flip chip technology (fct) again; The light minimizing that its element penetrates receives substrate and electrode disturbs, so its luminance is higher than the luminance of general conventional semiconductors photoelectricity horizontal cell.In addition, semiconductor optoelectronic element is also good than the thermal diffusivity of general semiconductor optoelectronic element aspect thermal diffusivity.In addition, the process of semiconductor optoelectronic element of the present invention is simpler.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need in the scope of claims, understand, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentionedly being merely preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence accomplished under the disclosed spirit and changes or modify, and all should be included in the scope that claims of the present invention define.
Claims (8)
1. the manufacturing approach of a flip-chip type semiconductor photoelectric cell structure comprises:
One epitaxial substrate is provided;
Form a sacrifice layer on this epitaxial substrate, said sacrifice layer comprises a plurality of grooves and a plurality of cylinder;
Form the semiconductor ray structure on this sacrifice layer; This semiconductor light emitting structure has a first surface and with respect to the second surface of first surface; This sacrifice layer is positioned at the second surface of this semiconductor light emitting structure, and said semiconductor light emitting structure is not filled said a plurality of groove;
Form a n type electrode and a p type electrode on the first surface of this semiconductor light emitting structure;
Be inverted this semiconductor light emitting structure on a base plate for packaging; This base plate for packaging has a first surface and with respect to the second surface of first surface, wherein this first surface has one first weld pad and one second weld pad, also comprises one first projection and one second projection on this base plate for packaging; This first projection is positioned on this first weld pad; This second projection is positioned on this second weld pad, and this n type electrode and this first projection electrically connect, and this p type electrode and this second projection electrically connect;
Fill a transparent adhesive tape material between the first surface of the first surface of this base plate for packaging and semiconductor light emitting structure, coat this first weld pad, this second weld pad, this first projection and this second projection;
This sacrifice layer of etching is to peel off this epitaxial substrate.
2. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:
Form one first III-nitride on this epitaxial substrate;
The shade that forms a patterning is on this first III-nitride;
This first III-nitride of etching; And
Remove the shade of this patterning.
3. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:
Form one first III-nitride on this epitaxial substrate;
The shade that forms a patterning is in this first III-nitride;
Form one second III-nitride on the shade of this patterning; And
The shade that removes said patterning forms a plurality of holes.
4. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, the step of this sacrifice layer of wherein said formation on this epitaxial substrate comprises:
Form a shade on this epitaxial substrate;
Annealing forms the shade of a patterning;
This epitaxial substrate of etching; And
Remove the shade of this patterning.
5. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said wet etching, dry ecthing or the inductance type plasma etch system of being etched to.
6. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said method also comprise formation one insulating barrier structural rigidity and this n type electrode of electrical isolation and this p type electrode with the increase semiconductor light emitting structure between this n type electrode and this p type electrode.
7. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, wherein said method also comprise elder generation and form a protective layer in this semiconductor light emitting structure periphery, and this sacrifice layer of etching is to peel off this epitaxial substrate again.
8. the manufacturing approach of flip-chip type semiconductor photoelectric cell structure as claimed in claim 1, it is wet etching that wherein said etch sacrificial layer is peeled off this epitaxial substrate.
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| KR101144351B1 (en) * | 2010-09-30 | 2012-05-11 | 서울옵토디바이스주식회사 | wafer level LED package and fabrication method thereof |
| CN102446948B (en) * | 2010-10-12 | 2014-07-30 | 晶元光电股份有限公司 | Light emitting element |
| US8962358B2 (en) * | 2011-03-17 | 2015-02-24 | Tsmc Solid State Lighting Ltd. | Double substrate multi-junction light emitting diode array structure |
| US9263255B2 (en) | 2012-03-19 | 2016-02-16 | Seoul Viosys Co., Ltd. | Method for separating epitaxial layers from growth substrates, and semiconductor device using same |
| CN103296153B (en) * | 2012-05-28 | 2016-06-22 | 傅华贵 | LED chip method for packing |
| CN102931313B (en) * | 2012-08-30 | 2014-11-19 | 安徽三安光电有限公司 | Inverted light emitting diode and manufacture method thereof |
| CN103996779A (en) * | 2014-05-21 | 2014-08-20 | 广东威创视讯科技股份有限公司 | Flip-chip LED device and integrated COB display module thereof |
| CN104235775A (en) * | 2014-09-01 | 2014-12-24 | 重庆四联光电科技有限公司 | Light source structure of fish gathering lamp |
| CN104810444B (en) * | 2015-03-04 | 2018-01-09 | 华灿光电(苏州）有限公司 | LED epitaxial slice and preparation method thereof, light-emitting diode chip for backlight unit prepares and substrate recovery method |
| CN105047769B (en) * | 2015-06-19 | 2017-12-29 | 安徽三安光电有限公司 | A kind of light-emitting diodes tube preparation method that substrate desquamation is carried out using wet etching |
| CN104979412B (en) * | 2015-07-08 | 2017-09-29 | 苏州强明光电有限公司 | Solar battery epitaxial wafer and its preparation method |
| CN105355729B (en) * | 2015-12-02 | 2018-06-22 | 佛山市国星半导体技术有限公司 | LED chip and preparation method thereof |
| CN106098877A (en) * | 2016-08-26 | 2016-11-09 | 广东德力光电有限公司 | A kind of zno-based flip LED chips and preparation method thereof |
| CN109192670A (en) * | 2018-08-17 | 2019-01-11 | 中国科学院上海微系统与信息技术研究所 | Flexible semiconductor laminated film and preparation method thereof |
| CN111063773B (en) * | 2019-12-13 | 2021-08-27 | 深圳第三代半导体研究院 | Substrate, LED and manufacturing method thereof |
| CN110957407B (en) * | 2019-12-13 | 2021-04-09 | 深圳第三代半导体研究院 | Substrate, LED and manufacturing method thereof |
| CN110931608B (en) * | 2019-12-13 | 2021-07-30 | 深圳第三代半导体研究院 | Substrate, LED and manufacturing method thereof |
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