CN101853837B - Circuit substrate - Google Patents
Circuit substrate Download PDFInfo
- Publication number
- CN101853837B CN101853837B CN2009101311420A CN200910131142A CN101853837B CN 101853837 B CN101853837 B CN 101853837B CN 2009101311420 A CN2009101311420 A CN 2009101311420A CN 200910131142 A CN200910131142 A CN 200910131142A CN 101853837 B CN101853837 B CN 101853837B
- Authority
- CN
- China
- Prior art keywords
- conductive layer
- circuit
- grid
- conductive
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention discloses a circuit substrate, comprising a first conductive layer, wherein the first conductive layer comprises at least one power supply/grounding plane which is provided with at least one plane edge and a plurality of grid lines; each grid line is provided with a line width; the grid lines are mutually staggered and defined into a plurality of first grid holes; the distance between the first grid hole closest to the plane edge and the plane edge is 1.5 times greater than the line width, therefore, the influence of the first grid hole on power supply and grounding impedances is reduced to the lowest so as to solve the problem of the completeness of the power supply and reduce the generation of heat.
Description
Technical field
The present invention relates to a kind of circuit substrate, particularly relate to the circuit substrate that a kind of power supply/ground plane has the grid hole.
Background technology
Fig. 1 is for showing the schematic top plan view of known circuit substrate.With reference to figure 1; This known circuit substrate 1 is windowing type ball grid array (WINDOW BALL GRID ARRAY; WBGA) base plate for packaging, it comprise window 11, a plurality of power supply/ground plane (Power/Ground Plane) 12, a plurality of conductive finger (Finger) 13, a plurality of I/O ball pad (I/O Ball Pad) 14, power supply/ground connection ball pad (Power/GroundBall Pad) 15 and many conductive traces (Conductive Trace) 16.These conductive fingers 13 are positioned at this periphery of 11 of windowing.Each power supply/ground plane 12 has many grid line 121, and these grid line 121 are interlaced with each other and define a plurality of grid holes 122.The material of this power supply/ground plane 12 is a copper, and it utilizes etching mode that a sheet of copper district is formed these grid line 121 and these grid holes 122.For reliable reliability, these grid line 121 and these grid holes 122 are evenly to distribute, and to increase the passage of air dissipation, reach increase by two layers conjugation up and down.
These I/O ball pads 14 utilize these conductive traces 16 of part to be electrically connected to these conductive fingers 13 of part.These power supplys/ground connection ball pad 15 is positioned at this power supply/ground plane 12, and this power supply/ground plane 12 utilizes these conductive traces 16 of another part to be electrically connected to these conductive fingers 13 of another part.These conductive fingers 13 are in order to be electrically connected to the chip (not shown), and these I/O ball pads 14 and these power supplys/ground connection ball pad 15 is in order to form a plurality of soldered ball (not shown) on it.
The shortcoming of this known circuit substrate 1 is that because this power supply/ground plane 12 is important power supply or ground signalling source, the grid hole 122 that is covered with on it can influence the signal impedance of power supply or ground connection, and possibly make that power supply is imperfect.
Therefore, the circuit substrate that is necessary to provide the power supply/ground plane of a kind of innovation and tool progressive to have the grid hole is to address the above problem.
Summary of the invention
The present invention provides a kind of circuit substrate, and it comprises at least one power supply/ground plane (Power/GroundPlane).This power supply/ground plane has at least one horizontal edge and many grid line; Each grid line has live width; These grid line are interlaced with each other and define a plurality of first grid holes, wherein near greater than this live width 1.5 times of the first grid hole of this horizontal edge and the distance between this horizontal edge.Thus, it is minimum that the first grid hole is reduced to the impedance influences of power supply and ground connection, with the problem of minimizing power supply integrality, and can reduce hot generation.
Description of drawings
Fig. 1 is for showing the schematic top plan view of known circuit substrate;
Fig. 2 is for showing that power supply/ground plane of the present invention has the schematic top plan view of the circuit substrate of grid hole;
Fig. 3 is for showing that power supply/ground plane of the present invention has the cross-sectional schematic of the circuit substrate of grid hole; And
Fig. 4 is the schematic top plan view of second conductive layer of the circuit substrate of displayed map 3.
Description of reference numerals
1 known circuit substrate
2 circuit substrates of the present invention
3 circuit substrates of the present invention
11 window
12 power supplys/ground plane
13 conductive fingers
14 I/O ball pads
15 power supplys/ground connection ball pad
16 conductive traces
20 first conductive layers
21 window
22 power supplys/ground plane
23 conductive fingers
24 I/O ball pads
25 power supplys/ground connection ball pad
26 conductive traces
28 grid distributed areas
31 first conductive layers
32 second conductive layers
33 dielectric layers
121 grid line
122 holes
221 grid line
222 first grid holes
223 horizontal edges
281 edges of regions
321 window
322 second grid holes
323 projection circuits
Embodiment
Fig. 2 is for showing that power supply/ground plane of the present invention has the schematic top plan view of the circuit substrate of grid hole.With reference to figure 2, in the present embodiment, this circuit substrate 2 is windowing type ball grid array (WINDOWBALL GRID ARRAY; WBGA) base plate for packaging; Yet it is understandable that this circuit substrate 2 also can be other forms of circuit substrate, it can be single layer substrate or multilager base plate.This circuit substrate 2 comprises first conductive layer 20.This first conductive layer 20 comprise window 21, a plurality of power supply/ground plane (Power/Ground Plane) 22 and circuit.This circuit comprises a plurality of conductive fingers (Finger) 23, a plurality of I/O ball pad (I/O Ball Pad) 24, a plurality of power supply/ground connection ball pad (Power/Ground Ball Pad) 25 and many conductive traces (Conductive Trace) 26.These conductive fingers 23 are positioned at this periphery of 21 of windowing.
These I/O ball pads 24 utilize these conductive traces 26 of part to be electrically connected to these conductive fingers 23 of part.These power supplys/ground connection ball pad 25 is positioned at this power supply/ground plane 22, and this power supply/ground plane 22 utilizes these conductive traces 26 of another part to be electrically connected to these conductive fingers 23 of another part.These conductive fingers 23 are in order to be electrically connected to the chip (not shown), and these I/O ball pads 24 and these power supplys/ground connection ball pad 25 is in order to form a plurality of soldered ball (not shown) on it.
Each power supply/ground plane 22 has at least one horizontal edge 223, grid distributed areas 28.These grid distributed areas 28 have many grid line 221 and edges of regions 281.These grid line 221 are interlaced with each other and define a plurality of first grid holes 222.Preferably, the material of this power supply/ground plane 22 is a copper, and it utilizes etching mode that a sheet of copper district is formed these grid line 221 and these first grid holes 222.Each grid line 221 has live width W, that is the distance of 222 of two first grid holes also is W.
In the present invention, near the distance B 1 of 223 of the first grid hole 222 of this horizontal edge 223 and this horizontal edges 1.5 times (if this live width W is 100 μ m, 1 of this distance B is 150 μ m) greater than this live width W; Perhaps, the distance B 2 of 223 of the horizontal edges of the edges of regions 281 of these grid distributed areas 28 and this power supply/ground plane 22 is greater than 1.5 times of this live width.Therefore, in this circuit substrate 2, inwardly start at from the horizontal edge 223 of this power supply/ground plane 22 in the scope of 1.5W and have no the first grid hole for entity part.The principle of this design for the entity part that keeps this horizontal edge 223 and inwardly start at 1.5W as the current reflux path in electric current/ground connection (Return CurrentPath) 27; And the first grid hole is not set on this current reflux path 27; So can make the first grid hole reduce to minimum to the impedance influences of power supply and ground connection; With the problem of minimizing power supply integrality, and can reduce hot generation.
Preferably, these power supplys/ground connection ball pad 25 position of being positioned at this power supply/ground plane 22 does not also have the first grid hole.
Fig. 3 is for showing that power supply/ground plane of the present invention has the cross-sectional schematic of the circuit substrate of grid hole.With reference to figure 3, this circuit substrate 3 is a double layer substrate, and it comprises first conductive layer 31, second conductive layer 32 and dielectric layer 33.The vertical view of this first conductive layer 31 is identical with first conductive layer 20 of Fig. 2, and it has at least one power supply/ground plane (Power/Ground Plane) 22 and circuit.This second conductive layer 32 is positioned at this first conductive layer, 31 belows.This dielectric layer 33 is located between this first conductive layer 31 and this second conductive layer 32, and this dielectric layer 33 has thickness T.
In this first conductive layer 31, each power supply/ground plane 22 has at least one horizontal edge 223, grid distributed areas 28.These grid distributed areas 28 have many grid line 221 and edges of regions 281.These grid line 221 are interlaced with each other and define a plurality of first grid holes 222.Preferably, the material of this power supply/ground plane 22 is a copper, and it utilizes etching mode that a sheet of copper district is formed these grid line 221 and these first grid holes 222.Each grid line 221 has live width W, that is the distance of 222 of two first grid holes also is W.Near the distance B 1 of 223 of the first grid hole 222 of this horizontal edge 223 and this horizontal edges 1.5 times (if this live width W is 100 μ m, 1 of this distance B is 150 μ m) greater than this live width W; Perhaps, the distance B 2 of 223 of the horizontal edges of the edges of regions 281 of these grid distributed areas 28 and this power supply/ground plane 22 is greater than 1.5 times of this live width.
With reference to figure 4, the schematic top plan view of second conductive layer of the circuit substrate of displayed map 3.This second conductive layer 32 have window 321, a plurality of second grid hole 322 and projection circuit 323.This window 321 pairs should first conductive layer 20 window 21.Preferably, the material of this second conductive layer 32 is full wafer copper district, and it utilizes etching mode that this copper district is formed these second grid holes 322.This projection circuit 323 is formed by the circuit projection of this first conductive layer 20, should projection circuit 323 be imaginary virtual circuit therefore.Throw the distance B of 323 in circuit with this in this second conductive layer 32 near the second grid hole 322 of this projection circuit 323
3Thickness T greater than this dielectric layer 33.Therefore, in this second conductive layer 32, start at from the edge of this projection circuit 323 in the scope of T and have no the second grid hole for entity part.
The foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, persons skilled in the art are made amendment to the foregoing description and are changed and still do not take off spirit of the present invention.Interest field of the present invention should be liked claim enclosed and define.
Claims (8)
1. a circuit substrate comprises first conductive layer, and this first conductive layer comprises:
At least one power supply/ground plane; Have at least one horizontal edge and many grid line; Each grid line has live width; These grid line are interlaced with each other and define a plurality of first grid holes, wherein near greater than this live width 1.5 times of the first grid hole of this horizontal edge and the distance between this horizontal edge
Wherein this first conductive layer also comprises circuit; This circuit comprises a plurality of conductive fingers, a plurality of I/O ball pad, a plurality of power supply/ground connection ball pad and many conductive traces; Wherein these these conductive traces of I/O ball pad utilization part are electrically connected to these conductive fingers of part; These power supplys/ground connection ball pad is positioned at this power supply/ground plane, and this power supply/ground plane utilizes these conductive traces of another part to be electrically connected to these conductive fingers of another part.
2. circuit substrate as claimed in claim 1, wherein these conductive fingers are in order to be electrically connected to chip, and these I/O ball pads and these power supplys/ground connection ball pad is in order to form a plurality of soldered balls on it.
3. circuit substrate as claimed in claim 1, wherein these power supplys/ground connection ball pad position of being positioned at this power supply/ground plane does not have the first grid hole.
4. circuit substrate as claimed in claim 1; Also comprise second conductive layer and a dielectric layer; This second conductive layer is positioned at this first conductive layer below, and this second conductive layer has a plurality of second grid holes and projection circuit, and the circuit projection of this this first conductive layer of incident line route forms; This projection circuit is imaginary virtual circuit; This dielectric layer is located between this first conductive layer and this second conductive layer, and this dielectric layer has thickness, wherein throws distance between circuit greater than the thickness of this dielectric layer near the second grid hole of this projection circuit and this in this second conductive layer.
5. a circuit substrate comprises first conductive layer, and this first conductive layer comprises:
At least one power supply/ground plane; Have at least one horizontal edge and grid distributed areas; These grid distributed areas have many grid line and edges of regions, and each grid line has live width, and these grid line are interlaced with each other and define a plurality of first grid holes; Wherein the distance between the horizontal edge of the edges of regions of these grid distributed areas and this power supply/ground plane is greater than 1.5 times of this live width
Wherein this first conductive layer also comprises circuit; This circuit comprises a plurality of conductive fingers, a plurality of I/O ball pad, a plurality of power supply/ground connection ball pad and many conductive traces; Wherein these these conductive traces of I/O ball pad utilization part are electrically connected to these conductive fingers of part; These power supplys/ground connection ball pad is positioned at this power supply/ground plane, and this power supply/ground plane utilizes these conductive traces of another part to be electrically connected to these conductive fingers of another part.
6. circuit substrate as claimed in claim 5, wherein these conductive fingers are in order to be electrically connected to chip, and these I/O ball pads and these power supplys/ground connection ball pad is in order to form a plurality of soldered balls on it.
7. circuit substrate as claimed in claim 5, wherein these power supplys/ground connection ball pad position of being positioned at this power supply/ground plane does not have the first grid hole.
8. circuit substrate as claimed in claim 5; Also comprise second conductive layer and dielectric layer; This second conductive layer is positioned at this first conductive layer below, and this second conductive layer has a plurality of second grid holes and projection circuit, and this projection circuit is that the circuit by this first conductive layer throws and forms; This projection circuit is imaginary virtual circuit; This dielectric layer is located between this first conductive layer and this second conductive layer, and this dielectric layer has thickness, wherein throws distance between circuit greater than the thickness of this dielectric layer near the second grid hole of this projection circuit and this in this second conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101311420A CN101853837B (en) | 2009-04-03 | 2009-04-03 | Circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101311420A CN101853837B (en) | 2009-04-03 | 2009-04-03 | Circuit substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101853837A CN101853837A (en) | 2010-10-06 |
| CN101853837B true CN101853837B (en) | 2012-05-23 |
Family
ID=42805214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101311420A Active CN101853837B (en) | 2009-04-03 | 2009-04-03 | Circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101853837B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361548A (en) * | 2000-12-28 | 2002-07-31 | 扬智科技股份有限公司 | Base board lay-out method and structure to reduce cross-talk of adjacent signals |
| US6784525B2 (en) * | 2002-10-29 | 2004-08-31 | Micron Technology, Inc. | Semiconductor component having multi layered leadframe |
| JP2005244010A (en) * | 2004-02-27 | 2005-09-08 | Toppan Printing Co Ltd | Packaging structure of circuit board |
-
2009
- 2009-04-03 CN CN2009101311420A patent/CN101853837B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1361548A (en) * | 2000-12-28 | 2002-07-31 | 扬智科技股份有限公司 | Base board lay-out method and structure to reduce cross-talk of adjacent signals |
| US6784525B2 (en) * | 2002-10-29 | 2004-08-31 | Micron Technology, Inc. | Semiconductor component having multi layered leadframe |
| JP2005244010A (en) * | 2004-02-27 | 2005-09-08 | Toppan Printing Co Ltd | Packaging structure of circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101853837A (en) | 2010-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4195883B2 (en) | Multilayer module | |
| CN104795382A (en) | Semiconductor package | |
| CN104425459B (en) | The inspection method of semiconductor device and semiconductor device | |
| CN204243028U (en) | Electronic system | |
| US10811332B2 (en) | Thermal-dissipating substrate structure | |
| JP2011023528A5 (en) | ||
| CN103383940A (en) | Semiconductor package and fabrication method thereof | |
| CN104218016A (en) | IC (integrated circuit) carrier board and semiconductor device with same | |
| KR20090083709A (en) | Printed circuit board, semiconductor package, card and system | |
| TWI358243B (en) | Circuit substrate having power/ground plane with g | |
| TW200518270A (en) | Semiconductor device, and wiring-layout design system for automatically designing wiring-layout in such semiconductor device | |
| CN101572260B (en) | Multi-chip stacking type packaging body | |
| CN101853837B (en) | Circuit substrate | |
| CN207369392U (en) | A kind of folder paper tinsel base circuit board with heat sink material | |
| JPWO2021111604A5 (en) | ||
| CN207947003U (en) | Display panel and its drive component | |
| CN102196657B (en) | Circuit substrate | |
| CN104795363A (en) | Copper-clad substrate with barrier structure and manufacturing method thereof | |
| CN101150123A (en) | Semiconductor encapsulation structure with electromagnetic shielding cover | |
| JP2010219501A (en) | Circuit board, and electronic apparatus having the same | |
| CN208014692U (en) | Chip package and electronic assembly | |
| CN1971897B (en) | Ball grid array wiring structure | |
| KR20100104911A (en) | Semiconductor package | |
| CN207896090U (en) | array substrate and display device | |
| TW200532884A (en) | Integrated circuit substrate with conductive ring and semiconductor device integrated with the substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |