CN101870445B - Circuit lead structure and micro-electromechanical system - Google Patents
Circuit lead structure and micro-electromechanical system Download PDFInfo
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- CN101870445B CN101870445B CN2009101347494A CN200910134749A CN101870445B CN 101870445 B CN101870445 B CN 101870445B CN 2009101347494 A CN2009101347494 A CN 2009101347494A CN 200910134749 A CN200910134749 A CN 200910134749A CN 101870445 B CN101870445 B CN 101870445B
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Abstract
The invention relates to a circuit lead structure and a micro-electromechanical system. The micro-electromechanical system comprises a substrate, at least one transistor arranged on the substrate, at least one micro-electromechanical element arranged at a micro-electromechanical structure area; and a lowest step region connection line; wherein the transistor is arranged in a CMOS circuit region and is electrically connected with a contact window column, the lowest step region connection line is made by the same material at the same step with the contact window column, and the micro-electromechanical element is coupled with the transistor by the lowest step region connection line. The circuit lead structure comprises a substrate, at least one transistor and a lowest step region connection line; the transistor is arranged on the substrate and is electrically connected with a contact window column, the lowest step region connection line is at the same step with the contact window column and is made of the same material with the contact window column.
Description
Technical field
The present invention relates to a kind of circuit lead structure and a kind of MEMS (MEMS; Micro-Electro-Mechanical System); In this MEMS; Micro electromechanical structure couples through lowest-order regional metal line and microelectronic circuit, and this lowest-order regional metal line and contact hole hitching post are the metals that is in rank, same position.
Background technology
Microcomputer electric component has various application, for example little sound pressure sensor, gyroscope, accelerometer etc.Most microcomputer electric component must be integrated with other microelectronic circuit.Shown in Figure 1A plane graph, MEMS 2 comprises cmos circuit 6 and micro electromechanical structure 8, and this MEMS 2 for example is a gyroscope.Micro electromechanical structure 8 is through first rank or more go up rank metal connecting line 16A/16B and cmos circuit 6 couples.14 is contact hole hitching post (contact) among the figure, and 18 is interlayer hitching post (via) among the figure.
With reference now to Figure 1B,, Figure 1B is the profile along the A-A ' direction of Figure 1A.Field-effect transistor is formed on the semiconductor substrate 20, and it includes gate dielectric layer 22, grid 24 and source/drain 26.In the dielectric layer 27 of semiconductor substrate 20, form contact hole to expose source electrode and drain electrode; Then be filled with contact hole hitching post 14 in the contact hole; Then above hitching post, form the first rank metal connecting line 30,34 of the somes of micro electromechanical structure are through this first rank metal connecting line 30 or more go up the rank metal connecting line and field-effect transistor couples.Can find that this first rank metal connecting line 30 is to be in the not metal on coordination rank with contact hole hitching post 14: the first rank metal connecting line 30 is than contact hole hitching post 14 higher order at least.
As as everyone knows, micro electromechanical structure must produce cavity (cavity) between metal structure, shown in the 36A/36B of Figure 1B.36A/36B is a cavity, and it was the insulating barrier between the metal structure originally, and this insulating barrier is emptied when making microcomputer electric component, is directed at micro electromechanical structure and suspends.But along with the making of micro electromechanical structure, metal connecting line 30 or its are more gone up the rank metal connecting line also becomes suspension, and the metal connecting line that suspends possibly cause the instability of field-effect transistor-micro electromechanical structure integration system, for a long time integrity problem will take place.This problem not only can take place in microcomputer electric component, also is present in in the CMOS integrated circuit of air as low dielectric constant.
Therefore, need a kind of more firm circuit lead structure, can be applicable in the MEMS or with in the CMOS integrated circuit of air as low dielectric constant.
Summary of the invention
The objective of the invention is to overcome the deficiency and the defective of prior art, propose a kind of circuit lead structure and a kind of MEMS, to solve foregoing problems.
For reaching above-mentioned purpose, with regard to one of them viewpoint of the present invention, a kind of MEMS is provided, comprise: a substrate; Position at least one transistor on this substrate, this transistor is positioned at a cmos circuit district and electrically connects with a contact hole hitching post; At least one microcomputer electric component is positioned at a micro electromechanical structure district; And one and the lowest-order zone line in same steps as, processed with same material of this contact hole hitching post, this microcomputer electric component couples with this transistor via this lowest-order zone line.
For reaching above-mentioned purpose, with regard to another viewpoint of the present invention, a kind of circuit lead structure is provided, comprise: a substrate; Position at least one transistor on this substrate, this transistor AND gate one contact hole hitching post electrically connects; And one and the lowest-order on these contact hole hitching post coordination rank zone line.
In above MEMS and the circuit lead structure, the mode of this lowest-order zone line and substrate insulation for example can be: between lowest-order zone line and substrate, silicon nitride or silicon oxynitride insulating barrier are set; Or in substrate, be provided with and the opposite wellblock of substrate conduction kenel; Or between lowest-order zone line and substrate, the composite bed that comprises compound crystal silicon pattern and dielectric pattern is set.
Explain in detail through specific embodiment below, when the effect that is easier to understand the object of the invention, technology contents, characteristics and is reached.
Description of drawings
Figure 1A-1B is a prior art;
Fig. 2-6 marks first embodiment of the present invention;
Fig. 7 marks second embodiment of the present invention;
Fig. 8 marks the 3rd embodiment of the present invention.
Symbol description among the figure
2 MEMSs
6 cmos circuits
8 micro electromechanical structures
14 contact hole hitching posts
16A/16B first rank or more go up the rank metal connecting line
18 interlayer hitching posts
20 semiconductor substrates
22 gate dielectric layers
24 grids 24
26 source/drains
27/28 dielectric layer
30 first rank metal connecting lines
The some of 34 micro electromechanical structures
The 36A/36B cavity
50 silicon semiconductor substrates
54A/52A grid/gate dielectric layer
54B/52B compound crystal silicon pattern/silicon oxide pattern
56 source electrodes or drain electrode
58 dielectric layers
60 protective layers
62 contact holes
64 grooves
66 contact hole hitching posts
68 lowest-order regional metal lines
70 first rank metal connecting lines
72 micro electromechanical structures
80 N+ wellblocks
82 N-wellblocks
84 insulating barriers
40 suspension structures
Embodiment
Illustrate graphic all genus the among the present invention, mainly be intended to represent the orbution up and down between fabrication steps and each layer, then according to scale as for shape, thickness and width.
The first embodiment of the present invention at first is described.See also Fig. 2, a semiconductor wafer substrate 50 at first is provided in the present embodiment, for example, P type silicon substrate.Then on the cmos circuit zone of substrate 50 with standard MOS processing procedure fabricating yard effect transistor, this field-effect transistor contains gate dielectric layer 52A, grid 54A and source/drain 56.Form the composite bed that comprises pattern 52B and pattern 54B in the microcomputer electric component zone simultaneously.The material of gate dielectric layer 52A and pattern 52B for example is that the material of silica, grid 54A and pattern 54B for example is a compound crystal silicon.The component structure of visual field effect transistor and deciding, the material of gate dielectric layer 52A and patterned layer 52B can also be a high dielectric constant material.The compound crystal silicon of pattern 52B should not contain any doping.
Gate dielectric layer 52A is that thermal oxidation silicon substrate 50 forms, and thickness is for example at 10 to 100 dusts.Grid 54A cooperates active ion formula plasma etch techniques etching compound crystal silicon to form with traditional little shadow technology again, and compound crystal silicon is with Low Pressure Chemical Vapor Deposition (LoW Pressure Chemical Vapor Deposition; LPCVD) form, general preferable thickness is between 1000 to 3000 dusts.
With reference to figure 3, deposition one dielectric layer 58, and can form the thin protective layer 60 of one deck as required and optionally, and said dielectric layer 58 is implemented planarization, for example chemical-mechanical polishes technology (Chemical Mechanical Polishing; CMP) or the hot-fluid adjusting technique.This dielectric layer 58 can be the unadulterated silicon dioxide that utilizes Low Pressure Chemical Vapor Deposition to form, its thickness between 3000 dusts between 8000 dusts.Said dielectric layer 58 also can be boron phosphorus doped silicon dioxide or the phosphorus doped silicon dioxide that utilizes atmospheric chemical vapor deposition or subatmospheric chemical vapour deposition technique to form, and its thickness is between 3000 to 8000 dusts.60 of protective layers are the silicon nitrides that utilizes Low Pressure Chemical Vapor Deposition or plasma enhanced chemical vapor deposition method to form, and its thickness is between 100 to 500 dusts.Because protective layer 60 needs to stop the used etchant of follow-up formation microcomputer electric component step, HF for example, its etching characteristic is essential totally different in this dielectric layer 58.
With reference now to Fig. 4 and Fig. 5.In the dielectric layer in field-effect transistor zone, form contact hole 62 (contact hole) with technology such as little shadow and etchings in regular turn, in this dielectric layer in microcomputer electric component zone, then form groove 64 (trench), as shown in Figure 4.Etching technique can be non-plasma etch techniques such as the tropism of grade.Contact hole 62 can expose source electrode or drain 56.When forming groove 64, channel bottom is the silicon oxide pattern 52B and the compound crystal silicon pattern 54B in microcomputer electric component zone.Groove 64 is positions that preparation forms lowest-order regional metal line, and silicon oxide pattern 52B and compound crystal silicon pattern 54B are then as the insulation between follow-up lowest-order regional metal line and the semiconductor wafer substrate.Then, in contact hole 62, form contact hole hitching post 66, in groove 64, then form lowest-order regional metal line 68 with this semiconductor substrate 50 (source electrode or drain 56) contact, as shown in Figure 5.MEMS will be with these lowest-order regional metal line 68 leads as the micro electromechanical structure district, and extend in the cmos circuit district and couple with transistor.This lowest-order regional metal line 68 is not Figure 1B first rank metal connecting line 30 of the prior art, but with contact hole hitching post 66 coordination rank (that is metal connecting line 68 is to process in same step with identical material with contact hole hitching post 66).Hitching post 66 can be tungsten, aluminium, copper or its alloy with the material of lowest-order regional metal line 68, and manufacture method can be inserted technology (damascene) or plasma etch techniques.
With reference to figure 6.Then, above this lowest-order regional metal line 68, form the first rank metal connecting line 70 and micro electromechanical structure 72.This micro electromechanical structure 72 couples with this transistor through this lowest-order regional metal line 68.Certainly,, above this lowest-order regional metal line 68, can form the second rank metal connecting line again except the first rank metal connecting line 70, the 3rd rank metal connecting line and quadravalence metal connecting line, the metal level number can be more, and icon only is for example.In addition; The step of making micro electromechanical structure 72 and metal connecting line does not have absolute precedence; The making of the micro electromechanical structure of present embodiment is after the first rank metal connecting line; But according to demands such as the kind of microcomputer electric component or processing procedures, the making of micro electromechanical structure also can be before the first rank metal connecting line.
What specify is, the conductor structure that micro electromechanical structure 72 uses lowest-order regional metal lines 68 to couple as itself and cmos circuit zone, this lowest-order regional metal line 68 is not the first rank metal of the prior art, but with contact hole hitching post coordination rank.Because it presses close to substrate 50, therefore can be described as the internal connection-wire structure (substrate-level interconnection) on rank, substrate position.Under this kind structural design, so the unlikely suspension of the conductor structure in the micro electromechanical structure district is more firm than prior art.
Fig. 7 is used to explain second embodiment.Second embodiment follows the difference of first embodiment to be that lowest-order regional metal line 68 is different with the insulation mode between the semiconductor wafer substrate 50.As shown in Figure 7, suppose that substrate 50 is P type substrate, then can use N+/N-wellblock 80/82 to be used as insulation.N+/N-wellblock 80/82 can be planted with arsenic or phosphonium ion cloth and formed; Look the face that the connects effect of being desired and decide; N+ ion implantation dosage for example can be about 1E15 between 1E17 atom/square centimeter, and N-ion implantation dosage for example can be about 1E13 between 1E15 atom/square centimeter.Certainly, if substrate is the substrate of other type, then the dopant profile of wellblock and concentration can conversion.
Fig. 8 then discloses the 3rd embodiment, and it is to be that lowest-order regional metal line 68 is different with the insulation mode between the semiconductor wafer substrate 50 equally that the 3rd embodiment follows the difference of first embodiment.As shown in Figure 8, present embodiment utilizes an insulating barrier 84 to be used as insulation, and lowest-order regional metal line 68 contacts with this insulating barrier 84 and do not suspend.Insulating barrier 84 for example can be the silicon nitride of Low Pressure Chemical Vapor Deposition or the formation of plasma enhanced chemical vapor deposition method, and its thickness is between 100 to 1000 dusts.Silicon oxynitride is not poor to the etching selection rate (etch selectivity) of silica yet, also can be as the usefulness of insulation.
Among aforementioned each embodiment,, also can be applicable to in the CMOS integrated circuit of air as low dielectric constant with the mode of lowest-order regional metal line 68 as conductor structure.
Below to preferred embodiment the present invention being described, is the above, be merely to make those skilled in the art be easy to understand content of the present invention, and be not to be used for limiting interest field of the present invention.To those skilled in the art, when can in spirit of the present invention, thinking immediately and various equivalence variation.For example, material, number of metal, the etching mode among the above each embodiment is all for example, and also other has the possibility that various equivalences change.So all according to a notion of the present invention and spirit impartial for it a variation or modification, all should be included in the scope of claims of the present invention.
Claims (11)
1. a MEMS is characterized in that, comprises:
A substrate;
Position at least one transistor on this substrate, this transistor is positioned at a cmos circuit district and electrically connects with a contact hole hitching post;
At least one microcomputer electric component is positioned at a micro electromechanical structure district; And
The one lowest-order zone line in same steps as, processed with same material with this contact hole hitching post, this microcomputer electric component couples with this transistor via this lowest-order zone line.
2. MEMS as claimed in claim 1, wherein, this transistor comprises gate dielectric layer, grid, source electrode and drain electrode, and this source electrode electrically connects with one of drain electrode and this contact hole hitching post.
3. MEMS as claimed in claim 1, wherein, this lowest-order zone link material comprises metal.
4. MEMS as claimed in claim 2, wherein, the metal material of this lowest-order zone line comprises tungsten, aluminium, copper or its alloy.
5. MEMS as claimed in claim 2, wherein, the metal of this lowest-order zone line is to utilize inserted technology or plasma etch techniques to form.
6. MEMS as claimed in claim 1; Wherein, At least under the line of this lowest-order zone and between this substrate, this MEMS also include one be close to this substrate insulating barrier, and this lowest-order zone line contacts with this insulating barrier and not suspension.
7. MEMS as claimed in claim 6, wherein, this insulating layer material is selected from silicon nitride or silicon oxynitride.
8. MEMS as claimed in claim 1, wherein, this substrate locates to be provided with at least one wellblock under this lowest-order zone line, so that this substrate and this lowest-order zone line electrical isolation.
9. MEMS as claimed in claim 8, wherein, this wellblock comprises and the opposite light doped region of substrate conduction kenel, and the dense doped region that is arranged in light doped region.
10. MEMS as claimed in claim 1; Wherein, Also include one be close to this substrate composite bed; Under the line of this lowest-order zone and between this substrate, and this lowest-order zone line contacts with this composite bed and not suspension, and this composite bed comprises a top compound crystal silicon pattern and a below dielectric pattern.
11. MEMS as claimed in claim 10, wherein, this compound crystal silicon pattern non-impurity-doped, and this dielectric pattern material is selected from silica and high dielectric constant material.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101347494A CN101870445B (en) | 2009-04-22 | 2009-04-22 | Circuit lead structure and micro-electromechanical system |
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| CN2009101347494A CN101870445B (en) | 2009-04-22 | 2009-04-22 | Circuit lead structure and micro-electromechanical system |
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| Publication Number | Publication Date |
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| CN101870445A CN101870445A (en) | 2010-10-27 |
| CN101870445B true CN101870445B (en) | 2012-07-04 |
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| CN105523518B (en) * | 2014-09-29 | 2017-08-08 | 原相科技股份有限公司 | Microcomputer electric component with low substrate coupling effect |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6012336A (en) * | 1995-09-06 | 2000-01-11 | Sandia Corporation | Capacitance pressure sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6012336A (en) * | 1995-09-06 | 2000-01-11 | Sandia Corporation | Capacitance pressure sensor |
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| CN101870445A (en) | 2010-10-27 |
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Granted publication date: 20120704 Termination date: 20210422 |