CN101882583A - Trenched-gate field effect transistors and forming method thereof - Google Patents
Trenched-gate field effect transistors and forming method thereof Download PDFInfo
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- CN101882583A CN101882583A CN2010102182330A CN201010218233A CN101882583A CN 101882583 A CN101882583 A CN 101882583A CN 2010102182330 A CN2010102182330 A CN 2010102182330A CN 201010218233 A CN201010218233 A CN 201010218233A CN 101882583 A CN101882583 A CN 101882583A
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Abstract
The invention discloses a kind of Trenched-gate field effect transistors and forming method thereof.Integrated field-effect transistor of a kind of monolithic and Schottky diode comprise the gate trench that extends in the semiconductor region.Source area with fundamental triangle is positioned at the side of each side of gate trench.Contact openings extends in the semiconductor region between adjacent gate trenches.Conductor layer fill contact openings with: (a) at least a portion along the sloped sidewall of each source area electrically contacts source area, and (b) along the bottom electrical contact semiconductor district of contact openings, wherein, conductor layer and semiconductor region formation Schottky contacts.
Description
The application is the dividing an application that be on April 4th, 2006, denomination of invention the applying date for No. 200680018774.0 Chinese patent application of " Trenched-gate field effect transistors and forming method thereof ".
The reference of related application
The application requires the priority of No. the 60/669th, 063, the U.S. Provisional Application submitted on April 6th, 2005, and its full content is hereby expressly incorporated by reference.The full content of following patent application is hereby expressly incorporated by reference: the 60/588th, No. 845 U.S. Provisional Application of submitting on July 15th, 2004; The 11/026th, No. 276 U. S. application of submitting on December 29th, 2004; And the 09/844th, No. 347 U. S. application of submitting to April 27 calendar year 2001 (publication number US2002/0008284).
Technical field
The present invention relates in general to power semiconductor technologies, and especially relates to accumulation type and enhancement mode ditch grid (trenched-gate) field-effect transistors (FET) and manufacture method thereof.
Background technology
Critical component in the power electronics applications is a solid-state switch.IGNITION CONTROL from automobile is used all needs a kind of mains switch that is fit to concrete application requirements best to battery-driven consumer electronics, the power converter in the commercial Application again.Solid-state switch for example comprises power metal oxide semiconductor field-effect transistor (power MOSFET), igbt (IGBT) and various types of thyristor, and sustainable development is to satisfy this requirement.Under the situation of power MOSFET, a lot of technology have been developed, comprising for example, double diffusion structure (DMOS) with lateral channel (channel) (for example, No. the 4th, 682,405, people's such as Blanchard United States Patent (USP)), ditch grid structure (for example, people's such as Mo United States Patent (USP) the 6th, 429, No. 481) and various technology (for example, the United States Patent (USP) the 4th of Temple that is used for the charge balance in transistor drift district, 941, No. 026; No. the 5th, 216,275, the United States Patent (USP) of Chen; And No. the 6th, 081,009, the United States Patent (USP) of Neilson), to satisfy different and often to be competitive performance requirement.
The performance characteristics of some regulations of mains switch is its conducting resistance (on-resistance), puncture voltage (breakdown voltage) and switching speed (conversion speed, switching speed).According to the needs of concrete application, different focuses on each performance index (performance standard).For example, for the application of power greater than about 300-400 volt, compare with power MOSFET, IGBT has demonstrated intrinsic than low on-resistance, but since its its switching speed of closing property (turn off characteristic) is lower slowly.Therefore, for need low on-resistance have low switching frequency greater than 400 volts application, IGBT is preferred switch, and power MOSFET often is the selected device of using for upper frequency.If the frequency requirement of given application has been stipulated employed switchtype, voltage request has just determined the structure of concrete switch to form so.For example, under the situation of power MOSFET, because the proportionate relationship between drain electrode-source on-state resistance RDSon and the puncture voltage, it is challenging improving transistorized voltage characteristic when keeping low RDSon.The various charge balance structure in transistor drift district have been developed, successfully to have defeated this challenge in various degree.
Two kinds of different field-effect transistors are accumulation type FET and enhancement mode FET.In traditional accumulation type FET, (reverse raceway groove, inversionchannel), thereby channel resistance eliminated, thereby improved transistor power handling capability and efficient thereof owing to do not form inversion channel.And, owing to there is not pn body diode (body diode, body diode), reduced the loss that causes by the pn diode in the circuit of synchronous rectification.Tradition accumulation type transistorized shortcoming be the drift region need be low-doped (light dope, lightly doped) to support sufficiently high reverse bias.Yet low-doped drift region has caused higher conducting resistance and lower efficient.Similarly, in enhancement mode FET, improving transistorized puncture voltage is cost with higher conducting resistance often, and vice versa.
The device performance parameter also is subjected to the influence of manufacturing process., carry out various trials, to solve these challenges of part by the various improved treatment technologies of exploitation.No matter be in ultralight consumer electronic devices (consumer electronic device) just, still in the router and hub of communication system, the various application of mains switch increase along with the development of electronics industry.Therefore mains switch belongs to the semiconductor device with high potentiality to be exploited.
Summary of the invention
The present invention is directed to power device and their manufacture method provides various embodiments.Briefly, according to an aspect of the present invention, Schottky (Schottky) diode preferably is integrated in the individual unit (singlecell) with accumulation type FET or enhancement mode FET.According to other aspects of the invention, provide the method for making various power transistor structures with autoregistration feature and other advantage and feature.
According to a kind of embodiment of the present invention, integrated (monolithicallyintegrated) field-effect transistor of monolithic and Schottky diode comprise the gate trench that extends in the semiconductor region.Source area with fundamental triangle shape is positioned at the side of each side of gate trench.Contact openings extends in the semiconductor region between adjacent gate trenches territory.Conductor layer fill contact openings with: (a) at least a portion along each source area sloped sidewall electrically contacts source area, and (b) along the bottom electrical contact semiconductor district of contact openings, wherein, conductor layer and semiconductor region formation Schottky contacts.
According to another embodiment of the present invention, the integrated groove of monolithic (monolithicallyintegrated trench) FET and Schottky diode comprise the gate trench that extends in the epitaxial loayer and end at this, and described epitaxial loayer extends on substrate.Have concave grid (recessed gate) in each gate trench, on the concave grid top, dielectric substance is arranged.Conduction type of epitaxial loayer (conduction type, conductivity type) and substrate (substrate, substrate) identical, but doping content is lower than substrate.Source area is positioned at the side of each side of gate trench, and the end face of each source area is lower than the end face of dielectric substance.Contact openings extends in the epitaxial loayer between the neighboring gates groove.Conductor layer is filled contact openings electrically contacting source area and epitaxial loayer, and forms Schottky contacts with semiconductor region.Epitaxial loayer and source area comprise a kind of in carborundum, gallium nitride and the GaAs.
According to another embodiment of the present invention, integrated trench FET of monolithic and Schottky diode comprise the gate trench that extends in the first conduction type semiconductor district, have concave grid in each gate trench, and on the top of concave grid, dielectric substance is arranged.The first conduction type source area is positioned at the side of each side of gate trench.Each source area has upper surface, and its upper surface with respect to dielectric substance is recessed into, and described dielectric substance is on the top of corresponding concave grid.Extend between corresponding source area and semiconductor region along the sidewall of each gate trench in this tagma of second conduction type (body region).Contact openings extends in the semiconductor region between adjacent gate trenches.Conductor layer is filled contact openings and is electrically contacted source area, this tagma and semiconductor region, and conductor layer and semiconductor region formation Schottky contacts.
According to another embodiment of the present invention, integrated trench FET of monolithic and Schottky diode comprise the gate trench that extends in the semiconductor region, have grid in each gate trench, and on the top of grid dielectric substance are arranged.Semiconductor source interpolar spacer (sourcespacer) is positioned at the side of each side of gate trench, so that form contact openings between between per two neighboring gates grooves each is to adjacent semiconductor source interpolar spacer.Conductor layer is filled contact openings and contact semiconductor source electrode interval body and semiconductor region, and forms Schottky contacts with semiconductor region.
According to another embodiment of the present invention, integrated trench FET of monolithic and Schottky diode comprise the gate trench that extends in the first conduction type semiconductor district.The source area of first conduction type is positioned at the side of each side of gate trench.Bucking electrode is placed along the bottom of each gate trench, and by shield dielectric layer and semiconductor region insulation.Grid is arranged in the bucking electrode top of each groove, and has dielectric layer between grid and the bucking electrode.Dielectric cap (dielectric cap, dielectric cap) is positioned at the grid top.Conductor layer contact source area and semiconductor region make conductor layer and semiconductor region form Schottky contacts.
Below in conjunction with accompanying drawing, these and other aspect of the present invention is explained in more detail.
Description of drawings
Fig. 1 is the simplification viewgraph of cross-section of ditch grid accumulation (accumulation) FET with integrated Schottky of exemplary embodiment according to the present invention;
Fig. 2 A-2I is the simplification viewgraph of cross-section of the exemplary embodiment according to the present invention, and it shows each processing step that is used to form the integrated FET Schottky diode structure among Fig. 1;
Fig. 3 A-3E is the simplification viewgraph of cross-section of another exemplary embodiment according to the present invention, and it shows the alternative techniques step of the latter part of step in the processing step shown in Fig. 2 G-2I;
Fig. 3 EE is the simplification viewgraph of cross-section that substitutes embodiment, and wherein, the dielectric spacers in Fig. 3 A-3E processing step had been removed before forming the top side conductor layer;
Fig. 4 is the simplification cross-sectional view of the modification of structure among Fig. 3 EE, and wherein, bucking electrode forms below grid;
Fig. 5 is the simplification cross-sectional view of the modification of structure among Fig. 3 E, and wherein, contact openings extends to and the about identical degree of depth of gate trench;
Fig. 6 is the simplification viewgraph of cross-section of the enhancement mode modification of accumulation FET-Schottky diode structure among Fig. 5;
Fig. 7 A shows simulation (emulation) result, wherein, shows the electric field line of two SiC base accumulation FET, and one has darker Schottky contacts than another and is recessed into (contact depression, contact recess);
Fig. 7 B is about the drain current of two kinds of recessed situations of darker and more shallow Schottky contacts and the simulation curve figure of drain voltage;
Fig. 8 is the simplification viewgraph of cross-section of the ditch grid accumulation FET with polysilicon source electrode interval body of exemplary embodiment according to the present invention;
Fig. 9 A-9H, Fig. 9 I-1 and Fig. 9 J-1 are the simplification viewgraph of cross-section of the exemplary embodiment according to the present invention, show each processing step of the FET-Schottky diode structure that is used to form among Fig. 8;
Fig. 9 I-2 and Fig. 9 J-2 simplify viewgraph of cross-section, show the alternative techniques step corresponding to the step of Fig. 9 I-1 and Fig. 9 J-1, and it has produced the modification of FET-Schottky diode structure among Fig. 8;
Figure 10 and Figure 11 simplify viewgraph of cross-section, show the modification of FET-Schottky junction structure among Fig. 9 J-1 and Fig. 9 J-2 respectively, and wherein, bucking electrode is formation below grid;
Figure 12 be according to the present invention another embodiment have a simplification viewgraph of cross-section that bucking electrode is positioned at the ditch grid accumulation FET-Schottky junction structure under the grid;
Figure 13 simplifies viewgraph of cross-section, and it shows the modification of Figure 11 embodiment, wherein, has changed schottky region between the adjacent trenches to form the MPS structure;
Figure 14 shows drain current-drain voltage performance plot (left figure) and grid voltage-gate charge (right figure) figure of FET-Schottky junction structure among Fig. 1;
Figure 15 A-15H is the simplification viewgraph of cross-section of another embodiment according to the present invention, shows each processing step that is used to form the ditch grid FET with autoregistration characteristic;
Figure 16 shows the isometric view of the p-raceway groove ditch grid FET with on-plane surface end face (before top metal forms) of another embodiment according to the present invention;
Figure 17 A, Figure 17 B-1 and Figure 17 B-2 are two viewgraph of cross-section of simplifying processing step that are used to form FET among Figure 16;
Figure 18 is the viewgraph of cross-section according to the specific embodiment of the invention, shows the technology that is used to form autoregistration source electrode and heavy this tagma (heavy tagma, heavy body region);
Figure 18 A-18I is the viewgraph of cross-section of the different process step that is used to form the ditch grid FET shown in Figure 18 of exemplary embodiment according to the present invention;
Figure 19 A-19H is the viewgraph of cross-section of different process step in the processing step of another exemplary embodiment according to the present invention, wherein, has formed non-surperficial polysilicon, and has compared with the technology of Figure 18 A-18I, and the quantity of mask has reduced;
Figure 20 A-20G is the viewgraph of cross-section of the another exemplary embodiment according to the present invention, and it shows another processing step, and wherein, with comparing among Figure 18 A-18I, the quantity of mask has reduced;
Figure 21 A-21H is the viewgraph of cross-section of the exemplary embodiment according to the present invention, and it shows the processing step that is used to form ditch grid FET (this ditch grid FET is similar to by Figure 18 A-18I and obtains, except Schottky diode and FET are integrated);
Figure 22 A-22F is the viewgraph of cross-section of another embodiment according to the present invention, and it shows the another processing step that is used for forming with the number of masks that reduces ditch grid FET;
Figure 23 A-23I is the viewgraph of cross-section of the different process step that is used to form the ditch grid FET with autoregistration feature of another embodiment according to the present invention; And
Figure 24 A-24I shows the viewgraph of cross-section of the different process step that is used to form the ditch grid FET with autoregistration feature of another embodiment according to the present invention.
Embodiment
Mains switch can be by any is realized in power MOSFET, IGBT, all types of thyristor etc.For illustrative purposes, be described in many new technologies that this presented situation with power MOSFET.Yet should be appreciated that each embodiment of the present invention described here is not limited to power MOSFET and can be applied to the mains switch technology of many other types, for example comprise the bipolarity switch of IGBT and other type.And for illustrative purposes, shown the specific embodiment of the present invention comprises specific p type district and n type district.It will be appreciated by those skilled in the art that instruction herein can of equal value be applied to respectively distinguish the opposite device of conductibility.
The ditch grid that the preferred and Schottky diode that Fig. 1 shows according to the present invention exemplary embodiment is integrated in individual unit accumulate the simplification viewgraph of cross-section of field-effect transistors (FET).Low-doped n type epitaxial loayer 104 extends on the n of high doped type substrate 102 and contact with it.Gate trench 106 extends in the epitaxial loayer 104 and ends at this.Each gate trench 106 (is arranged, line) dielectric layer 108 is arranged, and comprise concave grid (recessed gate) 110 and the insulating material 112 on concave grid 110 tops along its sidewall and bottom lining.The conductive triangle source area 114 of n type is positioned at the side of groove 106 each side.Source area 114 polysilicon gate 110 that vertically overlaps.In this application as high voltage FET, this overlaps not necessarily, and wherein, lacking overlapping can produce minimum influence to transistor conduct resistance Rdson.Lack gate-to-source and overlap and to influence Rdson in the low-voltag transistor greatly, thereby its appearance is favourable in such transistor.
The recessed portion of epitaxial loayer 104 and source area 114 form the V-arrangement contact openings 118 with rounded bottom together.Schottky barrier metal (barrier metal) 120 is structurally extended and is filled contact openings 118 and contacts with source area 114 with the sloped sidewall along source area 114, and contacts with epitaxial loayer 104 at its recessed portion.Because source area 114 is highly doped and epitaxial loayer 104 is low-doped, thereby top side conductor layer 120 forms ohmic contact and forms Schottky contacts with epitaxial loayer 104 with source area 114.In an embodiment, Schottky barrier metal 120 comprises titanium.Dorsal part conductor layer 122 for example comprises aluminium (or titanium), contact substrate 102.
Different with enhancement transistor, the accumulation type transistor in Fig. 1 structure 100 does not comprise this tagma or the blocking-up trap (inaccessible trap, blocking well) (being the p type in this example) that wherein is formed with conduction (conduction channel).What substitute is, when accumulation layer in epitaxial loayer 104 when trenched side-wall forms, the formation conductive channel.According to the doping content of channel region and the doping type of grid 110, the transistor in the structure 100 is normally opened (conducting) or is closed (ending).When channel region exhausted fully and be reverse a little, transistor was closed.Equally, owing to do not form inversion channel (reverse raceway groove, inversion channel), therefore eliminated channel resistance, thereby improved transistor power handling capability and efficient thereof.And, owing to do not have the pn body diode, so eliminated the loss that in circuit of synchronous rectification, causes by the pn diode.
In the embodiment of Fig. 1, the FET in the structure 100 is vertical furrow grid accumulation MOSFET, and it has top side conductor layer 120 that forms source conductor and the bottom side conductor layer 120 that forms drain conductor.In another embodiment, substrate 102 is p types, thereby forms accumulation IGBT.
Fig. 2 A-2I is the simplification viewgraph of cross-section of the exemplary embodiment according to the present invention, shows each processing step that is used to form the integrated FET-Schottky diode structure 100 among Fig. 1.In Fig. 2 A, use conventional method, following epitaxial loayer 204 and last epitaxial loayer 205 order on n type substrate 202 forms.Replacedly, can use the initial wafer material (wafer material) that comprises epitaxial loayer 204,205.Last n type epitaxial loayer 205 has higher doping content than following n type epitaxial loayer 204.In Fig. 2 B, utilize known technology, use the mask (not shown) limit with etching silicon to form groove 206, this groove 206 passes epitaxial loayer 205 and ends at down epitaxial loayer 204.In the process that forms groove, can use traditional doing or wet etching.In Fig. 2 C, structurally growth or deposition for example comprise the dielectric layer 208 of oxide, thereby the sidewall of groove 206 and bottom are lined with dielectric layer 208.
In Fig. 2 D, use conventional art deposit spathic silicon layer 209 subsequently with filling groove 206.Polysilicon layer 209 can in-situ dopedly obtain required grid doping type and concentration.In Fig. 2 E, use traditional technology, the deep erosion in (etch-back, etch back) polysilicon layer 209 and the recessed groove 206 to form grid 210.Concave grid 210 (recessed gate) vertically overlaps and goes up epitaxial loayer 205.As mentioned above, according to application target and purpose of design, epitaxial loayer 205 (that is, processing step and final structure needn't be subjected to the restriction of this overlapping) on concave grid 210 need not to overlap.In other embodiment, grid 210 comprises polycrystal carborundum (polysilicon carbide, polysilicon carbide) or metal.
In Fig. 2 F, for example structurally form the dielectric layer 211 that forms by oxide and use traditional technology to carry out planarization subsequently.In Fig. 2 G, at least go up blanket etching (the felt formula etching of the dielectric layer 211 (at active area (activeregion)) of implementing planarization at the active area (active area) of device, blanket etch), to expose the surf zone of epitaxial loayer 205, the part 212 of dielectric layer 211 is retained in the concave grid 210 simultaneously.In Fig. 2 H, utilize traditional technology, in active area, implement blanket formula inclination (blanket angled) silicon etching (for example) at least in the dry ecthing of active area, have the V-arrangement contact openings 218 of round bottom with formation.Contact openings 218 extends and passes through last epitaxial loayer 205 fully, thereby forms two source areas 214 between per two adjacent grooves.Contact openings 218 stretches into and ends at down the first half of epitaxial loayer 204.
In Fig. 2 I, top side conductor layer 220 uses conventional art to form.Top side conductor layer 220 comprises Schottky barrier metal.As shown in the figure, top side conductor layer 220 is filled contact openings 218, so that contact with source area 214 along the sloped sidewall of source area 214, and contacts with following epitaxial loayer 204 along the bottom of contact openings 218.Since source area 214 be highly doped and down epitaxial loayer 204 be low-doped, so top side conductor layer 220 forms ohmic contact with source area 214, and with following epitaxial loayer 204 formation Schottky contacts.As can be seen, source area 214 and Schottky contacts for (about) groove 206 is self aligned.
Fig. 3 A-3E is the simplification cross-sectional view of another exemplary embodiment according to the present invention, shows the alternative techniques step by back a part of processing step of the processing step shown in Fig. 2 G-2I.Therefore, in this embodiment, implement by the identical processing step shown in Fig. 2 A-2G, and forward to by the step shown in Fig. 3 B (step shown in Fig. 3 A is identical with the step shown in Fig. 2 G).In Fig. 3 B, last epitaxial loayer 305 sufficiently to expose the upper side wall of dielectric substance 312, is used to hold the dielectric spacers 316 that forms subsequently by dark etching.In a kind of embodiment, second epitaxial loayer 305 is by the amount of dark etching 0.05-0.5 mu m range.In Fig. 3 C, use conventional art, interval body 316 is adjacent to the upper side wall of the dielectric substance 312 that has exposed and forms.Interval body 316 is to make with the dielectric substance that is different from dielectric substance 312.For example, if dielectric substance 312 is made by oxide, then interval body 316 can be made by nitride.
In Fig. 3 D, the exposed surface area of last epitaxial loayer 305 is recessed and pass through epitaxial loayer 305 fully, thereby forms the contact openings 318 that stretches into down epitaxial loayer 304.Also fully by last epitaxial loayer 305, the part 314 that is located immediately under the interval body 316 that only goes up epitaxial loayer 305 has kept by recessed.Part 314 forms transistorized source area.As can be seen, the source area 314 of contact openings 318 and so formation is self aligned for groove 306.In Fig. 3 E, top side conductor layer 320 and bottom side conductor layer 322 use conventional art to form.Conductor layer 320 comprises Schottky barrier metal.As shown in the figure, top side conductor layer 320 is filled contact openings 318, so that contact with source area 314 along the sidewall of source area 314, and contacts with the recessed portion of following epitaxial loayer 304.Owing to source area 314 is that the highly doped epitaxial loayer 304 that descends is low-doped, so top side conductor layer 320 forms ohmic contact with source area 314, and with following epitaxial loayer 304 formation Schottky contacts.
In the alternative embodiment shown in Fig. 3 EE, before forming the top side conductor layer, dielectric spacers 316 has been removed, thus the end face of source of exposure polar region 314.Top side conductor layer 321 contacts with sidewall along the end face of source area 314 thus.Thereby reduced the source electrode contact resistance.In the replaceable modification of above-mentioned each embodiment, used known technology to form dielectric of the thick end (thickbottom dielectric) with bottom before forming grid along each groove.Thick bottom-dielectric has reduced miller capacitance (millercapacitance).
As can be seen, Schottky diode preferably is integrated in individual unit with FET in described from here each embodiment, repeatedly repeats this operation in such cellular array.Equally, Schottky contacts and source area are self aligned for groove.In addition, Schottky contacts has caused low on-resistance Rdson, thereby has caused low conducting loss, and has improved transistorized reverse recovery characteristic.Under the situation that does not need the dense cell spacing, also obtained good blocking ability (block capability, blocking capability).
In the illustrative processes step shown in Fig. 2 A-2I and Fig. 3 A-3E, use diffusion or injection (to implant, implantation).Though can carry out these processing steps with traditional crystalline silicon material, but they are particularly suitable for using the material of another type, such as carborundum (SiC), gallium nitride (GaN) and GaAs (GaAs), wherein, diffusion, injection and dopant activation technology are difficult to finish and control.In such embodiment, substrate, down epitaxial loayer and last epitaxial loayer and transistorized other district can comprise a kind of among SiC, GaN and the GaAs.In addition, in traditional silicon carbide-based enhancement mode FET, inversion channel is especially big to the contribution of conducting resistance.On the contrary, quite little for the conducting resistance contribution of the accumulation channels in the transistorized carborundum embodiment of the accumulation among Fig. 2 I and Fig. 3 E.
Fig. 4 shows the viewgraph of cross-section of another embodiment of the present invention.In Fig. 4, bucking electrode 424 forms under grid 410.Bucking electrode 424 insulate by shielding dielectric 425 and following epitaxial loayer 404, and by inter-electrode dielectric (iner-electrodedielectric) 427 and grid 410 insulation that overlap.Bucking electrode 424 helps to make miller capacitance to be decreased to negligible amount, thereby reduces transistorized switching loss tempestuously.Although do not have shown in Figure 4ly, bucking electrode 424 also is electrically connected to source area 414, perhaps is connected to earth potential, perhaps stipulates to be electrically connected to other current potential according to design and performance requirement.If necessary, can under each grid 410, form the more than one bucking electrode that is biased in identical or different current potential.One or more methods that are used to form such bucking electrode are disclosed in top mentioned common transfer (commonly assigned) application the 11/026th, 276.And, application other charge balance structure disclosed in the 11/026th, No. 276 also can with combine in this each disclosed embodiment, with the further performance characteristics of improving device.
The shortcoming of the silicon carbide-based ditch gate transistor that some is traditional is that gate oxide breakdown voltage is low.According to the present invention,, for example, solve this problem greater than half the degree of depth of the gate trench degree of depth by deeper extending to Schottky contacts is recessed.Fig. 5 shows exemplary embodiment, and wherein, Schottky contacts is recessed to be extended to and the gate trench 506 approximately uniform degree of depth.Dark Schottky contacts is used for gate oxide 508 and high electric field shielding, thereby improves the puncture of gate oxide.This can find out from Fig. 7 A, the figure shows the analog result of two SiC base accumulation FET, and it is recessed that one of them has darker Schottky contacts.Eliminated in having the transistor (left figure) that darker Schottky contacts is recessed into situation along the electric field line of the bottom appearance of the groove that has the recessed transistor (right figure) of more shallow Schottky contacts.The reaction of electric field line among the right figure under the gate trench (reflection, reflect) electric field that increases from bottom to top.That is, the electric field line that minimum electric field line is the highest corresponding to the highest electric field is corresponding to minimum electric field.
Another recessed advantage of dark Schottky contacts is: the transistor leakage under blocking state has reduced.This clearly show that in the analog result of Fig. 7 B, wherein is recessed at the recessed and more shallow Schottky contacts of darker Schottky contacts, has drawn the curve of drain current to drain voltage.Just as can be seen, when drain voltage when 0V is increased to 200V, under the recessed situation of more shallow Schottky contacts, drain current rises continuously, and recessed for darker Schottky contacts, the drain current held stationary.Therefore, by Schottky contacts is recessed in the epitaxial loayer 504 dearly, transistor leakage has obtained substantively to reduce and obtained higher gate oxide breakdown.
Dark recessed Schottky contacts structure (for example, among Fig. 5) is particularly suitable for silicon carbide-based transistor, and this is because the degree of depth that gate trench extends in epitaxial loayer need not as silicon-based transistor.This allows more shallow Schottky contacts recessed (it is easy to limit and etching).Yet the similar structures for using other types of material (as SiC, GaN and GaAs) can obtain the similar improvement of gate oxide breakdown and transistor leakage aspect.
Fig. 6 shows the enhancement mode FET modification of accumulation FET in Fig. 5 structure.In Fig. 6, extend under respective sources polar region 614 along each trenched side-wall in this tagma 613 of p type.As shown in the figure, dark contact openings 618 extends under the bottom surface in this tagma 613, so that form Schottky contacts between top side conductor layer 620 and N-epitaxial loayer 604.The same with traditional MOSFET, as the MOSFET among Fig. 6 during in conducting state, electric current flows through along this tagma the raceway groove that each trenched side-wall of 613 extends.In the modification of Fig. 6 embodiment, removed interval body 616, thereby top side conductor layer 620 contacts with source area 614 along its end face.
Fig. 8 shows the viewgraph of cross-section of the accumulation type FET that has the interval body source area of another exemplary embodiment according to the present invention, and this interval body source area preferably is integrated into individual unit with Schottky diode.N type epitaxial loayer 1104 extends on n type substrate 1102 and contact with it.Gate trench 1106 stretches into epitaxial loayer 1104 and ends at this.Each gate trench 1106 is lined with dielectric layer 1108 along its sidewall and bottom surface, and comprises grid 1110 and the insulating material 1112 on grid 1110 tops.The interval body source area 1114 of n section bar material (for example n type polysilicon) is on epitaxial loayer 1104 and be positioned at the side of each side of groove 1106.
Interval body source area 1114 forms contact openings 1118, passes this opening, and top side conductor layer 1120 electrically contacts epitaxial loayer 1104 and source area 1114 simultaneously.Top side conductor layer 1120 comprises Schottky barrier metal.Because epitaxial loayer 1104 is low-doped, so top side conductor layer 1120 forms Schottky contacts with epitaxial loayer 1104.
The same in the embodiment as described above, the accumulation type transistor in the structure 1100 does not comprise this tagma or the blocking-up trap (being the p type in this example) that wherein is formed with conduction (conduction channel).Alternatively, when accumulation layer is formed in the epitaxial loayer 1104 along trenched side-wall, formed conducting channel.The doping content of channel region and the doping type of grid 1110 are depended in normally opening (conducting) or closing (ending) of FET in the structure 1100.When channel region exhausted fully and be anti-phase a little, it was closed.Equally, owing to do not form inversion channel, so channel resistance eliminated, thereby improved transistorized power handling capability and efficient thereof.In addition, owing to be not the pn body diode, therefore the loss that is caused in circuit of synchronous rectification by the pn diode has been eliminated.
In the embodiment of Fig. 8, the FET in the structure 1100 is vertical ditch-grid accumulation MOSFET, and wherein, top side conductor layer 1120 forms source conductor and bottom side conductor layer (not shown) forms drain conductor.In another embodiment, substrate 1102 can be that the p type is to form accumulation IGBT.
Fig. 9 A to Fig. 9 H, Fig. 9 I-1 and Fig. 9 J-1 show the viewgraph of cross-section according to the different process step of the specific embodiment of the invention, and this processing step is used to form FET/ Schottky diode structure 1100 integrated among Fig. 8.In Fig. 9 A, n type epitaxial loayer 1204 uses conventional art to form on n type substrate 1202.Replacedly, can use the initial wafer that comprises epitaxial loayer 1204.In Fig. 9 B, use conventional art, mask (not shown) to be used for limiting and etching silicon with the formation groove.In the process that forms groove, can use traditional dry ecthing or wet etching.Groove 1206 stretches into epitaxial loayer 1204 and ends at this.In Fig. 9 C, structurally grow or dielectric layer deposition 1208 (for example comprising oxide), so that the sidewall of groove 1206 and bottom are lined with dielectric layer 1208.
In Fig. 9 D, use conventional art deposit spathic silicon layer 1209 with filling groove 1206.Polysilicon layer 1209 can be in-situ doped to obtain the grid doping type and the concentration of expectation.In Fig. 9 E, use the dark etching polysilicon layer 1209 of conventional art and be recessed to form concave grid 1210 at groove 1206.
In Fig. 9 F, dielectric layer 1211 (for example comprising oxide) structurally forms and uses subsequently the conventional art planarization.In Fig. 9 G, go up the enforcement blanket etching at the dielectric layer 1211 (at least at active area) of planarization, to expose the surface region of epitaxial loayer 1204, the part 1212 of dielectric layer 1211 remains on grid 1210 simultaneously.In Fig. 9 H, epitaxial loayer 1204 is by dark etching, and the sidewall that sufficiently exposes dielectric substance 1212 is to hold the source electrode interval body 1214 that forms subsequently.In Fig. 9 I-1, deposited conductive layer (for example polysilicon) and made its sidewall that exposes that is etched with deeply in abutting connection with dielectric substance 1212 form highly doped source electrode interval body 1214 subsequently.Be used to form at polysilicon under the situation of source electrode interval body 1214, polysilicon can be in-situ doped to obtain highly doped source electrode interval body.In Fig. 9 J-1, conductor layer 1220 usefulness conventional arts in top side form.Conductor layer 1220 comprises Schottky barrier metal.In a kind of embodiment, conductor layer 1220 comprises titanium.As shown in the figure, source electrode interval body 1214 forms contact openings 1218, by this opening, and top side conductor layer 1220 contact epitaxial loayers 1204.Conductor layer 1220 also contacts source electrode interval body 1214.Because source electrode interval body 1214 is highly doped and epitaxial loayer 1204 is low-doped, so top side conductor layer 1220 forms ohmic contact and forms Schottky contacts with epitaxial loayer 1204 with source electrode interval body 1214.
Fig. 9 I-2 and Fig. 9 J-2 are viewgraph of cross-section, show the alternative techniques step of step shown in Fig. 9 I-1 and Fig. 9 J-1, and it has produced the modification of structure among Fig. 8.Opposite with the step of Fig. 9 I-1 (being stopped when wherein expose on the polysilicon surface that is etched in epitaxial loayer 1204), in the step shown in Fig. 9 I-2, the polysilicon etching is continuously with the epi region of exposing between the recessed source electrode interval body.As can be seen, because this extra etching, the source electrode interval body 1215 among Fig. 9 I-2 is less than the source electrode interval body 1214 among Fig. 9 I-1.In Fig. 9 J-2, top side conductor layer 1221 forms with conventional art on structure.Top side conductor layer 1221 forms ohmic contact with source electrode interval body 1215, and forms Schottky contacts with epitaxial loayer 1204 in district 1219.
As can be seen, Schottky contacts and source electrode interval body are self aligned about groove 1406.In addition, Schottky contacts produces lower conducting resistance Rdson, from but lower conducting state loss and has improved transistorized reverse recovery characteristic.And, under the situation that need not the compact unit spacing, obtained good blocking ability.And as described in conjunction with Fig. 7 curve chart, the further advantage of the recessed Schottky contacts of Fig. 9 I-2, Fig. 9 J-2 embodiment is: the transistor leakage of blocking state (blocked state, blocking state) has reduced.And the area that polysilicon source electrode interval body takies is less than the conventional diffusion source area.This advantage has produced bigger Schottky contacts area.
Figure 10 shows the viewgraph of cross-section of the modification of Fig. 8 embodiment, and wherein bucking electrode 1324 forms under grid 1310.Bucking electrode 1324 helps miller capacitance is decreased to negligible amount, thereby reduces transistorized switching loss tempestuously.Can make bucking electrode 1324 electrical bias in the current potential identical with the source electrode interval body, or electrical bias in earth potential or electrical bias in other current potential by design and performance requirement defined.If necessary, an above bucking electrode that is biased in identical or different current potential can form under each grid 1310.One or more methods that are used to form such bucking electrode are disclosed in above-cited common assigning an application in the 11/026th, No. 276.
Use in the recessed Schottky contacts and use the advantage in the bucking electrode can be by they be realized in the single structure combination, shown in two examples of Figure 11 and Figure 12 like that.Figure 11 shows and use recessed Schottky contacts and bucking electrode in the accumulation type FET that has polysilicon source electrode interval body 1415.Figure 12 shows and use recessed Schottky and bucking electrode in having the accumulation type FET of source area 1517, and wherein, this source area is to use traditional method of diffusion to form.Figure 13 shows the modification of Figure 11 embodiment, wherein, changes schottky region and makes it merge p type district 1623.P type island region 1623 can form by injected p type alloy in schottky region before forming top side conductor layer 1620.Like this, the merging P-i-N Schottky of knowing (Merged P-i-N Schottky) (MPS) has formed in the zone of structure between adjacent trenches.In fact, blocking junction is incorporated in the accumulation transistor (accumulation transistor).As known in the art, the MPS structure reduces transistorized leakage when blocking state.
Figure 14 shows the analog result of using the structure among Fig. 1.Used MEDICI device simulation device.Figure 14 comprises left figure (wherein having drawn the curve of drain current to drain voltage) and right figure (wherein having drawn the curve of grid voltage to gate charge).Shown in left figure, obtained 1 * 10
-14The low current leakage of A/ μ m and the BVDSS that is higher than 35V, and as shown at right, bucking electrode helps to eliminate miller capacitance.
In the illustrative processes step shown in Fig. 9 A-9H, Fig. 9 I-1, Fig. 9 J-1, Fig. 9 I-2 and Fig. 9 J-2 and in the exemplary crystal tubular construction of Figure 10 and Figure 11, do not use DIFFUSION TREATMENT or inject processing.Though can use these processing step and structures with traditional crystalline silicon material, but be particularly suitable for using the material of other type, such as carborundum (SiC), gallium nitride (GaN), GaAs (GaAs), at this, diffusion, injection and dopant activation are handled and are difficult to realize and control.In such embodiment, the epitaxial loayer on substrate, the substrate, source area and transistorized other district can be by a kind of the making among SiC, GaN and the GaAs.And in traditional silicon carbide-based enhancement mode FET, inversion channel is especially big to the contribution of conducting resistance.On the contrary, substantially very low for the contribution of the conducting resistance of the accumulation channel in the transistorized carborundum embodiment of the accumulation among Fig. 9 J-1, Fig. 9 J-2, Figure 10 and Figure 11 (accumulation channels, accumulated channel).
Though mainly utilize accumulation type FET to describe above-mentioned embodiment, in enhancement mode FET, also can realize many above-mentioned feature and advantage.For example, the processing step among Fig. 2 A-2I and Fig. 3 A-3E can be changed on forming and form p type well region in the epitaxial loayer 204 down before the epitaxial loayer 205.Processing step among Fig. 9 A-9H, Fig. 9 I-1, Fig. 9 J-1 and Fig. 9 A-9H, Fig. 9 I-2 and the 9J-2 also can be changed into and form p type well region before forming source electrode interval body 1214 and 1215 in epitaxial loayer 1204.The many alternate manners that change said structure and processing step embodiment in order to obtain the enhancement mode FET that integrates with Schottky diode are conspicuous under the situation of this disclosure content of reading to those skilled in the art.
Figure 15 A-15H is the simplification viewgraph of cross-section of the different process step that is used to form ditch-grid FET of another embodiment according to the present invention.In Figure 15 A, this tagma 1704 of low-doped p type in n type district 1702 with traditional injection and (drive) technology that drives in form.In a kind of embodiment, n type district 1702 comprises highly doped substrate zone, and low-doped n type epitaxial loayer is formed on this substrate zone.In this embodiment, this tagma 1704 forms in n type epitaxial loayer.
In Figure 15 B, comprise that the dielectric stack (dielectric lamination, dielectric stack) of lower dielectric layer 1706, middle dielectric layer 1708 and upper dielectric layer 1710 is formed on this tagma 1704.Middle dielectric layer need be the dielectric substance that is different from upper dielectric layer.In a kind of embodiment, dielectric stack comprises oxide-nitride thing-oxide.As will be seen, the thickness of the thickness effect dielectric cap 1720 of middle dielectric layer 1708 (Figure 15 D), this dielectric cap 1720 is formed on the grid in processing step afterwards, thus dielectric layer thickness in must carefully selecting.The lower dielectric layer relative thin minimizes so that dielectric layer 1720 thickness that carry out in the subsequent process steps of removing lower dielectric layer 1702 are reduced.As shown in the figure, dielectric stack is patterned and is etched, and to limit opening 1712, gate trench formed by this opening afterwards.
In Figure 15 C, to implement traditional silicon and be etched with formation groove 1703, this groove extends through this tagma 1704 and ends at n type district 1702.Form the gate dielectric layer 1714 of trenched side-wall and bottom lining subsequently, use conventional art deposit spathic silicon layer 1716 subsequently.In Figure 15 D, polysilicon layer 1716 is recessed in the grooves to form grid 1718.Dielectric layer structurally forms and subsequently by dark etching, so that dielectric cap 1720 keeps directly over grid 1718.Nitride layer 1708 is used as etch-stop (etch stop) or etch-stop detection layers in the dark etching process of dielectric layer.In Figure 15 E, nitride layer 1708 uses conventional art optionally to be stripped to expose the sidewall of dielectric cap 1720.Thereby bottom oxide layer 1706 is retained in the top in this tagma 1704, and dielectric cap 1720 also intactly is retained on the grid 1718.
In Figure 15 F, in the active area of device, implement blanket formula source electrode and inject (blanketsource implant), with in this tagma 1704, form highly doped n type district 1722 at the either side of groove 1703.Dielectric spacers 1724 (for example, comprising oxide) forms with traditional technology along the exposed sidewalls of dielectric cap 1720 subsequently.Inject the activation of dopant and drive in (drive-in) and can carry out in this stage or the later phases of processing step.In Figure 15 G, implement the silicon etching, with the exposed surface in recessed n type district 1722, make it as shown fully by n type district 1722 and enter body district 1704.The part 1726 in the n type district 1722 that keeps under interval body 1724 forms the source area of device.Heavy this tagma 1728 forms in recessed district subsequently.In a kind of embodiment, heavy this tagma 1728 uses traditional technology to form by the etched silicon that filling has p+ type silicon.Thereby heavy this tagma 1728 and source area 1726 are for groove 1703 autoregistrations.
In Figure 15 H, dielectric cap 1720 and interval body 1724 partly are etched with the surface region of source of exposure polar region 1726 subsequently deeply.After the etching, hemisphere dielectric 1703 is retained on the grid 1718.Form top conductor layer 1732 subsequently, with contact source area 1726 and heavy this tagma 1728.Hemisphere dielectric 1730 is used for making grid 1718 and top conductor layer 1732 electric insulations.In a kind of embodiment, n type district 1702 is low-doped epitaxial loayers, wherein is extended with highly doped n type substrate (not shown) under this epitaxial loayer.In this embodiment, form dorsal part conductor layer (not shown) with contact substrate, the dorsal part conductor layer forms the drain terminal of device.Formed the ditch-grid FET that has autoregistration source electrode and heavy this tagma like this.
In replaceable embodiment, dielectric layer (for example, comprising oxide) bottom along groove 1703 before forming grid 1718 forms.The dielectric thickness in the thick end is greater than gate dielectric layer 1714, and is used for reducing the electric capacity of grid to drain electrode, improved the switching speed of device like this.In another embodiment, bucking electrode forms under grid 1718, is similar to shown in Fig. 4 and Figure 10-13 those.
In the another modification of the processing step shown in Figure 15 A-15H, with the corresponding step of Figure 15 F after, the silicon face that exposes is not recessed, and what replace is to implement that heavy body injects and injection process weighs this tagma to form, and this heavy this tagma extends through n type district 1722 and enters body district 1704.Obtained to be similar to the viewgraph of cross-section of Figure 15 G, difference is that because the cause of the diffusion of the sidepiece in the injection process, extend in heavy this tagma 1728 below dielectric spacers 1724.Dielectric spacers 1724 needs enough wide, can not fallen by full consumption in the sidepiece diffusion process in heavy this tagma to guarantee n type district 1722.This can realize by selecting thicker middle dielectric layer 1708.
The autoregistration source electrode that uses dielectric stack to obtain shown in Figure 15 A-15H can be implemented in a plurality of technology embodiments disclosed herein similarly with the technology in heavy this tagma.For example, in the technology embodiment shown in Fig. 3 A-3E, can replace with the processing step shown in Figure 15 B-15E corresponding to the processing step of Fig. 3 A-3B, so that obtain autoregistration source electrode and Schottky contacts as described below.
The mask that is used to form groove 306 in Fig. 3 A replaces with the dielectric stack of three dielectric layers, and is patterned and be etched with the formation opening, forms groove (being similar to shown in Figure 15 B and Figure 15 C) by this opening.Thereafter, in Fig. 3 B, when the opening in the ONO composite bed is filled with dielectric cap, (be similar to the dielectric cap 1720 among Figure 15 D), remove the top oxide and the middle nitride layer of ONO composite bed, with the sidewall (being similar to shown in Figure 15 E) that exposes dielectric cap.All the other treatment steps shown in Fig. 3 C-3E remain unchanged.Being recessed into of the n+ epitaxial loayer 305 that is no longer necessary for the sidewall of exposure dielectric 312 and in Fig. 3 B, implements, and can use thinner epitaxial loayer 305.
By using the processing step shown in Figure 15 B-15E to replace and the corresponding processing step of Fig. 9 B-9, the dielectric stack technology also can be implemented in the technology embodiment shown in Fig. 9 A-9J to be similar to above-mentioned mode.
Figure 16 shows the simplification isometric view of the p raceway groove ditch-grid FET with non-flat forms end face (before top metal forms) of another embodiment according to the present invention.The present invention is not limited to the p channel fet.Those skilled in the art will be appreciated that how to implement the present invention in the power transistor of n channel fet or other type by the reading present disclosure.In Figure 16, metal layer at top 1832 is peelled off to expose coating zone (bottom zone, underlying region).Similarly, for illustrative purposes, remove dielectric cap 1820 from the upper section ground of two grids 1818 on right side.As shown in the figure, extend above low-doped p type district 1802 in low-doped this tagma 1804 of n type.In a kind of embodiment, p type district 1802 is the epitaxial loayers that are formed at highly doped p type substrate (not shown) top, and this tagma 1804 is by injection known in the art with drive in suitable dopant and form at epitaxial loayer 1802.
To utilize Figure 17 A, Figure 17 B-1 and Figure 17 B-2 to describe two kinds of methods of the FET that forms Figure 16.These figure do not illustrate heavy this tagma, because these figure are corresponding to the viewgraph of cross-section along the front of the isometric view of Figure 16.In Figure 17 A, traditional injection is used in this tagma 1904 of n type and the technology that drives in forms at p type epitaxial loayer 1902.Groove 1906, be the gate insulator 1907 of groove 1906 linings and the recessed known technology formation of polysilicon gate 1918 usefulness.The structurally square one-tenth of dielectric layer is flattened subsequently, and finally by dark etching equably up to exposing silicon face.The space that is positioned at directly over each grid then is filled with dielectric cap 1920.In a kind of embodiment, the silicon mesa surface of exposing between the adjacent dielectric district 1920 is recessed into between the end face of dielectric region 1920 and the degree of depth between the bottom surface, then carries out source electrode and injects to form p type source area.In replaceable embodiment, before recessed silicon, implement the formation of source electrode.Heavy this tagma (not shown) can form before or after forming source area.
Figure 17 B-1 shows a kind of modification, wherein implemented silicon recessed (silicon dent, siliconrecess) the exposure so that the upper side wall of dielectric region 1920 becomes (that is, source area 1926 has smooth end face).Figure 17 B-2 shows another modification, and it is recessed wherein to have implemented silicon, so as the end face of the source area between the adjacent trenches be arc (bowl-type, thus bowl-shaped) sidewall of dielectric region 1920 does not expose.In a kind of embodiment, this can realize by implementing the anisotropic silicon etching.The advantage of Figure 17 B-2 modification has been to provide bigger source electrode surface region to contact with top conductor layer 1935, thereby has reduced the source electrode contact resistance.And, obtained compacter unit interval by form heavy this tagma intermittently along the source electrode band, obtained highdensity FET thus.
Figure 18 simplifies cross section, and it shows the technology of the ditch-grid FET of the highly compact that is used to obtain to have heavy this tagma of autoregistration and source area.In Figure 18, the gate trench that wherein has grid 2012 extends through p-well region 2004 and ends at n type drift region 2000.In a kind of embodiment, n type drift region 2000 is the epitaxial loayers that are formed at highly doped n type substrate (not shown) top.Each gate trench comprises the dielectric cap 2014 on the grid 2012.As shown in the figure, the table section between two grooves is recessed into, and makes silicon be recessed into the outer wall with inclination, and this outer wall is from extending to the bottom of mesa recess near the top of dielectric cap 2014.
Indicated as the solid arrow 2019 that extends perpendicular to the mesa recess basal surface, (for example, blanket formula BF2) is injected (blanket implant) and is formed by implementing dopant with 0 degree angle in highly doped p type heavy this tagma 2016.Under the situation that the heavy body of setting 0 degree angle injects, the relative inclined-plane of each trenched side-wall and mesa recess with its very approaching outer wall and the injection dopant type of meticulously selecting and inject variable (such as injecting energy), guaranteed to be injected into dopant and can not arrive the channel region that in well region 2004, extends along trenched side-wall.
Dotted arrow 2018 as two one-tenth angles is indicated, and the two-way of implementing n type dopant becomes the blanket formula at angle to inject, and forms source area 2020 with the sloped sidewall along each mesa recess.As shown in the figure, the last turning of groove has hindered source electrode and has injected the core that enters heavy this tagma.As can be seen, all do not use mask in heavy this tagma injection or double-current angled source injection process.In fact, mesa recess has formed the natural mask that can form heavy this tagma of autoregistration and source area.
Autoregistration weighs this tagma and source area has reduced unit interval significantly, and the result has produced highdensity cellular construction, and it helps to reduce transistorized conducting resistance then.And heavy this tagma of autoregistration helps to improve not clamper inductive switch (unclamped inductiveswitching, durability UIL) (ruggedness).And, reduce number of masks with self-aligned manner formation source area and heavy this tagma, thereby reduced manufacturing cost, simplify processing step simultaneously and improved the manufacturing productive rate.In addition, the benefit of the concrete profile (profile) in source area and heavy this tagma is: (i) the inclination outer wall of mesa recess provides big source electrode surface region, it helps to reduce the source electrode contact resistance, and (ii) heavy this tagma overlaps under the source area, and it helps to improve transistorized UIL durability.And as can be seen, technology shown in Figure 180 is suitable for dielectric technology of many thick ends, and himself is applicable to LOCOS (local oxidation of silicon) technology well.
Figure 18 A-18I, Figure 19 A-19H, Figure 20 A-20G, Figure 21 A-21H and Figure 22 A-22F show various processing steps, and wherein, technology shown in Figure 180 is used to form the various FET with autoregistration characteristic.Have described in Figure 18 and many other processing steps technology of being implemented or under the situation of reading present disclosure, be predictable to those skilled in the art in the modification of these disclosed those.
Figure 18 A-18I shows the viewgraph of cross-section of the different process step that is used to form the ditch-grid FET with autoregistration source electrode and heavy this tagma of another embodiment according to the present invention.In Figure 18 A, traditional silicon etching and LOCOS technology are used for (termination region) formation insulation-filling groove 2001 in the terminator.Pad oxide layer (not shown) and nitride layer (not shown) at first form on n type silicon area 2000.Use first mask to limit the part of waiting to remove silicon of silicon area 2000 in terminal region subsequently.Nitride layer, pad oxide and following silicon area are removed by first mask, to form groove 2001 in terminal region.Implement selective oxidation subsequently, to use insulating material 2002 filling grooves 2001.Though not shown, parent material can comprise on it and to form the highly doped n type substrate that (for example, being epitaxially formed) has n type district 2000.
In Figure 18 B, enforcement blanket formula trap injects and drives in, so that form p type well region 2004 on silicon area 2000.Replacedly, the impurity that is injected can drive in the last stages of technology.In Figure 18 C, implement second masks, to limit and etched trench 2006, this groove extends through well region 2004 and ends in the silicon area 2000.The bottom of groove 2006 is filled with insulating material, for example by deposition high-density plasma (HDP) oxide, and with the HDP oxide that after etching deposited, to form oxide of the thick end 2008.
In Figure 18 D, gate insulator 2010 forms along all surface district that comprises trenched side-wall.Deposit spathic silicon and mix (for example, in-situ doped) subsequently.Use the 3rd mask to limit and the etching polysilicon, in active area, to form concave grid 2012A, and to form and stop trench-gate (termination trench gate) 2012B and surperficial grid 2012C.In Figure 18 E, dielectric layer structurally forms.Then use the 4th mask to be limited with the part in source region and at the opening 2015 of terminator, herein, dielectric layer will be by dark etching.By the mask open etch dielectric layer, up to touching silicon.Thereby, at active area, being positioned at space directly over each grid 2012A and being left and being filled with dielectric substance 2014A, opening 2015 forms in the terminator simultaneously.As can be seen, the surface of the well region 2004A of well region 2004B and terminator is exposed in the active area.
In Figure 18 F, implement silicon etch steps so that in active area and the terminator institute exposed silicon surface district recessed.Substantially form among the well region 2004B of arc silicon face between the adjacent trenches of active area and in the well region 2004A of terminator.Then, implement the heavy body injection of 0 degree and (for example, BF2),, and in the well region 2004A of terminator, form heavy this tagma 2016A with heavy this tagma 2016B of formation p type in the well region 2004B of active area.Source area 2020 utilizes two-way to become the angle source electrode to inject shown in arrow 2018 subsequently and forms.Tilt to inject in (two-way is angled implant to, two-pass angled implant) at double fluid, n type impurity is to inject as lower angle, that is, the core 2016B in heavy this tagma of prevention, last turning of groove receives and injects.Source area 2020 thereby form immediately near the ditch trough, the core 2016B in heavy this tagma is intactly keeping as shown in the figure simultaneously.Because the cause of the angle that the aspect ratio of opening 2015 (Figure 18 E) and two-way source electrode inject stops well region 2004A and does not receive the source electrode injection.
In Figure 18 G, implement to inject activation step and drive in the dopant that will inject.Use the 5th mask to limit and etching isolation layer 2014C subsequently, to form grid contact openings 2019.In Figure 18 H, conductor layer (for example, comprising metal) structurally forms subsequently.Use the 6th mask to limit and the etched conductors layer, so that make source conductor 2021A and grid conductor 2021B insulation.In Figure 18 I, deposit passivation layer.Use the 7th mask to come the etching part passivation layer subsequently, thereby limit the source area and the gate regions that will form the wire-bonded contact.In the embodiment that does not need passivation layer, can omit corresponding mask and processing step.
As can be seen, in the process that forms heavy this tagma 2016B and source area 2020, do not use mask.Equally, weighing this tagma and source area is self aligned with slot wedge all.And heavy this tagma 2016B is stacked under the source area 2020, but does not extend in the channel region.Thereby obtained compact unit interval and rebound unusually (snapback, snapback) and the UIL durability.Little unit interval helps to obtain lower Rdson.Equally, because therefore source area 2020 has obtained bigger source electrode contact area, thereby has obtained lower source electrode contact resistance along the outside sweep surface formation of well region 2004B.In addition, the masks that the simple process step has used quantity to reduce is suitable for many oxides of the thick end (TBO) processing module, and himself is applicable to the LOCOS method that forms TBO well.
The cross section of Figure 18 A-18I only shows illustrative processes step and exemplary termination structure.This processing step can be optimized in every way so that further reduce number of masks and realize different termination structures, and it comprises processing step among following described Figure 19 A-19H, Figure 20 A-20G, Figure 21 A-21H and Figure 22 A-22F is illustrated those.
Figure 19 A-19H is the viewgraph of cross-section of processing step, wherein, forms fluted polysilicon and replaces surperficial polysilicon, compares with the processing step of Figure 18 A-18I, and this fluted polysilicon makes the quantity of mask reduce one.The processing step corresponding with Figure 19 A-19C be similar to Figure 18 A-18C pairing those, thereby will not lay down a definition.In Figure 19 D, form gate insulator 2110 and deposit spathic silicon and mixing subsequently.Polysilicon to deposition carries out blanket etching, so that kept concave grid 2112 in groove.Here, the gate mask among Figure 18 D of previous embodiment has been omitted.In Figure 19 E, implementation of class is similar to the processing step of the sequence of process steps among Figure 18 E, so that the space that is positioned at directly over each grid 2112 is filled dielectric substance 2114A, opening 2115 forms on termination p-trap 2014A in dielectric layer simultaneously.In Figure 19 F, implementation of class is like the processing step of sequence of process steps among Figure 18 F, to form autoregistration heavy this tagma 2116A and 2116B and autoregistration source area 2120.
In Figure 19 G, use grid contact mask (the 4th mask) and in dielectric layer away from left gate trench on limit and etching grid contact openings 2113 activation of then injecting dopant.Grid contact openings 2113 provides the electric channel that leads to fluted polysilicon gate (electrical), and described fluted polysilicon gate is along unshowned third dimension degree interconnection among Figure 19 G.In replaceable embodiment, allow to stop p-trap 2104A drift, saved thus stopping the needs of source conductor 2121A.
In Figure 19 H, deposited conductor layer (for example, comprising metal) then is masks (the 5), to limit source conductor part 2121A and to make source conductor part 2121A and grid conductor part 2121B insulation.As can be seen, five masks in the technology shown in Figure 19 A-19H, have only been used.The thin layer that is located immediately at gate conductor layer and source conductor layer below is optional barrier metal.
Figure 20 A-20G is the viewgraph of cross-section of another processing step, and this processing step is less with the mask that the technology shown in Figure 18 A-18I is compared use.The pairing processing step of Figure 20 A-20D is similar to the pairing processing step of Figure 18 A-18D, therefore will not lay down a definition.The pairing processing step of Figure 20 E is similar to the pairing processing step of Figure 18 E, and different is to use the 4th mask to form extra opening 2217 in stopping dielectric layer on surperficial polysilicon 2212C.The pairing processing step of Figure 20 F is similar to the pairing processing step of Figure 18 F.Yet, because the cause of opening 2217 (in Figure 20 E) on the surperficial polysilicon 2212C, the silicon etching that is used for the recessed table top that exposes also etching the expose portion of surperficial polysilicon 2212C, thereby produce opening 2218.The sidewall of surface polysilicon is then by contact openings 2218 exposure that becomes.According to the degree of depth of mesa recess in the active area and the thickness of surperficial polysilicon 2212C, mesa recess etching etching and pass surperficial polysilicon 2212C or stay the thin layer of polysilicon along the bottom of opening 2218 fully.In a kind of embodiment, form opening 2218, so that its aspect ratio makes two to become the source electrode injection 2218 surperficial polysilicon segment 2213A of arrival at angle and the sidewall of 2213B.This advantageously makes the gate conductor layer 2221B (Figure 20 G) of formation afterwards and the contact resistance between surperficial polysilicon segment 2213A and the 2213B minimize.
Except the processing step of Figure 20 G comprised activation to the injection region, the pairing processing step of Figure 20 G was similar to the pairing processing step of Figure 18 H.Equally, unlike Figure 18 H (the wherein end face of grid conductor 2021B contact polysilicon 2012C), the grid conductor 2221B among Figure 20 G is by the sidewall of opening 2218 contact surface polysilicons.If surperficial polysilicon 2212C does not have complete eating thrown (that is, its part is keeping along the bottom of opening 2218) after the recessed step of the silicon in Figure 20 F, grid conductor 2021B is with the surface region of the polysilicon that stays in the same contact openings 2218 so.
In Figure 20 G, the thin layer that is located immediately under source conductor layer and the gate conductor layer is optional barrier metal.The advantage of this embodiment is, be similar to the embodiment of Figure 19 A-19H, in the whole steps that forms the top side conductor, only use five masks, but also preserved surface region by saving the source conductor layer 2121A (Figure 19 H) that surrounds periphery gates conductor layer 2121B (Figure 19 H).
Figure 21 A-21H is the viewgraph of cross-section of different process step, and this processing step is used to form ditch-grid FET of the ditch-grid FET that is similar to the technology shown in Figure 18 A-18I and obtains, and difference is that Schottky diode and FET are integrated.The pairing processing step of Figure 21 A is similar to the pairing processing step of Figure 18 A, thereby will no longer explain.In Figure 21 B, use p-trap blocking mask (blocking mask) (second mask) injects and drives in p type impurity, to form well region 2304 in n type silicon area 2300.Replacedly, the impurity that is injected can be driven in the later phases of processing step and push away trap.(as shown) that p-trap blocking mask stops p type impurity to be injected into silicon area 2300 forms in the part 2303 of schottky region.
In Figure 21 C and Figure 21 D, implementation of class is similar to a collection of processing step of Figure 18 C and Figure 18 D, therefore will no longer describe.In Figure 21 E, implement and the similar processing step of Figure 18 E, but also implement contact mask (the 5th) and dielectric planarisation step, so that the part 2314D of insulating barrier is retained on the schottky region 2303, in after a while source electrode and heavy body implantation step (Figure 21 F) process, receive dopant to prevent this zone.The pairing processing step of Figure 21 F is similar to the pairing processing step of Figure 18 F, therefore will no longer describe.
In Figure 21 G, implement to inject activation step to drive in the dopant that is injected into.Use the 6th mask subsequently, to limit on the schottky region 2303 and etching insulation layer 2314D and formation grid contact openings 2319 on surperficial grid 2312C.The pairing processing step of Figure 21 H is pairing identical with Figure 18 H, difference is, with outside source electrode and heavy this tagma contact, source conductor 2321A also contacts with schottky region 2303, to form Schottky contacts with silicon area 2300, this silicon area for example uses titanium silicide as barrier metal.So just formed ditch-grid FET with integrated schottky diode.
Though Figure 21 A-21H shows the processing step integrated schottky diode that how to utilize shown in Figure 18 A-18I, can change Figure 19 A-19H, Figure 20 A-20G, Figure 21 A-21H, Figure 22 A-22F, Figure 23 A-23I and Figure 24 A-24I processing step shown in separately similarly with integrated schottky diode.
Figure 22 A-22F is the viewgraph of cross-section according to another processing step that is used to form ditch-grid FET of embodiment, and wherein, the number of masks in the whole forming process of top side source electrode and grid conductor is reduced to four.In Figure 22 A, the pad oxide layer (not shown) is formed on the n type silicon area 2400.The conductive dopant of p type is injected into and drives in (pushing away trap), to form p-well region 2404 in n type silicon area 2400.Replacedly, the impurity that is injected can be driven in the later phases of processing step.Use first mask to limit at active area and etched trench 2406 and at terminator qualification and the wide groove 2401 of etching.Subsequently, use LOCOS oxide of the thick end (TBO) technology along the layer that forms insulating material 2402 on the end face of silicon mesa (silicon mesa) between both bottoms of active groove 2406 and wide termination groove (termination trench) 2401 and the adjacent trenches.
The pairing processing step of Figure 22 C is similar to the pairing processing step of Figure 20 D, yet, in Figure 22 C, what form smooth surperficial polysilicon 2212C among replacement Figure 20 D is that polysilicon 2412C extends and drops in the wide groove 2401 on stopping p-trap 2204A.The pairing separately processing step of Figure 22 D, Figure 22 E and Figure 22 F is similar to Figure 20 E, Figure 20 F and the pairing separately processing step of Figure 20 G respectively, thereby will no longer describe.As can seeing in Figure 22 F, the sidewall of the grid 2412D in grid conductor 2421B and the wide groove in terminator contacts.As in Figure 20 A-20G embodiment, if after the recessed step of the silicon of Figure 22 E, stop polysilicon 2412C and do not have complete eating thrown (promptly, its part keeps along the bottom of the opening 2218 of polysilicon 2412C), grid conductor 2021B is also with the end face district of the residual polysilicon in the contact openings 2218 so.Used four masks altogether, it adds up to 5 masks with passivation pad mask (for example, as determined in the pairing processing step of Figure 18 I).
Figure 23 A-23I is the viewgraph of cross-section of the different process step that is used to form the ditch-grid FET with autoregistration feature of another embodiment according to the present invention.The pairing processing step of Figure 23 A-23D be similar to Figure 18 A-18D pairing those, therefore will no longer describe.In Figure 23 E, dielectric layer structurally forms.Subsequently, use the 4th mask to cover the terminator, this is because implement dielectric planarization etching so that dielectric cap 2514A is retained on each trench-gate 2512A in active area.In Figure 23 F, implement the mesa recess etching, so that under the end face of the recessed dielectric cap 2514A of p type well region 2504B, the exposure thereby the upper side wall of dielectric cap 2514A becomes.Implement the blanket formula of dopant (for example arsenic) subsequently and inject, to form n+ district 2517 among the well region 2504B between adjacent trenches.Subsequently, use the sidewall that exposes of conventional art 2517 upper edge dielectric cap 2514A to form nitride spacers 2518 in the n+ district.In Figure 23 G, make the silicon mesa that is exposed between the adjacent spaces body 2518 be recessed to the interior degree of depth of well region 2504B.Silicon is recessed has removed the mid portion (Figure 23 F) in n+ district 2517, has stayed the outside 2520 of extending under complete interval body 2518 in n+ district 2517.Part 2520 forms transistorized source area.Subsequently, inject the agent of p type doping impurity, to form heavy this tagma 2516.
In Figure 23 H, use conventional art to remove nitride spacers 2518.Subsequently, use the 5th mask in the terminator, in dielectric region 2514B, to produce opening 2515 and 2519.In Figure 23 I, source conductor and grid conductor form in the mode that is similar among Figure 18 I.Amount to like this and used six masks.This processing step is particularly suitable for forming the ditch grid FET with wide spacing body.And it is the formation in self aligned source area and heavy this tagma that this processing step advantageously produces for groove.
Figure 24 A-24I is the viewgraph of cross-section of the different process step that is used to form ditch-grid FET of another embodiment according to the present invention.The pairing processing step of Figure 24 A-24D be similar to Figure 19 A-19D pairing those, therefore will no longer describe.In Figure 24 E, dielectric layer forms structurally.Subsequently, use the 3rd mask to cover the terminator, this is because implement dielectric planarization etching in active area, so that form dielectric cap 2614A on each trench-gate 2612.Figure 24 F and the pairing processing step of Figure 24 G be similar to respectively Figure 23 F and Figure 23 G pairing those, therefore will no longer describe.
In Figure 24 H, use conventional art to remove nitride spacers 2618.In the terminator, use the 4th mask subsequently, in dielectric region 2614B (Figure 24 G), to produce opening 2615.In Figure 24 I, metal level structurally forms, and uses the 5th mask to limit source conductor 2621A and grid conductor 2621B.As shown in the figure, source conductor 2621A contacts with heavy this tagma 2616 and source area 2620 along its end face and sidewall.Stop well region 2604B electric drift.Replacedly, well region 2604B can be by electrically contacting and bias voltage of carrying out along the direction that enters paper.
The embodiment represented with Figure 23 A-23I is similar, and this embodiment is suitable for forming the ditch grid FET with wide spacing body, and this embodiment to have with respect to groove be self aligned source electrode and heavy this tagma.Yet advantageously, this embodiment need be lacked one mask than the needed mask of Figure 23 A-23I embodiment.
Though each processing step represented by Figure 18 A-18I, Figure 19 A-19H, Figure 20 A-20G, Figure 21 A-21H, Figure 22 A-22F, Figure 23 A-23I and Figure 24 A-24I is that background illustrates with the single gate groove structure, but under the situation of reading present disclosure, these processing steps are made amendment to comprise that the bucking electrode (being similar to the dhield grid 1324 among Figure 10) under the grid will be conspicuous to those skilled in the art.
Various structure of the present invention and method can with common one or more a large amount of electric charge diffusion technique combinations disclosed in the 11/026th, No. 276 that assign an application of top institute reference, to obtain lower conducting resistance, higher blocking ability and the efficient of Geng Gao.
The viewgraph of cross-section of different embodiments can be not to scale, and similarly and do not mean that the possible modification of restriction in the corresponding construction layout-design.And various transistors can or form in the closed cell structure (for example, hexagon or rectangular cells) in open cell structure (for example, band).
Though more than illustrate and described a large amount of concrete embodiments, the specific embodiment of the present invention is not limited thereto.For example, should be appreciated that in the case of without departing from the present invention that the doping polarity of the structure that has illustrated and described can be reverse, and/or the doping content of each key element (element) can change.As another example, above-mentioned various exemplary accumulation type and enhancement mode vertical transistor (vertical transistor) have the groove that ends at drift region (the low-doped epitaxial loayer that extends) on substrate, but they also can end at highly doped substrate.Equally, under the situation that does not deviate from scope of the present invention, the feature of one or more embodiments of the present invention can with one or more characteristics combination of other embodiment of the present invention.Because like this with such, therefore, more than describe should not be construed limiting the scope of the invention, scope of the present invention is limited by claims.
Claims (8)
1. method that forms field-effect transistor, described field-effect transistor have active area and around the terminator of described active area, described method comprises:
Form well region in first silicon area, described well region and described first silicon area are opposite conduction types;
Form gate trench, described gate trench extends through described well region and ends in described first silicon area;
In each gate trench, form concave grid;
On each concave grid, form dielectric cap;
Make the described well region between the adjacent trenches recessed, to expose the upper side wall of each dielectric cap;
Implement blanket formula source electrode and inject, to form second silicon area in the top of the female well region between per two adjacent trenches, described second silicon area is identical conduction type with first silicon area;
Upper side wall along each exposure of described dielectric cap forms dielectric spacers, and per two the adjacent dielectric interval bodies between per two neighboring gates grooves form opening on described second silicon area; And
Make described second silicon area recessed by the described opening between per two adjacent dielectric interval bodies, so that the part under described dielectric spacers of only described second silicon area remains, the described reserve part of described second silicon area forms source area.
2. method according to claim 1 further is included in formation top side conductor layer and removes described dielectric spacers before, so that described top side conductor layer contacts the end face of each source area.
3. method according to claim 1 further comprises:
Before forming the female formula grid, form dielectric of the thick end along the bottom of each gate trench; And
Before forming the female formula grid, form the gate-dielectric of the described sidewall lining of each gate trench, wherein, dielectric of the described thick end is thicker than described gate-dielectric.
4. method according to claim 1 further comprises:
Before forming the female formula grid, along the bottom formation bucking electrode of each gate trench; And
Before forming the female formula grid, on each bucking electrode, form dielectric layer.
5. method according to claim 1 further comprises:
In described terminator, form wide groove; And fill described wide groove with LOCOS.
6. method according to claim 1 further is included in when forming the female formula grid in the described gate trench, forms surperficial grid in described terminator.
7. method according to claim 6 further comprises:
On described surperficial grid, form opening; And formation contacts the grid conductor of described surperficial grid by described opening.
8. method according to claim 1 further comprises:
When forming described gate trench, in described terminator, form and stop groove;
In described gate trench, form in the female formula grid, in described termination groove, form concave grid;
Form opening on the female formula grid in described termination groove; And
Form grid conductor, described grid conductor contacts the female formula grid in the described termination groove by described opening.
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| CN2006800187740A Expired - Fee Related CN101185169B (en) | 2005-04-06 | 2006-04-04 | Trenched-gate field effect transistors and methods of forming the same |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8680611B2 (en) | 2005-04-06 | 2014-03-25 | Fairchild Semiconductor Corporation | Field effect transistor and schottky diode structures |
| CN103367360A (en) * | 2012-03-26 | 2013-10-23 | 株式会社东芝 | Semiconductor device |
| CN105977157A (en) * | 2016-07-25 | 2016-09-28 | 吉林华微电子股份有限公司 | IGBT device manufacturing method and device |
| CN106098561A (en) * | 2016-07-25 | 2016-11-09 | 吉林华微电子股份有限公司 | The manufacture method of a kind of MOSFET element and device thereof |
| CN106098752A (en) * | 2016-07-25 | 2016-11-09 | 吉林华微电子股份有限公司 | A kind of IGBT device and manufacture method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008536316A (en) | 2008-09-04 |
| CN101185169B (en) | 2010-08-18 |
| TW200644243A (en) | 2006-12-16 |
| US20140203355A1 (en) | 2014-07-24 |
| US20120156845A1 (en) | 2012-06-21 |
| KR20120127677A (en) | 2012-11-22 |
| US7504306B2 (en) | 2009-03-17 |
| KR101236030B1 (en) | 2013-02-21 |
| KR20070122504A (en) | 2007-12-31 |
| WO2006108011A2 (en) | 2006-10-12 |
| DE112006000832B4 (en) | 2018-09-27 |
| WO2006108011A3 (en) | 2007-04-05 |
| US20120319197A1 (en) | 2012-12-20 |
| CN102867825B (en) | 2016-04-06 |
| TWI434412B (en) | 2014-04-11 |
| AT504998A2 (en) | 2008-09-15 |
| US8680611B2 (en) | 2014-03-25 |
| HK1120160A1 (en) | 2009-03-20 |
| CN102867825A (en) | 2013-01-09 |
| US20090111227A1 (en) | 2009-04-30 |
| CN101185169A (en) | 2008-05-21 |
| US20060267090A1 (en) | 2006-11-30 |
| US8084327B2 (en) | 2011-12-27 |
| DE112006000832T5 (en) | 2008-02-14 |
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