CN101908547B - One time programmable memory and making, programming and reading method - Google Patents
One time programmable memory and making, programming and reading method Download PDFInfo
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- CN101908547B CN101908547B CN2009100865212A CN200910086521A CN101908547B CN 101908547 B CN101908547 B CN 101908547B CN 2009100865212 A CN2009100865212 A CN 2009100865212A CN 200910086521 A CN200910086521 A CN 200910086521A CN 101908547 B CN101908547 B CN 101908547B
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Abstract
The invention discloses a one time programmable memory with a double diode structure and making, programming and reading method. A one time programmable memory unit with the double diode structure comprises a first diode formed by a first doping area and an ion implantation area and a second diode formed by an ion implantation area and a well, wherein the first diode is connected in series with the second diode and is connected with a word line, the second diode is connected with a bit line, and reverse breakdown voltage of the first diode is different from reverse breakdown voltage of the second diode. By utilizing an on-resistance formed when the first diode is broken down, the closing characteristic when the first diode is not broken down and the characteristics of forward conduction and reverse closing of the second diode, the one time programmable memory has the advantages of small area of a storage unit, high integration level as well as high data storage stability and reliability, can further enhance the integration level along with development of a technology without adding a special technology based on the traditional logic technology.
Description
Technical field
The present invention relates generally to the semiconductor memory field, relates in particular to disposable programmable memory, manufacturing and programming read method.
Background technology
At present, DRAM structure is mainly adopted in the design of the disposable programmable memory of logic-based technology, but utilizes the breakdown characteristics of transistorized grid oxide layer to carry out data programing.Each unit of this disposable programmable memory all comprises two transistors, and one of them transistor is the thick grid oxide layer transistor that is used for input and output, because its grid oxide layer is thicker, therefore has higher withstand voltage properties; Another transistor is the thin grid oxide layer transistor that is used for the chip internal circuit, because its grid oxide layer is thinner, therefore is easy under lower voltage breakdown.Because thick grid oxide layer transistor possesses the gating characteristic, thin grid oxide layer transistor possesses can puncture capacitance characteristic, and therefore, the sort circuit structure is also referred to as and comprises a gate transistor and the circuit structure that can puncture electric capacity (1T1C).The disposable programmable memory of this structure; Because program voltage is higher; Need gate transistor to have higher withstand voltage properties,, make that the area of each memory cell is also bigger because the transistorized area of thick grid oxide layer is relatively large; Therefore, cause the increase of manufacturing cost and the reduction of integrated level.
Summary of the invention
In view of this; The object of the present invention is to provide a kind of disposable programmable memory, manufacturing and programming read method of double diode structure; Reaching provides that to have a memory cell area little, and integrated level is high, can further improve integrated level with the development of technology; Based on existing logic process, the disposable programmable memory that need not to increase special process, program voltage is adjustable, has high storage stability and reliability.
According to the one side of the embodiment of the invention, a kind of disposable programmable memory of double diode structure is provided, comprise the one-time programmable memory cell of a plurality of double diode structures, the one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms at said ion implanted region;
Said ion implanted region forms on said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode.
According to a characteristic of the embodiment of the invention,
Said programmable storage comprises:
Isolated groove is used for said trap is isolated; Wherein, the degree of depth of said isolated groove is greater than the degree of depth of said trap.
According to another characteristic of the embodiment of the invention,
The one-time programmable memory cell of said a plurality of double diode structures comprises the one-time programmable memory cell of the first double diode structure and the one-time programmable memory cell of the second double diode structure at least, wherein,
The one-time programmable memory cell of the one-time programmable memory cell of the said first double diode structure and the said second double diode structure keeps preset distance.
According to another characteristic of the embodiment of the invention,
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap.
According to another characteristic of the embodiment of the invention,
Said double diode structure comprises:
Type double diode structure or type double diode structure dorsad in opposite directions.
According to the embodiment of the invention on the other hand; A kind of manufacturing approach of disposable programmable memory of double diode structure is provided; The disposable programmable memory of said double diode structure comprises the one-time programmable memory cell of a plurality of double diode structures, and said manufacturing approach may further comprise the steps:
On substrate, form trap;
On said trap, form ion implanted region;
Form first doped region at said ion implanted region;
Said first doped region is different with the ion doping concentration of said trap;
Said first doped region and said ion implanted region are formed first diode;
Said ion implanted region and said trap are formed second diode;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode.
According to a characteristic of the embodiment of the invention,
The isolated groove that said ion implanted region is isolated in generation, wherein, the degree of depth of said isolated groove is greater than the degree of depth of said trap.
According to another characteristic of the embodiment of the invention,
The one-time programmable memory cell of said a plurality of double diode structures comprises the one-time programmable memory cell of the first double diode structure and the one-time programmable memory cell of the second double diode structure at least, wherein,
The one-time programmable memory cell of the said first double diode structure and the one-time programmable memory cell of the said second double diode structure are kept preset distance.
According to another characteristic of the embodiment of the invention,
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap.
According to another characteristic of the embodiment of the invention,
Said double diode structure comprises:
Type double diode structure or type double diode structure dorsad in opposite directions.
According to the embodiment of the invention on the other hand, a kind of programmed method of disposable programmable memory of double diode structure is provided, wherein,
The one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms at said ion implanted region;
Said ion implanted region forms on said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode;
Said programmed method comprises:
On said word line, apply first voltage; On said bit line, apply second voltage; The diode breakdown that reverse breakdown voltage is little in said first diode and second diode is formed conducting resistance, and make the big diode current flow of reverse breakdown voltage in said first diode and second diode.
According to a characteristic of the embodiment of the invention,
The difference of said first voltage and said second voltage is can be with the magnitude of voltage of the diode breakdown that reverse breakdown voltage is little in said first diode and second diode.
According to the embodiment of the invention on the other hand, a kind of read method of disposable programmable memory of double diode structure is provided, wherein,
The one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms at said ion implanted region;
Said ion implanted region forms on said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode;
Said read method comprises:
On said word line, apply tertiary voltage; Whether on said bit line, apply the 4th voltage, detecting sense amplifier has electric current, if; Then represent the breakdown formation resistance of diode that reverse breakdown voltage is little in said first diode and second diode, be output as logical one; Otherwise, represent that the diode that reverse breakdown voltage is little in said first diode and second diode is not breakdown, output logic " 0 ".
Disposable programmable memory of the present invention, manufacturing and programming read method, the beneficial effect that reaches is following:
1. break the traditional concept of the breakdown characteristics making disposable programmable memory that utilizes grid oxide layer in the prior art; Adopt the reverse breakdown characteristics of diode to make disposable programmable memory; Owing to adopt the double diode structure; Therefore, this one-time programmable memory cell is simple in structure, memory cell area is little, and integrated level is high;
2. because based on existing logic process manufacturing, so this one-time programmable memory cell can make integrated level further raising with the development of technology of this disposable programmable memory with technology characteristics size scaled down;
3. owing to need not to increase special process so this one-time programmable memory cell can be directly embedded in the SOC chip;
4, pass through to regulate the doping content of two diode PN junctions in the diode structure, thereby guarantee to have only a diode breakdown in the double diode structure, and then improved the reliability of one-off programming memory;
5,, therefore, can regulate puncture voltage through the doping content of regulating the diode PN junction, thereby be designed for the program voltage that memory cell is programmed neatly because the reverse breakdown voltage of diode is relevant with diode PN junction doping content;
6. effectively isolate ion implanted region owing to the transoid trap that adopts the alternative conventional bulk silicon technology of insulating barrier, and through insulating barrier and isolated groove, not only improve the stability and the reliability of storage, and further reduced memory cell area;
7, the present invention utilizes trap or the ion implanted region of the mutual isolation that insulating barrier and the isolated groove of SOI technology the form positive pole as diode; Therefore need not increase or change any processing step; Just can make the very little memory cell of area; And can avoid the inferior position on the common aspect silicon technology performance, like bolt-lock effect etc.
Description of drawings
Fig. 1 is the end view of the one-time programmable memory cell structure of double diode structure in the first embodiment of the invention;
Fig. 2 is the partial top view of the One Time Programmable storage array of double diode structure in the first embodiment of the invention;
Fig. 3 is the local domain of the One Time Programmable storage array of double diode structure in the first embodiment of the invention;
Fig. 4 is the end view of the one-time programmable memory cell structure of double diode structure in the second embodiment of the invention;
Fig. 5 is the partial top view of the One Time Programmable storage array of double diode structure in the second embodiment of the invention;
Fig. 6 is the local domain of the One Time Programmable storage array of double diode structure in the second embodiment of the invention;
Fig. 7 is the end view of the one-time programmable memory cell structure of double diode structure in the third embodiment of the invention;
Fig. 8 is the partial top view of the One Time Programmable storage array of double diode structure in the third embodiment of the invention;
Fig. 9 is the local domain of the One Time Programmable storage array of double diode structure in the third embodiment of the invention;
Figure 10 is the end view of the one-time programmable memory cell structure of double diode structure in the fourth embodiment of the invention;
Figure 11 is the partial top view of the One Time Programmable storage array of double diode structure in the fourth embodiment of the invention;
Figure 12 is the local domain of the One Time Programmable storage array of double diode structure in the fourth embodiment of the invention;
Figure 13 is the end view of the one-time programmable memory cell structure of double diode structure in the fifth embodiment of the invention;
Figure 14 is the partial top view of the One Time Programmable storage array of double diode structure in the fifth embodiment of the invention;
Figure 15 is the local domain of the One Time Programmable storage array of double diode structure in the fifth embodiment of the invention;
Figure 16 is the end view of the one-time programmable memory cell structure of double diode structure in the sixth embodiment of the invention;
Figure 17 is the end view of the one-time programmable memory cell structure of double diode structure in the seventh embodiment of the invention;
Figure 18 A for the present invention first, second and third, the equivalent circuit theory figure of the one-time programmable memory cell of double diode structure among six embodiment;
Figure 18 B for the present invention first, second and third, equivalent circuit theory figure after the one-time programmable memory cell programming of double diode structure punctures among six embodiment;
Figure 19 for the present invention first, second and third, the partial schematic diagram of the One Time Programmable storage array of double diode structure among six embodiment;
Figure 20 A is the circuit theory diagrams of the one-time programmable memory cell of double diode structure among the present invention fourth, fifth, seven embodiment;
Figure 20 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of double diode structure among the present invention fourth, fifth, seven embodiment punctures;
Figure 21 is the partial schematic diagram of the One Time Programmable storage array of double diode structure among the present invention fourth, fifth, seven embodiment.
Embodiment
Describe specific embodiment of the present invention in detail below in conjunction with accompanying drawing.
First embodiment
Fig. 1 is the end view of the one-time programmable memory cell structure of double diode structure in the first embodiment of the invention, comprises among Fig. 1: n type heavily doped region 101, n type light doping section 102, p type ion implanted region 103, isolated groove 104, n type trap 105 and p type substrate 106.Wherein,
N type heavily doped region 101, n type light doping section 102 are positioned at p type ion implanted region 103; P type ion implanted region 103 is positioned at n type trap 105; N type trap 105 is positioned on the p type substrate 106, and n type heavily doped region 101 is connected with word line (WL1, Word Line 1); N type light doping section 102 is connected with bit line (BL1, Bit Line 1).Wherein,
First diode 1801 that n type heavily doped region 101, p type ion implanted region 103 form shown in Figure 18 A, p type ion implanted region 103 and second diode 1802 of n type light doping section 102 formation shown in Figure 18 A.Because n type heavily doped region 101 is the negative pole of first diode 1801; N type light doping section 102 is the negative pole of second diode 1802; P type ion implanted region 103 is respectively as the positive pole of first diode 1801, second diode 1802; Therefore, the double diode structure in the present embodiment is called N-P-N type double diode structure dorsad again, and first diode 1801 and second diode 1802 are shared as anodal p type ion implanted region 103.Because the n type ion doping concentration of the negative pole of first diode 1801, second diode 1802 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; First reverse breakdown voltage of the PN junction that the n type heavily doped region 101 of first diode 1801 and p type ion implanted region 103 form is less than the n type light doping section 102 of second diode 1802 and second reverse breakdown voltage of the PN junction of p type ion implanted region 103 formation; That is to say that under identical voltage effect, first diode, 1801 to the second diodes 1802 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of n type half crastal tube structure in the first embodiment of the invention below, concrete steps are following:
Step 101S generates isolated groove according to mask pattern;
Step 102S forms the n trap on p type substrate;
Step 103S forms p type ion implanted region in the n trap;
Step 104S carries out heavy dose of n type ion and injects formation n type heavily doped region in the first area of p type ion implanted region;
Step 105S carries out low dose of n type ion and injects formation n type light doping section in the second area of p type ion implanted region;
Wherein, step 104S and step 105S can carry out simultaneously, also can first execution in step 105S, execution in step 104S again.
In the above-mentioned steps, n type heavily doped region, p type ion implanted region form first diode, and p type ion implanted region and n type light doping section form second diode.The degree of depth of isolated groove is less than the degree of depth of n trap and greater than the degree of depth of p type ion implanted region; Thereby the assurance isolated groove can be isolated p type ion implanted region well; Make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.
Fig. 2 is the partial top view of the One Time Programmable storage array of n type half crastal tube structure in the first embodiment of the invention; Among Fig. 2; Each one-time programmable memory cell comprises n type heavily doped region 101, n type light doping section 102, p type ion implanted region 103, isolated groove 104, n type trap 105; Wherein, isolated groove 104 surrounds p type ion implanted region 103.
Fig. 3 is the local domain of the One Time Programmable storage array of double diode structure in the first embodiment of the invention; Among Fig. 3, each one-time programmable memory cell comprises the metal level that forms word line WL1, word line WL2, metal level, n type heavily doped region 101, n type light doping section 102, p type ion implanted region 103, first contact hole 107 and second contact hole 108 that forms bit line BL1, bit line BL2.Wherein, the metal level of formation word line WL1 is connected with n type heavily doped region 101 through first contact hole 107; The metal level that forms bit line BL1 is connected with n type light doping section 102 through second contact hole 108; The metal level that forms word line WL1, word line WL2 is respectively two metal levels that are positioned at different layers with the metal level that forms bit line BL1, bit line BL2; For example, the metal level that forms word line is a first metal layer, and the metal level that forms bit line is second metal level; In addition; The metal level that forms word line is not limited in first and second metal level with the metal level that forms bit line, can certainly be other metal level, as long as belong to two different metal layers respectively.
Owing to the n type heavily doped region 101 among Fig. 3, the metal level that n type light doping section 102 is formed word line, bit line stop, therefore, the not shown n type of Fig. 3 heavily doped region 101, n type light doping section 102.
Second embodiment
Fig. 4 is the end view of the one-time programmable memory cell structure of double diode structure in the second embodiment of the invention, comprises first one-time programmable memory cell and second one-time programmable memory cell of the preset distance of being separated by among Fig. 4, wherein,
First one-time programmable memory cell comprises: n type heavily doped region 201, p type ion implanted region 202, n type trap 203 and p type substrate 204.
Wherein, n type heavily doped region 201 is positioned at p type ion implanted region 202, and p type ion implanted region 202 is positioned at n type trap 203, and n type trap 203 is positioned on the p type substrate 204.N type heavily doped region 201 is connected with word line, and n type trap 203 is connected with bit line.
Second one-time programmable memory cell comprises: n type heavily doped region 211, p type ion implanted region 212, n type trap 213 and p type substrate 204.
Wherein, n type heavily doped region 211 is positioned at p type ion implanted region 212, and p type ion implanted region 212 is positioned at n type trap 213, and n type trap 213 is positioned on the p type substrate 204.N type heavily doped region 211 is connected with word line, and n type trap 213 is connected with bit line.
First one-time programmable memory cell among Fig. 4 and second one-time programmable memory cell are independently one-time programmable memory cells of two of identical in structure; The influence that causes for the thermal diffusion effect that prevents n type trap is with first one-time programmable memory cell and second one-time programmable memory cell preset distance of being separated by.Describe in the face of the structure of first one-time programmable memory cell down.
In first one-time programmable memory cell, first diode 1801 that n type heavily doped region 201, p type ion implanted region 202 form shown in Figure 18 A, p type ion implanted region 202 and second diode 1802 of n type trap 203 formation shown in Figure 18 A.Because n type heavily doped region 201 is the negative pole of first diode 1801; N type trap 203 is the negative pole of second diode 1802; P type ion implanted region 202 is respectively as the positive pole of first diode 1801, second diode 1802; Therefore, the double diode structure in the present embodiment is also referred to as N-P-N type double diode structure dorsad, and first diode 1801 and second diode 1802 are shared as anodal p type ion implanted region 202.Because the n type ion doping concentration of the negative pole of first diode 1801, second diode 1802 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; The n type heavily doped region 101 of first diode 1801 is less than the n type trap 203 of second diode 1802 and second reverse breakdown voltage of the PN junction of p type ion implanted region 202 formation with first reverse breakdown voltage of the PN junction that p type ion implanted region 103 forms; That is to say that first diode, 1801 to the second diodes 1802 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of n type half crastal tube structure in the second embodiment of the invention below, concrete steps are following:
Step 201S forms the n trap on p type substrate;
Step 202S forms p type ion implanted region in the n trap;
Step 203S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region.
In the above-mentioned steps, n type heavily doped region, p type ion implanted region form first diode, and p type ion implanted region and n trap form second diode.
Fig. 5 is the partial top view of the One Time Programmable storage array of double diode structure in the second embodiment of the invention; Among Fig. 5; First one-time programmable memory cell comprises n type heavily doped region 201, p type ion implanted region 202, n type trap 203; Second one-time programmable memory cell comprises n type heavily doped region 211, p type ion implanted region 212, n type trap 213, the first one-time programmable memory cells and second one-time programmable memory cell preset distance of being separated by.
Fig. 6 is the local domain of the One Time Programmable storage array of double diode structure in the second embodiment of the invention; Among Fig. 6, one-time programmable memory cell comprises the metal level that forms word line WL1, word line WL2, metal level, n type heavily doped region 201, p type ion implanted region 202, n type trap 203, first contact hole 205 and second contact hole 206 that forms bit line BL1, bit line BL2.Wherein, the metal level of formation word line WL1 is connected with n type heavily doped region 201 through first contact hole 205; The metal level that forms bit line BL1 is connected with n type trap 203 through second contact hole 206; The metal level that forms word line WL1, word line WL2 is respectively two metal levels that are positioned at different layers with the metal level that forms bit line BL1, bit line BL2; For example, the metal level that forms word line is a first metal layer, and the metal level that forms bit line is second metal level; In addition; The metal level that forms word line is not limited in first and second metal level with the metal level that forms bit line, can certainly be other metal level, as long as belong to two different metal layers respectively.
Because the metal level that the n type heavily doped region 201 among Fig. 6 is formed word line, bit line stops, therefore, the not shown n type of Fig. 6 heavily doped region 201.
The 3rd embodiment
Fig. 7 is the end view of the one-time programmable memory cell structure of double diode structure in the third embodiment of the invention; Comprise among Fig. 7 by dark isolated groove (dSTI; Deeper STI) first one-time programmable memory cell and second one-time programmable memory cell of 304 isolation, wherein
First one-time programmable memory cell comprises: n type heavily doped region 301, p type ion implanted region 302, n type trap 303 and p type substrate 305.
Wherein, n type heavily doped region 301 is positioned at p type ion implanted region 302, and p type ion implanted region 302 is positioned at n type trap 303, and n type trap 303 is positioned on the p type substrate 305.N type heavily doped region 301 is connected with word line WL1, and n type trap 303 is connected with bit line BL1.
Second one-time programmable memory cell comprises: n type heavily doped region 311, p type ion implanted region 312, n type trap 313 and p type substrate 305.
Wherein, n type heavily doped region 311 is positioned at p type ion implanted region 312, and p type ion implanted region 312 is positioned at n type trap 313, and n type trap 313 is positioned on the p type substrate 305.N type heavily doped region 311 is connected with word line (WL, Word Line).
First one-time programmable memory cell among Fig. 7 and second one-time programmable memory cell are independently one-time programmable memory cells of two of identical in structure; The influence that causes for the thermal diffusion effect that prevents n type trap; The employing dark isolated groove darker than isolated groove in the prior art isolated first one-time programmable memory cell and second one-time programmable memory cell; Thereby the spacing between the programmable memory cell is dwindled, reduce the area of memory greatly.Describe in the face of the structure of first one-time programmable memory cell down.
In first one-time programmable memory cell, first diode 1801 that n type heavily doped region 301, p type ion implanted region 302 form shown in Figure 18 A, p type ion implanted region 302 and second diode 1802 of n type trap 303 formation shown in Figure 18 A.Because n type heavily doped region 301 is the negative pole of first diode 1801; N type trap 303 is the negative pole of second diode 1802; P type ion implanted region 302 is respectively as the positive pole of first diode 1801, second diode 1802; Therefore, the double diode structure in the present embodiment is also referred to as N-P-N type double diode structure dorsad, and first diode 1801 and second diode 1802 are shared as anodal p type ion implanted region 302.Because the n type ion doping concentration of the negative pole of first diode 1801, second diode 1802 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; The n type heavily doped region 101 of first diode 1801 is less than the n type trap 303 of second diode 1802 and second reverse breakdown voltage of the PN junction of p type ion implanted region 302 formation with first reverse breakdown voltage of the PN junction that p type ion implanted region 302 forms; That is to say that first diode, 1801 to the second diodes 1802 are breakdown more easily.
Dark isolated groove 304 is used for p type ion implanted region 303 and p type ion implanted region 313 are isolated, and the degree of depth of dark isolated groove 304 is greater than the degree of depth of p type ion implanted region 303,313 but less than the degree of depth of n type trap 305.
Introduce the manufacturing approach of the one-time programmable memory cell of n type half crastal tube structure in the third embodiment of the invention below, concrete steps are following:
Step 301S generates dark isolated groove according to mask pattern;
Step 302S forms the n trap on p type substrate;
Step 303S forms p type ion implanted region in the n trap;
Step 303S carries out heavy dose of n type ion and injects formation n type heavily doped region in p type ion implanted region.
In the above-mentioned steps, n type heavily doped region, p type ion implanted region form first diode, and p type ion implanted region and n trap form second diode.The degree of depth of dark isolated groove is less than the degree of depth of n trap and greater than the degree of depth of p type ion implanted region; Thereby guarantee that dark isolated groove can isolate p type ion implanted region well; Make that the spacing between each one-time programmable memory cell is very little, thereby reduce the area that the One Time Programmable storage array takies.
Fig. 8 is the partial top view of the One Time Programmable storage array of double diode structure in the third embodiment of the invention; Among Fig. 8; First one-time programmable memory cell comprises n type heavily doped region 301, p type ion implanted region 302, n type trap 303; Second one-time programmable memory cell comprises n type heavily doped region 311, p type ion implanted region 312, n type trap 313, and dark isolated groove 304 is isolated first one-time programmable memory cell, second one-time programmable memory cell.
Fig. 9 is the local domain of the One Time Programmable storage array of double diode structure in the third embodiment of the invention; Among Fig. 9, one-time programmable memory cell comprises the metal level that forms word line WL1, word line WL2, metal level, n type heavily doped region 301, p type ion implanted region 302, n type trap 303 and the contact hole 306 that forms bit line BL1, bit line BL2.Wherein, the metal level of formation word line WL1 is connected with n type heavily doped region 301 through contact hole 306; The metal level that forms bit line BL1 is connected with n type trap 303 through contact hole 306; The metal level that forms word line WL1, word line WL2 is respectively two metal levels that are positioned at different layers with the metal level that forms bit line BL1, bit line BL2; For example, the metal level that forms word line is a first metal layer, and the metal level that forms bit line is second metal level; In addition; The metal level that forms word line is not limited in first and second metal level with the metal level that forms bit line, can certainly be other metal level, as long as belong to two different metal layers respectively.
Because the metal level that the n type heavily doped region 301 among Fig. 9 is formed word line, bit line stops, therefore, the not shown n type of Fig. 9 heavily doped region 301.
The 4th embodiment
Figure 10 is the end view of the one-time programmable memory cell structure of double diode structure in the fourth embodiment of the invention, comprises first one-time programmable memory cell and second one-time programmable memory cell of the preset distance of being separated by among Figure 10, wherein,
First one-time programmable memory cell comprises: p type light doping section 401, p type heavily doped region 402, n type trap 403 and p type substrate 404.
Wherein, p type light doping section 401, p type heavily doped region 402 are positioned at n type trap 403, and n type trap 403 is positioned on the p type substrate 404.P type light doping section 401 is connected with word line WL1, and p type heavily doped region 402 is connected with bit line BL1.
Second one-time programmable memory cell comprises: p type light doping section 411, p type heavily doped region 412, n type trap 413 and p type substrate 404.
Wherein, p type light doping section 411, p type heavily doped region 412 are positioned at n type trap 413, and n type trap 413 is positioned on the p type substrate 404.P type light doping section 411 is connected with word line WL1.
First one-time programmable memory cell among Figure 10 and second one-time programmable memory cell are independently one-time programmable memory cells of two of identical in structure; The influence that causes for the thermal diffusion effect that prevents n type trap is with first one-time programmable memory cell and second one-time programmable memory cell preset distance of being separated by.Describe in the face of the structure of first one-time programmable memory cell down.
In first one-time programmable memory cell, first diode 2001 that p type light doping section 401, n type trap 403 form shown in Figure 20 A, p type heavily doped region 402 and second diode 2002 of n type trap 403 formation shown in Figure 20 A.Because p type light doping section 401 is the positive pole of first diode 2001; P type heavily doped region 402 is the positive pole of second diode 2002; N type trap 403 is respectively as the negative pole of first diode 2001, second diode 2002; Therefore, the double diode structure in the present embodiment is also referred to as P-N-P type double diode structure in opposite directions, first diode 2001 and second diode, 2002 shared n type traps 403 as negative pole.Because the p type ion doping concentration of the positive pole of first diode 2001, second diode 2002 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; The n type trap 403 of second diode 2002 is less than the p type light doping section 401 of first diode 2001 and first reverse breakdown voltage of the PN junction of n type trap 403 formation with second reverse breakdown voltage of the PN junction that p type heavily doped region 402 forms; That is to say that second diode, 2002 to the first diodes 2002 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of n type half crastal tube structure in the fourth embodiment of the invention below, concrete steps are following:
Step 401S forms the n trap on p type substrate;
Step 402S carries out heavy dose of n type ion and injects formation p type light doping section in the first area of n trap;
Step 403S carries out low dose of n type ion and injects formation p type heavily doped region in the second area of n trap;
Wherein, step 402S and step 403S can carry out simultaneously, also can first execution in step 403S, execution in step 402S again.
In the above-mentioned steps, p type light doping section and n trap form first diode, and p type heavily doped region and n trap form second diode.
Figure 11 is the partial top view of the One Time Programmable storage array of double diode structure in the fourth embodiment of the invention; Among Fig. 5; First one-time programmable memory cell comprises p type light doping section 401, p type heavily doped region 402 and n type trap 403; Second one-time programmable memory cell comprises p type light doping section 411, p type heavily doped region 412, n type trap 413, the first one-time programmable memory cells and second one-time programmable memory cell preset distance of being separated by.
Figure 12 is the local domain of the One Time Programmable storage array of double diode structure in the fourth embodiment of the invention; Among Figure 12, one-time programmable memory cell comprises the metal level that forms word line WL1, word line WL2, metal level, p type light doping section 401, p type heavily doped region 402, n type trap 403 and the contact hole 405 that forms bit line BL1, bit line BL2.Wherein, the metal level of formation word line WL1 is connected with p type light doping section 401 through contact hole 405; The metal level that forms bit line BL1 is connected with p type heavily doped region 402 through contact hole 405; The metal level that forms word line WL1, word line WL2 is respectively two metal levels that are positioned at different layers with the metal level that forms bit line BL1, bit line BL2; For example, the metal level that forms word line is a first metal layer, and the metal level that forms bit line is second metal level; In addition; The metal level that forms word line is not limited in first and second metal level with the metal level that forms bit line, can certainly be other metal level, as long as belong to two different metal layers respectively.
Owing to the p type light doping section 401 among Figure 12, the metal level that p type heavily doped region 402 is formed word line, bit line stop, therefore, the not shown p type of Figure 12 light doping section 401, p type heavily doped region 402.
The 5th embodiment
Figure 13 is the end view of the one-time programmable memory cell structure of double diode structure in the fifth embodiment of the invention, comprises first one-time programmable memory cell and second one-time programmable memory cell of being isolated by dark isolated groove 504 among Figure 13, wherein,
First one-time programmable memory cell comprises: p type light doping section 501, p type heavily doped region 502, n type trap 503 and p type substrate 505.
Wherein, p type light doping section 501, p type heavily doped region 502 are positioned at n type trap 503, and n type trap 503 is positioned on the p type substrate 505.P type light doping section 501 is connected with word line WL1, and p type heavily doped region 502 is connected with bit line BL1.
Second one-time programmable memory cell comprises: p type light doping section 511, p type heavily doped region 512 (figure does not show), n type trap 513 and p type substrate 505.
Wherein, p type light doping section 511, p type heavily doped region 512 are positioned at n type trap 513, and n type trap 513 is positioned on the p type substrate 505.P type light doping section 511 is connected with word line WL1.
First one-time programmable memory cell among Figure 13 and second one-time programmable memory cell are independently one-time programmable memory cells of two of identical in structure; For the influence that the thermal diffusion effect that prevents n type trap causes, adopt dark isolated groove that first one-time programmable memory cell and second one-time programmable memory cell are isolated.The degree of depth of dark isolated groove is greater than the degree of depth of n trap, thereby guarantees that dark isolated groove can isolate the n trap well, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.Describe in the face of the structure of first one-time programmable memory cell down.
In first one-time programmable memory cell, first diode 2001 that p type light doping section 501, n type trap 503 form shown in Figure 20 A, p type heavily doped region 502 and second diode 2002 of n type trap 503 formation shown in Figure 20 A.Because p type light doping section 501 is the positive pole of first diode 2001; P type heavily doped region 502 is the positive pole of second diode 2002; N type trap 503 is respectively as the negative pole of first diode 2001, second diode 2002; Therefore, the double diode structure in the present embodiment is also referred to as P-N-P type double diode structure in opposite directions, first diode 2001 and second diode, 2002 shared n type traps 503 as negative pole.Because the p type ion doping concentration of the positive pole of first diode 2001, second diode 2002 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; The n type trap 503 of second diode 2002 is less than the p type light doping section 501 of first diode 2001 and first reverse breakdown voltage of the PN junction of n type trap 503 formation with second reverse breakdown voltage of the PN junction that p type heavily doped region 502 forms; That is to say that second diode, 2002 to the first diodes 2002 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of n type half crastal tube structure in the fifth embodiment of the invention below, concrete steps are following:
Step 501S generates dark isolated groove according to mask pattern;
Step 502S forms the n trap on p type substrate;
Step 503S carries out heavy dose of n type ion and injects formation p type light doping section in the first area of n trap;
Step 504S carries out low dose of n type ion and injects formation p type heavily doped region in the second area of n trap;
Wherein, step 503S and step 504S can carry out simultaneously, also can first execution in step 504S, execution in step 503S again.
In the above-mentioned steps, p type light doping section and n trap form first diode, and p type heavily doped region and n trap form second diode.
Figure 14 is the partial top view of the One Time Programmable storage array of double diode structure in the fifth embodiment of the invention; Among Figure 14; First one-time programmable memory cell comprises p type light doping section 501, p type heavily doped region 502 and n type trap 503; Second one-time programmable memory cell comprises p type light doping section 511, p type heavily doped region 512, n type trap 513, and dark isolated groove 504 is isolated first one-time programmable memory cell, second one-time programmable memory cell.
Figure 15 is the local domain of the One Time Programmable storage array of double diode structure in the fifth embodiment of the invention; Among Figure 15, one-time programmable memory cell comprises the metal level that forms word line WL1, word line WL2, metal level, p type light doping section 501, p type heavily doped region 502, n type trap 503 and the contact hole 506 that forms bit line BL1, bit line BL2.Wherein, the metal level of formation word line WL1 is connected with p type light doping section 501 through contact hole 506; The metal level that forms bit line BL1 is connected with p type heavily doped region 502 through contact hole 506; The metal level that forms word line WL1, word line WL2 is respectively two metal levels that are positioned at different layers with the metal level that forms bit line BL1, bit line BL2; For example, the metal level that forms word line is a first metal layer, and the metal level that forms bit line is second metal level; In addition; The metal level that forms word line is not limited in first and second metal level with the metal level that forms bit line, can certainly be other metal level, as long as belong to two different metal layers respectively.
Owing to the p type light doping section 501 among Figure 15, the metal level that p type heavily doped region 502 is formed word line, bit line stop, therefore, the not shown p type of Figure 15 light doping section 501, p type heavily doped region 502.
The 6th embodiment
Figure 16 is the end view of the one-time programmable memory cell structure of double diode structure in the sixth embodiment of the invention, comprises among Figure 16: n type heavily doped region 601, n type light doping section 602, p type ion implanted region 603, isolated groove 604, insulating barrier 605 and p type substrate 606.Wherein,
N type heavily doped region 601, n type light doping section 602 are positioned at p type ion implanted region 603; P type ion implanted region 103 is positioned on the insulating barrier 605; Insulating barrier 605 is positioned on the p type substrate 606, and n type heavily doped region 101 is connected with word line WL1, and n type light doping section 102 is connected with bit line BL1.Wherein,
First diode 1801 that n type heavily doped region 601, p type ion implanted region 603 form shown in Figure 18 A, n type light doping section 602 and second diode 1802 of p type ion implanted region 603 formation shown in Figure 18 A.Because n type heavily doped region 601 is the negative pole of first diode 1801; N type light doping section 602 is the negative pole of second diode 1802; P type ion implanted region 603 is respectively as the positive pole of first diode 1801, second diode 1802; Therefore, the double diode structure in the present embodiment is called N-P-N type double diode structure dorsad again, and first diode 1801 and second diode 1802 are shared as anodal p type ion implanted region 603.Because the n type ion doping concentration of the negative pole of first diode 1801, second diode 1802 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore; The n type heavily doped region 601 of first diode 1801 is less than the n type light doping section 602 of second diode 1802 and second reverse breakdown voltage of the PN junction of p type ion implanted region 603 formation with first reverse breakdown voltage of the PN junction that p type ion implanted region 603 forms; That is to say that first diode, 1801 to the second diodes 1802 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of double diode structure in the sixth embodiment of the invention below, concrete steps are following:
Step 601S generates isolated groove according to mask pattern;
Step 602S forms p type ion implanted region on insulating barrier;
Step 603S carries out heavy dose of n type ion and injects formation n type heavily doped region in the first area of p type ion implanted region;
Step 604S carries out low dose of n type ion and injects formation n type light doping section in the second area of p type ion implanted region;
Wherein, step 603S and step 604S can carry out simultaneously, also can first execution in step 604S, execution in step 603S again.
In the above-mentioned steps, n type heavily doped region, p type ion implanted region form first diode, and p type ion implanted region and n type light doping section form second diode.Isolated groove can be isolated p type ion implanted region well, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.
The 7th embodiment
Figure 17 is the end view of the one-time programmable memory cell structure of double diode structure in the seventh embodiment of the invention, comprises among Figure 17: p type light doping section 701, p type heavily doped region 702, n type ion implanted region 703, isolated groove 704, insulating barrier 705 and p type substrate 706.Wherein,
P type light doping section 701, p type heavily doped region 702 are positioned at n type ion implanted region 703; N type ion implanted region 703 is positioned on the insulating barrier 705; Insulating barrier 705 is positioned on the n type substrate 706, and p type light doping section 101 is connected with word line WL1, and p type heavily doped region 102 is connected with bit line BL1.Wherein,
First diode 2001 that p type light doping section 701, n type ion implanted region 703 form shown in Figure 20 A, n type ion implanted region 703 and second diode 2002 of p type heavily doped region 702 formation shown in Figure 20 A.Because the p type ion doping concentration of the positive pole of first diode 2001, second diode 2002 is different; Diode for ion doping concentration is high more will be breakdown more easily; Therefore, p type light doping section 701 is the positive pole of first diode 2001, and p type heavily doped region 702 is the positive pole of second diode 2002; N type ion implanted region 703 is respectively as the negative pole of first diode 2001, second diode 2002; Therefore, the double diode structure in the present embodiment is called P-N-P type double diode structure in opposite directions again, and first diode 2001 and second diode 2002 are shared as anodal p type ion implanted region 703.Because the n type heavily doped region 702 of second diode 2002 is less than the n type light doping section 701 of first diode 2001 and second reverse breakdown voltage of the PN junction of p type ion implanted region 703 formation with first reverse breakdown voltage of the PN junction that p type ion implanted region 703 forms; Therefore, second diode, 2002 to the first diodes 2001 are breakdown more easily.
Introduce the manufacturing approach of the one-time programmable memory cell of double diode structure in the seventh embodiment of the invention below, concrete steps are following:
Step 701S generates isolated groove according to mask pattern;
Step 702S forms n type ion implanted region on insulating barrier;
Step 703S carries out heavy dose of p type ion and injects formation p type light doping section in the first area of n type ion implanted region;
Step 704S carries out low dose of p type ion and injects formation p type heavily doped region in the second area of n type ion implanted region;
Wherein, step 703S and step 704S can carry out simultaneously, also can first execution in step 704S, execution in step 703S again.
In the above-mentioned steps, p type light doping section, n type ion implanted region form first diode, and n type ion implanted region and p type heavily doped region form second diode.Isolated groove can be isolated n type ion implanted region well, makes that the spacing between each one-time programmable memory cell is very little, thereby reduces the area that the One Time Programmable storage array takies.
Following table 1 is the programming and the read method of the one-time programmable memory cell of double diode structure in the embodiment of the invention:
| ? | ? | V WL | V BL | Whether programme |
| Programming | Select WL/ to select BL | V pp | 0V | Be |
| ? | Select WL/ not select BL | V pp | V ppOr high resistant | Not |
| ? | Do not select WL/ to select BL | 0V | 0V | Not |
| ? | Do not select WL/ not select BL | 0V | V ppOr high resistant | Not |
| ? | ? | ? | ? | Whether detect the sense amplifier electric current |
| Read | Select WL/ to select BL | V read | 0V | Be |
| ? | Select WL/ not select BL | V read | V dd | Not |
| ? | Do not select WL/ to select BL | 0V | 0V | Not |
| ? | Do not select WL/ not select BL | 0V | V dd | Not |
Table 1
In the table 1, puncture voltage V
PpAt least greater than 2 times of operating voltage V
Dd, and less than the puncture voltage of the less diode of reverse breakdown voltage in first diode and second diode; Read voltage V
Read≤operating voltage V
Dd
Programming process:
On word line WL, apply puncture voltage V
Pp, on bit line BL, apply 0V voltage, thereby with the less diode breakdown of reverse breakdown voltage in first diode and second diode, and make the bigger diode forward conducting of reverse breakdown voltage in first diode and second diode.For unchecked programmable memory cell, on bit line BL, apply puncture voltage Vpp, in case other programmable memory cell that first diode of stop bit on the word line of having chosen punctured leaks electricity.
Under the logic process of 0.13um, puncture voltage V
PpSelectable magnitude of voltage such as 6-10V, operating voltage V
DdSelectable magnitude of voltage such as 1.3V read voltage V
ReadSelectable magnitude of voltage such as 1V.Certainly, according to different logical technology, puncture voltage V
Pp, operating voltage V
Dd, read voltage V
ReadAlso can change to some extent.
Read process:
With word line WL on apply and read voltage V
ReadWhether on bit line BL, apply 0V voltage, promptly on n type light doping section, apply 0V voltage, detecting sense amplifier has electric current; If; Then represent the less breakdown formation resistance of diode of reverse breakdown voltage in first diode and second diode, the bigger diode forward conducting of reverse breakdown voltage then is output as logical one in first diode and second diode; Otherwise, represent that the less diode of reverse breakdown voltage in first diode and second diode is not breakdown, output logic " 0 ".
Figure 18 A for the present invention first, second and third, the equivalent circuit theory figure of the one-time programmable memory cell of double diode structure among six embodiment; Comprise first diode 1801 and second diode 1802 that are connected in series among Figure 18 A, wherein, first diode 1801 is connected with bit line WL, and second diode 1802 is connected with word line BL.
Figure 18 B for the present invention first, second and third, equivalent circuit theory figure after the one-time programmable memory cell programming of double diode structure punctures among six embodiment; Comprise the resistance 1803 and second diode 1802 that are connected in series among Figure 18 B, wherein, after breakdown under first effect of diode 1801 among Figure 18 A, form resistance 1803 at program voltage.The direction of electric current I along word line WL to bit line BL flows.
Figure 19 for the present invention first, second and third, the partial schematic diagram of the One Time Programmable storage array of double diode structure among six embodiment; The one-time programmable memory cell, word line WL1, word line WL2, word line WL3, bit line BL1, bit line BL2, the bit line BL3 that comprise a plurality of double diode structures among Figure 19, each one-time programmable memory cell are connected with a word line, a bit lines respectively.The one-time programmable memory cell that connects word line WL2, bit line BL2 respectively that is positioned at Figure 19 central authorities has been programmed puncture, therefore, representes this one-time programmable memory cell with the equivalent electric circuit of resistance 1903 series diodes 1902 among the figure.
Figure 20 A is the circuit theory diagrams of the one-time programmable memory cell of double diode structure among the present invention fourth, fifth, seven embodiment; Comprise first diode 2001 and second diode 2002 that are connected in series among Figure 20 A, wherein, first diode 2001 is connected with bit line WL, and second diode 2002 is connected with word line BL.
Figure 20 B is the equivalent circuit theory figure after the one-time programmable memory cell programming of double diode structure among the present invention fourth, fifth, seven embodiment punctures; Comprise the resistance 2003 and first diode 2001 that are connected in series among Figure 20 B, wherein, after breakdown under second effect of diode 2002 among Figure 20 A, form resistance 1803 at program voltage.The direction of electric current I along word line WL to bit line BL flows.
Figure 21 is the partial schematic diagram of the One Time Programmable storage array of double diode structure among the present invention fourth, fifth, seven embodiment; The one-time programmable memory cell, word line WL1, word line WL2, word line WL3, bit line BL1, bit line BL2, the bit line BL3 that comprise a plurality of double diode structures among Figure 21, each one-time programmable memory cell are connected with a word line, a bit lines respectively.The one-time programmable memory cell that connects word line WL2, bit line BL2 respectively that is positioned at Figure 21 central authorities has been programmed puncture, therefore, representes this one-time programmable memory cell with the equivalent electric circuit of diode 2101 series resistances 2103 among the figure.
Disposable programmable memory of the present invention, manufacturing and programming read method, owing to adopt the double diode structure, therefore, this one-time programmable memory cell is simple in structure, memory cell area is little, integrated level is high.
In addition, because based on existing logic process manufacturing, so this one-time programmable memory cell can make the integrated level of this disposable programmable memory further improve with the development of technology with technology characteristics size scaled down.
In addition, owing to need not to increase special process so this one-time programmable memory cell can be directly embedded in the SOC chip.
In addition, through the doping content of two diode PN junctions in the adjusting diode structure, thereby guarantee to have only a diode breakdown in the double diode structure, and then improved the reliability of one-off programming memory.
In addition, because the reverse breakdown voltage of diode is relevant with diode PN junction doping content, therefore, can regulates puncture voltage through the doping content of regulating the diode PN junction, thereby be designed for the program voltage that memory cell is programmed neatly.
In addition, owing to adopt the transoid trap of the alternative conventional bulk silicon technology of insulating barrier, and effectively isolate ion implanted region through insulating barrier and isolated groove, not only improve the stability and the reliability of storage, and further reduced memory cell area.
In addition; The present invention utilizes the positive pole of the trap of the insulating barrier of SOI technology and the mutual isolation that isolated groove forms as diode; Therefore need not increase or change any processing step; Just can make the very little memory cell of area, and can avoid the inferior position on the common aspect silicon technology performance, like bolt-lock effect etc.
The above is merely preferred embodiment of the present invention; Not in order to restriction the present invention; All within spirit of the present invention and principle, any modification, the change that the embodiment of the invention is done, make up, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the disposable programmable memory of a double diode structure is characterized in that, comprises the one-time programmable memory cell of a plurality of double diode structures, and the one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms in said ion implanted region;
Said ion implanted region forms in said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode; Wherein,
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap.
2. disposable programmable memory according to claim 1 is characterized in that, said programmable storage comprises:
Isolated groove is used for the said trap of different said memory cells is isolated; Wherein, the degree of depth of said isolated groove is greater than the degree of depth of said trap.
3. disposable programmable memory according to claim 1 is characterized in that,
The one-time programmable memory cell of said a plurality of double diode structures comprises the one-time programmable memory cell of the first double diode structure and the one-time programmable memory cell of the second double diode structure at least, wherein,
The one-time programmable memory cell of the one-time programmable memory cell of the said first double diode structure and the said second double diode structure keeps preset distance.
4. disposable programmable memory according to claim 1 is characterized in that,
Said double diode structure comprises:
Type double diode structure or type double diode structure dorsad in opposite directions.
5. the manufacturing approach of the disposable programmable memory of a double diode structure; It is characterized in that; The disposable programmable memory of said double diode structure comprises the one-time programmable memory cell of a plurality of double diode structures, and said manufacturing approach may further comprise the steps:
On substrate, form trap;
In said trap, form ion implanted region;
In said ion implanted region, form first doped region;
Said first doped region is different with the ion doping concentration of said trap;
Said first doped region and said ion implanted region are formed first diode;
Said ion implanted region and said trap are formed second diode;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode; Wherein,
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap.
6. manufacturing approach according to claim 5 is characterized in that,
The isolated groove that the said trap of different said memory cells is isolated in generation, wherein, the degree of depth of said isolated groove is greater than the degree of depth of said trap.
7. manufacturing approach according to claim 5 is characterized in that,
The one-time programmable memory cell of said a plurality of double diode structures comprises the one-time programmable memory cell of the first double diode structure and the one-time programmable memory cell of the second double diode structure at least, wherein,
The one-time programmable memory cell of the said first double diode structure and the one-time programmable memory cell of the said second double diode structure are kept preset distance.
8. manufacturing approach according to claim 5 is characterized in that,
Said double diode structure comprises:
Type double diode structure or type double diode structure dorsad in opposite directions.
9. the programmed method of the disposable programmable memory of a double diode structure is characterized in that,
The one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms in said ion implanted region;
Said ion implanted region forms in said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode;
Said programmed method comprises:
On said word line, apply first voltage; On said bit line, apply second voltage; The diode breakdown that reverse breakdown voltage is little in said first diode and second diode is formed conducting resistance, and make the big diode current flow of reverse breakdown voltage in said first diode and second diode; Wherein,
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap.
10. programmed method according to claim 9 is characterized in that,
The difference of said first voltage and said second voltage is can be with the magnitude of voltage of the diode breakdown that reverse breakdown voltage is little in said first diode and second diode.
11. the read method of the disposable programmable memory of a double diode structure is characterized in that,
The one-time programmable memory cell of said double diode structure comprises:
First diode is formed by first doped region and ion implanted region;
Second diode is formed by said ion implanted region and trap; Wherein,
Said first doped region forms in said ion implanted region;
Said ion implanted region forms in said trap;
Said first doped region is different with the ion doping concentration of said trap;
Said first diode and said second diode are connected in series;
Said first diode is connected with word line, and said second diode is connected with bit line;
The reverse breakdown voltage of said first diode is different from the reverse breakdown voltage of said second diode;
The ionic type of said first doped region is identical with the ionic type of said trap;
The ionic type of said ion implanted region is different with the ionic type of the ionic type of said first doped region, said trap;
Said read method comprises:
On said word line, apply tertiary voltage; Whether on said bit line, apply the 4th voltage, detecting sense amplifier has electric current, if; Then represent the breakdown formation resistance of diode that reverse breakdown voltage is little in said first diode and second diode, be output as logical one; Otherwise, represent that the diode that reverse breakdown voltage is little in said first diode and second diode is not breakdown, output logic " 0 ".
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