CN101996975A - 内插器芯片及其制造方法 - Google Patents
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Abstract
本发明的目的是提供一种内插器芯片及其制造方法,其能够防止内插器芯片中的布线剥离。内插器芯片包括芯片安装区,在所述芯片安装区上通过由树脂制成的固定材料来安装半导体芯片。内插器芯片具有绝缘膜和在绝缘膜上形成的布线层。在与芯片安装区的边缘相对应的位置处,提供其中绝缘膜与布线层之间的粘合力增加的加强区。
Description
技术领域
本发明涉及一种安装半导体芯片的内插器芯片(interposer chip)及其制造方法,并且具体而言,涉及一种用于其中多个半导体芯片密封在一个封装中的SIP(系统级封装)结构中的内插器芯片及其制造方法。
背景技术
在半导体器件中,布线层形成在绝缘膜上。要求布线被形成为使得不会被剥离。
在文献1(日本专利公布2000-269215)和文献2(日本专利公布2004-282000)中公开了获得坚固半导体结构的技术。
此外,在文献3(日本专利公布2007-142333)中公开了一种半导体器件,其目的是获得一种半导体器件,在所述半导体器件中,下焊盘结构对压进(tucking)方向、剥离方向和水平方向上的力具有抵抗性。图1A是示出文献3中公开的半导体器件的焊盘部的透视平面图,以及图1B是示出图1中沿着C-C′横截面的截面图。该半导体封装包括在位于焊盘104下方的下焊盘区域中布置的加强图案(124、126、132、134、140、142和148)。加强图案的占用率在预定范围内,并且与预定芯片边缘部垂直的方向上的加强图案的占用率大于与预定芯片边缘部平行的方向上的加强图案的占用率。
通过这种方式,随着半导体器件中的功能升级和增加,诸如系统LSI(大规模集成),制造工艺的数目就会增加,并且变得难以实现高生产率。由该观点,SIP(系统级封装)成为焦点,其中,多个一般的半导体芯片密封在一个封装中。在SIP中,使用内插器芯片。提供该内插器芯片,用于改变从多个半导体芯片延伸的布线的次序(再布线),并且具有用于再布线的再布线层。
发明内容
图2A是示出SIP 30的平面图,以及图2B是示出SIP 30的截面图。如图2A和2B所示,SIP 30包括引线框架(1、7)、第一半导体芯片2、第二半导体芯片5和内插器芯片3。第一半导体芯片2经由固定材料4安装在引线框架的岛状部1上。第二半导体芯片5经由内插器芯片3安装在岛状部1上。内插器芯片3通过固定材料固定在岛状部1上,并且第二半导体芯片5也通过固定材料安装在内插器芯片3上。即使省略了图解,如上所述,在内插器芯片3中提供了再布线层。内插器芯片3通过接合线6连接到第一半导体芯片2、第二半导体芯片5和引线框架的引线端子7(封装引线端子)。此外,通过密封树脂8来密封岛状部1、第一半导体芯片2、内插器芯片3和半导体芯片5。
根据本发明人进行研究的结果,表明了内插器芯片3的布线会被剥离。此外,还表明了这种剥离与固定材料4和密封树脂8的结合有关。
图3A是示出半导体芯片3的截面图。参考图3A,将说明剥离部。如图3A所示,内插器芯片3包括基板11、在基板11上提供的层间绝缘膜12、在层间绝缘膜12上提供的布线层13、覆盖布线层13的覆盖绝缘膜14和在覆盖绝缘膜14上形成的钝化膜15。布线层13包括阻挡金属层(在图3A中未示出),并在阻挡金属层处接触层间绝缘膜12。在钝化膜15上,第二半导体芯片5通过固定材料4来固定。这里,布线层13从层间绝缘膜12剥离的部分是第二半导体芯片5的边缘的下部(图中的剥离部)。图3B示出该剥离部的电子显微照片。如图3B所示,在层间绝缘膜12与布线层13(以符号X示出)之间形成空隙,并且布线层13的阻挡金属层16从层间绝缘膜12剥离。
将说明为什么布线层容易在半导体芯片的边缘处剥离。图4A至图4D是示出在内插器芯片3上安装第二半导体芯片5的过程。如图4A所示,首先,用固定材料4将内插器芯片3固定在引线框架的岛状部1上。
接下来,如图4B所示,通过固定材料4将第二半导体芯片5固定在钝化膜15上。这里,使用树脂材料作为固定材料4。固定材料4涂覆在钝化膜15上。半导体芯片5布置在涂覆的固定材料4上,并且以预定温度来固化固定材料4。结果,第二半导体芯片5被固定。在安装第二半导体芯片5时,在第二半导体芯片5的边缘处增加强定材料4的量。
接下来,如图4C所示,通过密封树脂8密封岛状部1、内插器芯片3和第二半导体芯片5。在密封时,密封树脂8在预定温度处固化。在固化后冷却密封树脂8。
当固定材料4的固化温度过度低于密封树脂8的固化温度时,显示出很容易发生布线层的剥离。当固定材料4的固化温度低时,应考虑到:当在密封过程中对密封树脂8进行加热时,固定材料4通过加热向图中箭头标识Y所示的方向扩展(参见图4C)。另一方面,在密封过程中冷却时,应考虑到,扩展的固定材料4收缩。通过收缩,固定材料4将内插器芯片3的表面拉向图4D中的箭头标识Z示出的方向。结果,布线层13很容易从层间绝缘膜12剥离。由固定材料4产生的拉力在半导体芯片5的边缘处大,因为固定材料4的量增加了。从而,布线层13很容易在与半导体芯片5的边缘相对应的部分(图4D中X示出的部分)处剥离。
本发明的一个目的是提供一种内插器芯片及其制造方法,其能够防止内插器芯片3中布线的剥离。
其间,在文献3中,描述了用于加强结构的目的,但是没有描述关于内插器芯片3的内容。另外,在文献3中,描述了用于加强下焊盘结构的技术,但是没有描述用于防止半导体芯片边缘处的布线剥离的技术。也就是说,当用于剥离布线层的应力施加在除焊盘之外的区域时,在除焊盘之外的区域处不能防止布线层的剥离。此外,对于SIP的内插器芯片仅要求再布线层,并且提供用于加强的多层结构是不利的。
根据本发明的内插器芯片包括芯片安装区,并且半导体芯片通过由树脂制成的固定材料安装在芯片安装区上。内插器芯片包括绝缘膜和在绝缘膜上形成的布线层。加强区提供在与芯片安装区的边缘相对应的位置上,并且在加强区处增大了绝缘膜与布线层之间的粘合力。
根据本发明,由于绝缘膜与布线层之间的粘合力在芯片安装区的边缘处增加,所以即使固定材料收缩也能够防止布线层剥离。
根据本发明的半导体器件包括主基板、在主基板上安装的第一半导体芯片和通过内插器芯片在主基板上安装的第二半导体芯片。
根据本发明的方法是内插器芯片的制造方法。该内插器芯片包括芯片安装区,并且半导体芯片通过由树脂制成的固定材料安装在芯片安装区上。该方法包括:形成绝缘膜;在绝缘膜上形成布线层;以及在与芯片安装区的边缘相对应的位置处形成加强区。在加强区处,增加了绝缘膜与布线层之间的粘合力。
根据本发明的制造半导体器件的方法包括:利用固定材料在内插器芯片上安装半导体芯片,通过加热固化固定材料,通过由树脂制成的密封材料来密封半导体芯片以及通过加热来固化密封材料。固定材料的固化温度与密封材料的固化温度不同。
另一方面,根据本发明的制造半导体器件的方法包括:准备主基板,在主基板上安装第一半导体芯片,以及经由内插器芯片在主基板上安装第二半导体芯片。
根据本发明,提供一种内插器芯片及其制造方法,其能够防止内插器芯片中的布线剥离。
附图说明
从下面结合附图对某些优选实施例进行的描述,本发明的上述和其他目的、优点和特征将变得更明显,其中:
图1A是示出现有技术的平面图;
图1B是示出现有技术的截面图;
图2A是示出SIP的平面图;
图2B是示出SIP的截面图;
图3A是示意性地示出内插器芯片部的截面图;
图3B是内插器芯片的电子显微照片;
图4A是示出安装第二半导体芯片过程的截面图;
图4B是示出安装第二半导体芯片过程的截面图;
图4C是示出安装第二半导体芯片过程的截面图;
图4D是示出安装第二半导体芯片过程的截面图;
图5A是示出根据第一实施例的内插器芯片的透视平面图;
图5B是示出根据第一实施例的内插器芯片的截面图;
图6A是示出根据第一实施例的内插器芯片的制造方法的截面图;
图6B是示出根据第一实施例的内插器芯片的制造方法的截面图;
图6C是示出根据第一实施例的内插器芯片的制造方法的截面图;
图6D是示出根据第一实施例的内插器芯片的制造方法的截面图;
图6E是示出根据第一实施例的内插器芯片的制造方法的截面图;
图7A是示出根据第二实施例的内插器芯片的透视平面图;
图7B是示出根据第二实施例的内插器芯片的截面图;
图8A是示出根据第二实施例的内插器芯片的制造方法的截面图;
图8B是示出根据第二实施例的内插器芯片的制造方法的截面图;
图8C是示出根据第二实施例的内插器芯片的制造方法的截面图;
图8D是示出根据第二实施例的内插器芯片的制造方法的截面图;
图8E是示出根据第二实施例的内插器芯片的制造方法的截面图;
图9A是示出根据第三实施例的内插器芯片的透视平面图;
图9B是示出根据第三实施例的内插器芯片的截面图;
图10A是示出根据第三实施例的内插器芯片的制造方法的截面图;
图10B是示出根据第三实施例的内插器芯片的制造方法的截面图;
图10C是示出根据第三实施例的内插器芯片的制造方法的截面图;
图10D是示出根据第三实施例的内插器芯片的制造方法的截面图;
图10E是示出根据第三实施例的内插器芯片的制造方法的截面图;以及
图10F是示出根据第三实施例的内插器芯片的制造方法的截面图。
具体实施方式
(第一实施例)
参考附图,将说明根据本发明的第一实施例。如图2A和图2B所示的SIP,根据本实施例的半导体器件包括:引线框架(1,7)、第一半导体芯片2、第二半导体芯片5和内插器芯片3。由于半导体器件的全部构造与图2A和图2B示出的SIP相同,所以将省略详细的描述。在本实施例中,内插器芯片3的构造是创新的。
图5A是示出内插器芯片3的一部分的透视平面图。图5B是示出内插器芯片3的一部分的截面图,并且示出沿着图5A中的AA′的横截面。
如图5B所示,内插器芯片3具有基板31、层间绝缘膜32、布线层(34、36)、覆盖绝缘膜37和钝化膜38。
例如,使用硅基板作为基板31。
层间绝缘膜32形成在基板31的主面上。例如,使用SiO2层等作为层间绝缘膜32。
布线层(34、36)形成在层间绝缘膜32上。布线层(34、36)包括第一布线层34和第二布线层36。作为第一布线层34,可以使用诸如钨的、容易填充在通孔中的材料。作为第二布线层36,可以使用诸如铝的具有低电阻的材料,并且第二布线层36经由阻挡金属(Ti、TiN等)层被形成在层间绝缘膜32和第一布线层34上。
覆盖绝缘膜37覆盖布线层(34、36)。例如,使用等离子体氧化的氮化物膜作为覆盖绝缘膜37。
钝化膜38被提供在覆盖绝缘膜37上,并且保护布线层(34、36)和覆盖绝缘膜37。例如,使用聚酰亚胺树脂膜作为钝化膜38。
在钝化膜38上,通过固定材料4来固定第二半导体芯片5。使用通过加热而固化的热固树脂作为固定材料4。在第二半导体芯片5的边缘处,增加固定材料4的量。
如图5A所示,布线层(34、36)被布置成横跨其上安装有第二半导体芯片5的区域(芯片安装区)。布线层(34、36)的主要部分是第二布线层36。第二布线层36包括阻挡金属层(Ti、TiN、[Ta、TaN]等),并且经由阻挡金属层被形成在第一布线层34和层间绝缘膜32上。阻挡金属层与层间绝缘膜32之间的粘合力通常不太大。因而,如上所述,在第二半导体芯片5的边缘处,在密封过程之后冷却时,布线层会由于固定材料4的收缩而剥离。
在本实施例中,在提供布线层(34、36)的区域当中,加强区被提供在与第二半导体芯片5的边缘相对应的位置上。加强区是布线层(34、36)与层间绝缘膜32之间的粘合力大于周围区域中的粘合力的区域。
如图5B所示,在加强区中,多个通孔33(凸起)提供在层间绝缘膜32中。多个通孔33的底部被布置在层间绝缘膜中。即,多个通孔33没有达到基板31。多个通孔33填充有第一布线层34。第一布线层34是导电层,并且由容易填充在通孔中的材料(例如,钨等)形成。在加强区中,第二布线层36被提供在第一布线层34上。因而,在加强区中,第二布线层36没有接触层间绝缘膜32。在除了加强区之外的区域处,第二布线层36直接形成在层间绝缘膜32上。
由于多个通孔33填充有第一布线层34,所以布线层(34、36)不容易从层间绝缘膜32剥离。此外,在加强区中,容易从层间绝缘膜32剥离的第二布线层36没有直接接触层间绝缘膜32。从这些观点,布线层(34、36)不容易从层间绝缘膜32剥离。
随后,将说明根据本实施例的制造半导体器件的方法。图6A至图6E是示出根据本实施例的制造半导体器件的方法的截面图。
首先,如图6A所示,在基板31上形成层间绝缘膜32。然后,在层间绝缘膜32中形成多个通孔33。
接下来,如图6B所示,在层间绝缘膜32的整个表面上沉积第一布线层34。此时,用第一布线层34填充多个通孔33。
接下来,如图6C所示,通过光致抗蚀剂层35来掩蔽加强区,并且蚀刻第一布线层34。
接下来,如图6D所示,在整个表面上沉积第二布线层36,使得覆盖第一布线层34。之后,通过光致抗蚀剂来掩蔽需要的图案,并且蚀刻第二布线层36。结果,布线层(34、36)被形成为具有预定形状。
接下来,如图6E所示,按顺序沉积覆盖绝缘膜37(例如,等离子体氧化的氮化物膜)和钝化膜38,使得第二布线层36被覆盖。此外,在覆盖绝缘膜37和钝化膜38中形成开口作为用于接合的窗口。结果,获得内插器芯片3。
用于根据本实施例的制造半导体器件的方法与图4A至图4D示出的制造半导体器件的方法相似。即,第一半导体芯片2被布置在引线框架的岛状部上。另外,由上面提到的方法获得的内插器芯片3经由固定材料4被布置在该岛状部上。此外,第二半导体芯片5经由固定材料4被布置在钝化膜38上。之后,通过密封树脂8密封第一半导体芯片2和第二半导体芯片5。
此时,即使固定材料4的固化温度与密封树脂8的固化温度不同,由于布线层(34、36)在加强区中被牢固地附着到层间绝缘膜32,所以防止布线层(34、36)被剥离。也就是,即使布线图案被布置在半导体芯片下方,也能够防止由固定材料4的密封应力或拉力引起的布线层剥离。
(第二实施例)
随后,将说明第二实施例。在本实施例中,布线层(34、36)的构造和形成方法是由第一实施例的构造和形成方法变化而来的。由于其他点与第一实施例相同,所以将省略详细的描述。
图7A是示出根据本实施例的内插器芯片3的透视平面图,以及图7B是示出沿着图7A中的AA′的横截面的截面图。如图7A和图7B所示,第一布线层34不仅提供在加强区处,而且提供在除了加强区之外的区域处。第二布线层36被提供在第一布线层34上,并且没有接触层间绝缘膜32。
图8A至图8E是示出根据本实施例的内插器芯片3的制造方法的截面图。
首先,如图8A所示,在基板31上形成层间绝缘膜32,并且多个通孔33被形成使得不达到基板31。
接下来,如图8B所示,通过沉积用于填充通孔的材料(例如,钨)来形成第一布线层34。多个通孔33填充有第一布线层34。
随后,如图8C所示,沉积以铝作为例子的第二布线层36。
接下来,如图8D所示,用光致抗蚀剂35来掩蔽布线层(34、36)所需的部分,并且在一个工艺中蚀刻第一布线层34和第二布线层36这二者。蚀刻之后,剥离光致抗蚀剂35,并且获得布线图案。
之后,如图8E所示,沉积覆盖绝缘膜37(例如,等离子体氧化的氮化物膜)和钝化膜38,并且开口被提供作为用于接合的窗口。结果,获得了根据本实施例的内插器芯片3。
根据本实施例,容易剥离的第二布线层36不直接接触层间绝缘膜32,在除了加强区之外的位置中也不直接接触层间绝缘膜32。因而,完全防止布线层的剥离。
此外,在本实施例中,由于布线层的厚度大,所以蚀刻布线层的条件比第一实施例更严格(例如,增加蚀刻时间)。因而,要求光致抗蚀剂35具有高抗蚀性。然而,通过增加光致抗蚀剂35的厚度可以解决这个问题。
(第三实施例)
随后,将说明第三实施例。在本实施例中,在加强区中的布线层的构造是由上面提到的实施例的布线层构造改变而来的。由于其他点与上面提到的实施例相同,所以将省略详细的描述。
图9A是示出根据本实施例的内插器芯片3的透视平面图,以及图9B是示出沿着图9A中的AA′的横截面的截面图。
如图9A和图9B所示,在本实施例中,在加强区中没有提供第二布线层36。在加强区的外部,第二布线层36接触第一布线层34。在加强区中,在第一布线层34上形成覆盖绝缘膜37和钝化膜38。
图10A至图10E是示出根据本实施例的内插器芯片3的制造方法的截面图。
首先,如图10A所示,在基板31上形成层间绝缘膜32,并且多个通孔33被形成为不达到基板31。
接下来,如图10B所示,通过在整个表面上沉积用于通孔填充的材料(例如,钨)来形成第一布线层34。用第一布线层34填充多个通孔33。
接下来,如图10C所示,用光致抗蚀剂35来掩蔽加强区,并且在没有掩蔽的部分中蚀刻第一布线层34。
接下来,如图10D所示,剥离光致抗蚀剂35,并且沉积第二布线层36(例如,A1)。
接下来,如图10E所示,在利用光致抗蚀剂掩蔽加强区的情况下,蚀刻第二布线层36。在蚀刻之后,剥离光致抗蚀剂以获得布线图案。由于第一布线层34是导电层,所以即使第二布线层36从加强区被移除,电信号也能够通过加强区。
接下来,如图10F所示,形成覆盖绝缘膜37和钝化膜38,并且形成开口作为用于接合的窗口。结果,获得了根据本实施例的内插器芯片3。
根据本实施例,在加强区中,没有提供容易剥离的第二布线层36。第二布线层36远离由固定材料4施加应力的位置。因而,完全防止布线层的剥离。
此外,与上面提到的实施例相比,在加强区中,具有高导电性的材料不能用作第一布线层36,并且整个布线层容易具有高电阻。然而,根据产品的操作速度,这是可接受的。
Claims (18)
1.一种内插器芯片,包括:
芯片安装区,半导体芯片经由由树脂制成的固定材料安装在所述芯片安装区上;
绝缘膜;
布线层,所述布线层形成在所述绝缘膜上;以及
加强区,所述加强区被提供在与所述芯片安装区的边缘相对应的位置处,
其中,所述加强区中的所述绝缘膜与所述布线层之间的粘合力大于周围区域中的粘合力。
2.根据权利要求1所述的内插器芯片,其中,多个通孔被提供在所述加强区中的所述绝缘膜中,并且所述多个通孔填充有所述布线层。
3.根据权利要求2所述的内插器芯片,其中,所述布线层包括:
第一布线层,所述第一布线层填充在所述多个通孔中;以及
第二布线层,所述第二布线层被提供成与所述第一布线层接触,并且
其中,所述第二布线层被提供成不与所述加强区中的所述绝缘膜接触。
4.根据权利要求3所述的内插器芯片,其中,所述第二布线层被形成在所述加强区中的所述第一布线层上。
5.根据权利要求3所述的内插器芯片,其中,所述第二布线层不被提供在所述加强区中并且在所述加强区的外部与所述第一布线层接触。
6.根据权利要求3所述的内插器芯片,其中,所述第一布线层包括钨成分,并且所述第二布线层包括铝成分。
7.根据权利要求1所述的内插器芯片,其中,所述半导体芯片经由由树脂制成的密封材料密封,并且所述密封材料和所述固定材料的固化温度彼此不同。
8.一种半导体器件,包括:
主基板;
第一半导体芯片,所述第一半导体芯片安装在所述主基板上;以及
第二半导体芯片,所述第二半导体芯片经由内插器芯片安装在所述主基板上,
其中,所述内插器芯片包括:
芯片安装区,所述第二半导体芯片经由由树脂制成的固定材料安装在所述芯片安装区上;
绝缘膜;
布线层,所述布线层形成在所述绝缘膜上;以及
加强区,所述加强区被提供在与所述芯片安装区的边缘相对应的位置处,并且
其中,在所述加强区中的所述绝缘膜与所述布线层之间的粘合力大于周围区域中的粘合力。
9.一种内插器芯片的制造方法,所述内插器芯片具有芯片安装区,并且半导体芯片经由由树脂制成的固定材料安装在所述芯片安装区上,所述方法包括:
形成绝缘膜;
在所述绝缘膜上形成布线层;以及
在与所述芯片安装区的边缘相对应的位置处形成加强区,
其中,所述加强区是所述绝缘膜与所述布线层之间的粘合力大于周围区域中的粘合力的区域。
10.根据权利要求9所述的内插器芯片的制造方法,其中,所述形成布线层包括:
在所述绝缘膜中形成多个通孔;以及
沉积所述布线层,以便填充所述多个通孔。
11.根据权利要求10所述的内插器芯片的制造方法,其中,所述沉积所述布线层包括:
形成第一布线层,以便填充所述多个通孔;以及
形成第二布线层,以便与所述第一布线层接触,并且与所述加强区中的所述绝缘膜不接触。
12.根据权利要求11所述的内插器芯片的制造方法,其中,所述形成所述第一布线层包括:
在所述绝缘膜的整个表面上沉积所述第一布线层;以及
蚀刻沉积的所述第一布线层,以具有预定形状,以及
其中,所述形成所述第二布线层包括:
在所述蚀刻沉积的所述第一布线层之后,在所述绝缘膜的所述整个表面上沉积所述第二布线层;以及
蚀刻沉积的所述第二布线层,以具有预定形状。
13.根据权利要求12所述的内插器芯片的制造方法,其中,所述蚀刻所述第二布线层包括,蚀刻所述第二布线层,使得所述第二布线层保留在所述第一布线层上。
14.根据权利要求12所述的内插器芯片的制造方法,其中,所述蚀刻所述第二布线层包括,蚀刻所述第二布线层,使得所述第二布线层从所述加强区被移除,并且在所述加强区的外部与所述第一布线层接触。
15.根据权利要求14所述的内插器芯片的制造方法,其中,所述蚀刻所述第一布线层和所述蚀刻所述第二布线层在一个工艺中进行。
16.根据权利要求11所述的内插器芯片的制造方法,其中,所述第一布线层包括钨成分,以及所述第二布线层包括铝成分。
17.一种半导体器件的制造方法,包括:
经由由树脂制成的固定材料在内插器芯片上安装半导体芯片;
在所述安装之后,通过加热来固化所述固定材料;
在所述固化所述固定材料之后,通过由树脂制成的密封材料来密封所述半导体芯片;以及
通过加热来固化所述密封材料,
其中,所述内插器芯片包括:
芯片安装区,所述半导体芯片安装在所述芯片安装区上;
绝缘膜;
布线层,所述布线层形成在所述绝缘膜上;以及
加强区,所述加强区被提供在与所述芯片安装区的边缘相对应的位置处,
其中,所述加强区中的所述绝缘膜与所述布线层之间的粘合力大于周围区域中的粘合力,并且
其中,所述固定材料的固化温度和所述密封材料的固化温度彼此不同。
18.一种半导体器件的制造方法,包括:
准备主基板;
在所述主基板上安装第一半导体芯片;以及
经由内插器芯片在所述主基板上安装第二半导体芯片,
其中,所述内插器芯片包括:
芯片安装区,半导体芯片经由由树脂制成的固定材料安装在所述芯片安装区上;
绝缘膜;
布线层,所述布线层形成在所述绝缘膜上;以及
加强区,所述加强区被提供在与所述芯片安装区的边缘相对应的位置处,
其中,所述加强区中的所述绝缘膜与所述布线层之间的粘合力大于周围区域中的粘合力,以及
其中,所述固定材料的固化温度和所述密封材料的固化温度彼此不同。
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CN113644046A (zh) * | 2021-07-19 | 2021-11-12 | 太极半导体(苏州)有限公司 | 一种nand闪存芯片的边缘封装工艺及其结构 |
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US8159073B2 (en) | 2012-04-17 |
JP5456411B2 (ja) | 2014-03-26 |
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